Device Design and Optimization Considerations for Bulk FinFETs

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 2, FEBRUARY 2008 609

Device Design and Optimization Considerationsfor Bulk FinFETs

C. R. Manoj, Meenakshi Nagpal, Dhanya Varghese, and V. Ramgopal Rao, Senior Member, IEEE

Abstract—Fabrication of FinFETs using bulk CMOS instead ofsilicon on insulator (SOI) technology is of utmost interest as it re-duces the process costs. Using well-calibrated device models and3-D mixed mode simulations, we show that bulk FinFETs can beoptimized with identical performances as that of SOI FinFETs.Optimized bulk FinFETs are compared with the correspondingSOI FinFETs for a range of technology nodes using an extensivesimulation and design methodology. Further, we extend the conceptof body doping in bulk FinFETs to the case of lightly doped finsunlike the heavily doped fin cases reported earlier. The optimumbody doping required for bulk FinFETs, and its multiple advan-tages are also systematically evaluated. We also show that deviceparasitics play a crucial role in the optimization of nanoscale bulkFinFETs.

Index Terms—Bulk FinFET, device parasitics, fringe capaci-tance, inverter delay, SOI FinFET.

I. INTRODUCTION

F INFETS [1] are the most promising candidates for thefuture ultrashort channel transistors owing to their supe-

rior scalability over the conventional planar transistors. Conven-tionally, FinFETs are fabricated on the SOI substrates [2], [3].However, SOI wafers have disadvantages with respect to theirself-heating issues, cost, defect density, etc., when compared tothe bulk Si substrates [4]. Bulk Si wafers, in addition to elimi-nating most of the disadvantages with SOI, are compatible withthe existing planar CMOS process technologies, which is animportant consideration. The bulk FinFET technologies werefirst reported a few years ago and most of the published litera-ture [5]–[8] on bulk FinFETs is mainly on the optimization ofthe individual device level dc characteristics. Also, there are re-ports of fully integrated static random access memory (SRAM)cells using bulk FinFETs [9]. Structurally bulk FinFETs and SOIFinFETs are similar except for the fact that bulk FinFETs usean isolation oxide layer (SiO2) (Tins) between the gate electrodebottom and the bulk Si surface to avoid gate electrode contactingthe Si wafer (as shown schematically in Fig. 1). Most of the bulkFinFET processes reported using a large isolation oxide to re-duce the parasitics. However, this will cause a significant portionof the actual fin height not to be available for the effective de-

Manuscript received October 26, 2007. This work was supported in part bythe Intel Corporation, in part by the Department of Science and Technology(DST), Government of India under Grant Swarnajayanti Fellowship scheme,and in part by the International Business Machines (IBM) Faculty Award. Thereview of this paper was arranged by Editor M. J. Kumar.

The authors are with the Department of Electrical Engineering, IndianInstitute of Technology (IIT)-Bombay, Mumbai 400076, India (e-mail:[email protected]; [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2007.912996

Fig. 1. 3-D view of simulated bulk FinFET showing the patterned 3-D gateand bulk doping layer.

vice width (Weff). Also, most of the reported bulk FinFETs use aheavy fin doping to control the OFF-state leakage, which causesa significant mobility degradation.

In this paper, we present the optimization aspects of bulk Fin-FET structures and also report a comparison of the SOI FinFETswith the bulk FinFETs for the first time, using extensive 3-D de-vice as well as circuit simulations. The paper is organized infour sections. In Section II, we discuss the technology computeraided design (TCAD) tool calibration and the verification of thesame by matching the experimental and simulation results. InSection III, we discuss the effect of different possible fin dopingprofiles to get the best device performance. In Section IV, wediscuss the optimization of Tins from the dc performance per-spective. In Section V, we compare the transient performance ofSOI and bulk FinFETs.

II. TCAD TOOL CALIBRATION

For FinFET simulations, the TCAD tools need to be prop-erly calibrated as current flow in actual FinFETs will be dom-inated by 〈1 1 0〉 plane. Also, the default contact resisitvityand mobility values are to be fine-tuned to match with that ofthe actual experimental data. So the calibration of the TCADtool has been done by matching both the ac and the dc char-acteristics of fabricated FinFETs [10], [11] with that of thesimulated devices. The contact resisitvity value chosen for thesimulations is 1.45 × 10−7 Ω · cm2 . Calibrated drift-diffusionmodels are used for all the technology nodes [12]. For themobility, we have used the “Lombardi” model with calibrated

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610 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 2, FEBRUARY 2008

TABLE IDIMENSIONS USED FOR 3-D BULK FINFET SIMULATIONS

model parameters. The matching has been mainly achieved bytuning the contact resisitvity and mobility values. From the cal-ibration exercise, we find that with the tuned parameters, the ON

current is considerably lower than the case when default modelparameters were used. This clearly shows that proper calibrationof the TCAD model parameters is very essential for meaning-ful FinFET simulations. Also, it was found that tuning doesnot affect the subthreshold behavior as only the mobility andcontact resisitvity are used for matching the experimental andthe simulation results. We use the calibrated model parametersfor all the TCAD FinFET simulations reported in this paper.To further verify the validity of our TCAD tuning approach,we have simulated a 13-stage FinFET-based ring oscillator, us-ing the lookup table (LUT) approach [14] by using the ac anddc data generated from the calibrated TCAD tool set. Here thesame device dimensions as that of the fabricated device wereused. For this study, all the device level parasitics are capturedin the calibrated simulations where as the parasitics due to lay-outs were extracted and added to the LUT via postprocessing.The value of the extracted parasitic resistance was 390 Ω andthat of parasitic capacitance was 0.01 fF, as extracted from thelayout data for inverters. The exact matching of the stage delayof the simulation and experimental results further validates thecalibration of the TCAD tool set.

III. DC DEVICE SIMULATIONS

The 3-D perspective view of the bulk FinFET simulation isshown in Fig. 1. To meet the requirements of international tech-nology roadmap for semiconductors (ITRS), 3-D simulationshave been performed for a wide range of proposed technologynodes (see Table I) with proportionate device dimensions andwork function values [13]. Sufficient mesh refinements were ap-plied to the fin region and the inversion layer regions to capturethe inversion layer quantization. The corner effects in these de-vices are appropriately taken care of by implementing the cornerrounding approaches [15]. In the bulk FinFETs, ensure that a

Fig. 2 (a) Id − Vg comparison for different doping profiles (for device withLg = 65 nm). (b) Plot showing the different doping profiles used. Profile (i) iswith heavily doped channel and a heavier lower fin doping, profile (ii) is withundoped/moderately doped channel and a heavier lower fin doping, and profile(iii) is with undoped/moderately doped channel and a heavier lower fin dopingextended into the bulk substrate.

portion of the fin at the bottom is not under the gate controland is covered by an isolation oxide (Tins). We use the term“upper fin” to represent the fin region which is actually con-trolled by the gate and “lower fin” to represent the fin regionwhich is covered by the Tins. The proposed bulk FinFET struc-tures [6]–[8] use a heavily doped upper fin/channel doping anda heavier lower fin doping to control the short-channel effects(SCEs). This corresponds to the profile case (i) as shown inFig. 2(b). However, this results in a channel mobility degrada-tion causing a lower ION/IOFF ratio. We study the effect due tomodified doping profiles (ii) and (iii) and compare their advan-tages over profile (i), shown in Fig. 2(a). In case (ii) we useundoped/moderately doped channel with a heavier doping inthe lower fin region. In case (iii), we use undoped/moderatelydoped channel with the heavier doping in the lower fin regionthat is extended deeper into the bulk. From Fig. 2(b), we can seethat too low a value of body doping (i.e. profile (ii) in the lowerfin region) leads to an increased IOFF owing to punch through.Also, we can see that the doping profiles (ii) and (iii) givebetter IOFF when compared to the conventional doping profiles.Note that in both the cases, the heavier doping in the lower finregion is lower compared to what has been reported [6]. As

MANOJ et al.: DEVICE DESIGN AND OPTIMIZATION CONSIDERATIONS FOR BULK FinFETs 611

Fig. 3. Plot showing optimum body doping value. (a) DIBL and SS. (b) IONand IOFF.

has been shown, the conventional profiles give rise to a higherIOFF value due to the band-to-band-tunneling (BTBT) currentsowing to their heavier doping concentrations. Also, it is clearthat case (iii) is superior to all other doping profiles as it givesthe lowest IOFF among all the cases considered. Further, onecan notice that we get almost a factor of 2 increase in ION withthe optimized doping profiles. Therefore, this paper establishesthat one can use undoped/lightly doped fins with bulk FinFETtechnologies, still keeping the SCE under control by using aheavier body doping. However, an increase in body doping con-centration does not give a higher ION/IOFF ratio, contrary towhat is expected. This is because initially when we increasethe body doping, IOFF decreases exponentially (although ION

also decreases linearly). But for too high values of body doping(such as above 1018 /cm3), the IOFF shows a reverse trend. Thisis because of the enhanced BTBT currents owing to heavy S/Ddoping (1020 /cm3). Hence, the body doping needs to be opti-mally chosen to get the best ION/IOFF ratio as shown in Fig. 3(b).From our extensive simulations, we identify this optimum dop-ing value to be approximately 1 × 1018 cm−3 . Fig. 3(a) showsthe corresponding variation in drain-induced barrier lowering(DIBL) and subthreshold swing with body doping levels. Simu-lations have been done for a range of technology nodes from 65

Fig. 4. Comparison of OFF-state leakage of SOI and bulk FinFETs, for differenttechnology nodes ranging from 65 to 22 nm node. It shows that with optimumbody doping bulk off current can be brought closer to that of SOI FinFETs.

Fig. 5. Plot showing optimum insulator height (Tins) for IOFF with and with-out body doping approaches, at 32 nm node. It can be seen that, IOFF is relativelyinsensitive to the value of Tins in case of body doped bulk FinFETs.

to 22 nm. Simulations show that with the optimal body doping,IOFF of the bulk FinFET can be made comparable to that of theSOI FinFETs even with undoped fins (see Fig. 4) making thebulk FinFET technology a strong candidate for the future scaledCMOS nodes.

IV. OPTIMIZATION OF THE ISOLATION OXIDE THICKNESS (TINS)

In the literature, we find that the Tins is kept thick enoughto avoid the parasitic inversion channel formation in the bulkunderneath the gate region. However, increasing the Tins causesa significant portion of the fin height not to be available foreffective device width (Weff). For a given total fin height (Hfin),this will cause a significant performance degradation in bulkFinFETs, when compared to the SOI FinFETs. We studied inthis paper the effect of Tins on dc and transient performanceof bulk FinFETs. By using a heavy body doping region in thebulk Si just underneath the fin, one can prevent inversion regionformation, even when the Tins thickness is decreased to about20 nm. Fig. 5 shows the variation in total IOFF with Tins for anundoped and body doped bulk FinFETs. If no body doping isapplied, IOFF will increase for a decrease in the Tins thickness.


This is due to the parasitic channel formation in the bulk Sijust underneath the gate region. Further, IOFF also shows an in-crease for large Tins values. This is due to the fact that when Tins

thickness is high, the field lines from the bottom portion of thegate electrode terminate on the lower fin region causing the sub-channel leakage to increase. This has been verified by plottingthe electric field values at different depths along the “lower fin”direction as a function of Tins. This confirms that for very largeTins thickness, electric field in the lower fin region increasessignificantly contributing to an additional leakage component.However, with a heavier body doping, IOFF essentially remainsconstant for a broader range of Tins values. This means that wecan have a smaller value for the Tins, allowing for the best useof total fin height for optimization of the effective device width.However, the lower limit of Tins will come from the additionalparasitics due to the parallel plate capacitance contributed by theTins thickness, which increases with the decrease in Tins value.From simulations we find that the minimum value for Tins with-out significantly affecting the transient delay is approximately20 nm.

In Fig. 6, different parasitic capacitance components areschematically represented that must be taken into account whileoptimizing the Tins thickness. All these capacitance values havebeen extracted through detailed TCAD simulations. The variousparasitic capacitance components are (1) Cof, the outer fringecapacitance, which is due to the field lines terminating in theS/D regions and bulk from the vertical side walls of the gateelectrode [see Fig. 6(a)], (2) Cpar, the parallel plate capaci-tance, which is due to the field lines terminating from the lowerface of the gate electrode and terminating on the top bulk Sisurface, and (3) Cif, the inner fringe capacitance, which is dueto the field lines originating from the lower face of the gateelectrode and terminating in the lower fin region [see Fig. 6(b)].When Tins is very small, Cpar will be higher compared to the Cif.But when the Tins thickness becomes larger, Cif will increase asmore field lines from the bottom of the gate electrode divergeout to the lower fin portion. Fig. 7 shows, the variation of thesecapacitance parasitics with Tins. As expected, Cif increases lin-early with the Tins value. Sum of Cof and Cpar will decreaselogarithmically and saturate to a constant value.

V. BULK AND SOI FINFET INVERTER 3-D TRANSIENT

SIMULATIONS

Till date, all the reports on bulk FinFETs were on their dcperformance metrics. We have done the full 3-D Mixed Modeinverter level simulations for equivalent bulk and SOI FinFETs.Here each inverter is assumed to drive an identical inverter, sothat the fan out of the stage is unity. For this case, we havemaintained a constant Weff (effective width) of the bulk andSOI devices by making the actual fin height of the bulk devicestaller (by the factor Tins) compared to that of the SOI FinFETs.This was required since, for any meaningful comparison of thetransient performance of the two, we need to keep the iso-ION

condition. To accurately compare the transient results of the bulkand SOI FinFET-based inverters, one needs to ensure that theId − Vg of the devices (both PMOS and NMOS) are matched.

Fig. 6. (a) Plot showing the outer fringe capacitance through the spacer (Cof)and the parallel plate capacitance (Cpar) below the gate electrode in the bulkregion. (b) Plot showing the inner fringe capacitance, (Cif), due to the field linesoriginating from the bottom of the gate electrode and terminating on the lowerfin region.

Fig. 7. Plot showing the variation of the parasitic capacitances with increasinginsulator height (Tins).

This is required because, even if the IOFF, sub-threshold slope(SS), DIBL, etc., are all matched, a slight change in the ION

can give erroneous delay values. This is essential since the pur-pose of this part of the study is to understand the parasitics inbulk FinFETs. With this objective in mind, we did a perfect


matching of the Id − Vg of all four devices used in the invertermixed mode simulations. From 3-D mixed mode transient sim-ulations, we find that the delay difference between SOI and bulkFinFETs is <5% for sufficiently large fin heights. This is insharp contrast to the conventional notion that SOI devices havea 30% speed advantage at the device level compared to theirplanar CMOS counterparts [16]. The reason for the diminish-ing SOI advantage in FinFETs is the vertical nature of the fins.In FinFETs since the Weff is essentially contributed by the finheight, the S/D junction capacitance is considerably reducedeven for the bulk FinFETs, unlike their planar counterparts. Inplanar MOSFETs, the S/D junction capacitances are given by theexpression

CS/D = WjEjCj + 2(Wj + Lj )Cjsw (1)

where Wj and Lj are the width and length of the S/D junctions,respectively, Cj is the bottom junction capacitance (in contactwith the bulk region), and Cjsw is the side-wall perimeter relatedcapacitance. For the FinFETs, the contribution from the bottomto the junction capacitance (Cjn ) is minimal, even for the bulkFinFETs. We have performed these simulations for a range offin aspect ratios ranging from 1 to 5 and found improved per-formance for higher values of the aspect ratio, as expected. Theresults are shown in Fig. 8(a). For lower fin aspect ratios, thefraction of the Weff contacting the Si bottom region increases,thus causing a reduction in the performance advantage for bulkFinFETs. This clearly shows that it is the vertical nature of thefin that is responsible for the observed performance advantagein bulk FinFETs.

In order to gain a further insight into the bulk FinFEToptimization, we did a simple layout-based calculation asfollows. Say, for a Weff of bulk FinFET that is 130 nm,given by 2Hfin + Wfin, the equivalent planar transistor widthwould be 130 nm. The FinFET and the corresponding planartransistor S/D layout/footprint are shown in Fig. 9. From theplanar transistor layout, one can calculate the S/D junctionarea as Apl = 123 nm × 130 nm = 15 990 nm2 . For the caseof bulk FinFET, with an equivalent Weff, as per the layoutprovided in Fig. 9, the area of S/D will be Aff = area underthin fin region + area underthe wider fin region = (48 × 10) +(75 × 50) = 4230 nm2 . Therefore, the ratio of the S/D junctionarea of FinFET to that of equivalent planar FET (i.e., Aff /Apl)will be roughly 0.26, corresponding to an approximately 75%decrease in the junction capacitance between the planar and theFinFET layouts. This layout rule-based calculation, in additionto the advanced 3-D device/circuit simulations for FinFETspresented in this paper, show that it is the vertical nature of thefin that is responsible for the improved transient performanceobserved in bulk FinFETs.

We have also repeated these simulations for the case, wherethe total fin height is kept constant for both the bulk and SOIFinFETs. This would mean that, for a given value of fin height,the Weff per fin in the case of bulk FinFETs will be lower com-pared to the SOI FinFETs, due to the isolation oxide thicknessTins at the bottom of the fin. Here the delays of the two typesof FinFETs are compared for a wide range of total iso-effectivewidth (Weff) values. For this case, both SOI and bulk FinFETs

Fig. 8 (a) Plot showing the variation of the inverter delay of SOI and bulkFinFETs with different fin heights (32 nm node). (b) Plot showing the inverterdelay with comparison between bulk and SOI FinFETs under various conditionssuch as (a) SOI delay with the same number of fins as bulk, (b) bulk delay withadditional number of fins added to recover the loss due to Tins height and (c)bulk delay where effective fin height is assumed to be same as that of SOI (i.e.having equal number of fins as bulk).

Fig. 9. S/D foot print/layout of bulk FinFET with Weff = 130 nm and thatof the corresponding equivalent planar MOSFET (i.e. with Weff = 130 nm), at32 nm node.


are assumed to have an Hfin = 55 nm and Wfin = 10 nm so thatWeff = 120 nm. Then, we compare the delays of both types ofFinFETs for various total values of Weff (i.e., 120, 240, 360 nm,etc.). Note that, in order to achieve a constant total iso-Weff,one needs a larger number of fins for the case of bulk Fin-FETs as compared to the SOI FinFETs. This is because of thelower Weff per fin available in the case of bulk FinFETs dueto Tins. This would mean that, in order to achieve an effec-tive total device width with bulk FinFETs, one would need alarger number of fins, and hence a larger layout area. This isexpected, since the fin height is kept constant for this case forboth the bulk and SOI FinFETs. Fig. 8(b) shows the delay com-parison of SOI and bulk FinFETs with iso-Weff condition. Herethe delay of the bulk FinFET is slightly deteriorated from thatof SOI case, unlike the result shown in Fig. 8(a). The reasonfor the degradation in the delay is due to the additional para-sitics owing to the increased number of fins in the bulk FinFETcase, to meet the iso-Weff condition. Most of the additionalparasitics (due to increased number of fins) come from the ad-ditional running of the gate metal in the pitch region betweenthe two fins [17]. In this study, the fin pitch has been assumedto be 150 nm to meet the ITRS specifications. This is becausethe gate thickness (Tg ) has to be at least twice the channellength (i.e., Tg ∼ 60 nm for 32-nm-node) and we need to ac-commodate minimum of 2Tg between the fins. Hence the pitchis assumed to be 150 nm. From the simulation study it can beconcluded that, in a more realistic situation, where we need touse additional number of fins to get the same Weff, parasitics areexpected to affect the delay by about 10%–15% in the case bulkFinFETs.

VI. CONCLUSION

With careful body doping optimization it has been shown thatthe bulk FinFETs can be scaled down to the 22-nm-technologynode with performance comparable to the SOI technologies.The parasitic effects in bulk FinFETs have been systematicallyinvestigated using extensive device/circuit simulations with op-timized TCAD tools. This paper shows that after careful opti-mization, bulk FinFETs offer a promising alternative to the SOIFinFETs for future low-power high-performance applications.

ACKNOWLEDGMENT

The authors wish to acknowledge Interuniversity Microelec-tronics Center (IMEC) Belgium and Synopsys Inc., for provid-ing the FinFET experimental data and “Sentaurus” TCAD toolsuite, respectively.

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[5] T. Park, S. Choi, D. H. Lee, J. R. Yoo, B. C. Lee, J. Y. Kim, C. G Lee,K. K. Chi, S. Park, U. I. Chune, J. T. Moon, E. Yoon, and J. H. Lee,“Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Siwafers,” in VLSl Symp. Tech. Dig., 2003, pp. 135–136.

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[17] H. Zhao, N. Agrawal, R. Javier, S. C. Rustagi, M. Jurczak, Y.-C. Yeo,and G. S. Samudra, “Simulation of multiple gate FinFET device gatecapacitance and performance with gate length and pitch scaling,” in Proc.SISPAD 2006, pp. 251–255.

C. R. Manoj received the B.Tech. degree in elec-tronics and communication from the College of Engi-neering, Trivandrum, India, in 1995, and the M.Tech.degree in microelectronics in 2002 from the IndianInstitute of Technology (IIT)-Bombay, Mumbai,India, where he is currently working toward thePh.D. degree in electrical engineering, with microelectronics as the area of specialization.

During 1996–1997, he was a Deputy Engineer inBharat Electronics Limited (BEL), Bangalore, India.He is currently a Senior Lecturer in the National Insti-

tute of Technology (NIT), Calicut, India. His current research interests includethe area of novel CMOS devices such as FinFETs.


Meenakshi Nagpal received the B.Tech. degree inelectronics and communication from Rajasthan Uni-versity, Jaipur, India, in 2002, and the M.Tech. degreein microelectronics from the Indian Institute of Tech-nology (IIT)-Bombay, Mumbai, India, in 2007.

She is currently with Cypress Semiconductors,Hyderabad, India. Her current research interestsinclude nanoscale CMOS device simulation andcharacterization.

Dhanya Varghese received the B.Tech. degree in electronics and communica-tion engineering from the National Institute of Technology, Calicut, India, in2005, and the M.Tech degree in microelectronics from the Indian Institute ofTechnology (IIT)-Bombay, Mumbai, India, in 2007. She is currently workingtoward Ph.D. at the School of Electrical and Computer Engineering, PurdueUniversity, West Lafayette, IN.

Her current research interests include simulation and modeling of nanoscaledevices.

V. Ramgopal Rao (M’98–SM’02) received theM.Tech. degree from the Indian Institute of Tech-nology (IIT)-Bombay, Mumbai, India, in 1991, andthe Dr. Ing. degree from the Faculty of Elec-trical Engineering, Universitaet der BundeswehrMunich, Munich, Germany, in 1997, both in microelectronics.

During 1997–1998 and 2001, he was a VisitingScholar with the Electrical Engineering Department,University of California, Los Angeles. He is currentlya Professor in the Department of Electrical Engineer-

ing, IIT-Bombay, where he is also the Chief Investigator for the Centre for Na-noelectronics Project, besides being the Principal Investigator for many ongoingsponsored projects funded by various multinational industries and governmentagencies. His current research interests include physics, technology, and char-acterization of silicon CMOS devices for logic and mixed-signal applications,bio-microelectromechanical systems (MEMS), and nanoelectronics. He is theauthor or coauthor of more than 180 publications in refereed international jour-nals and conference proceedings, and holds two patents. He is also a workinggroup member set up by the Ministry of Communications and Information Tech-nology, Government of India, on nanotechnology.

Prof. Rao is a Fellow of the Indian National Academy of Engineering andthe Institution of Electronics and Telecommunication Engineers (IETE). Hereceived the Shanti Swarup Bhatnagar Prize in Engineering Sciences in 2005for his contribution to the field of electron devices. He also received the Swar-najayanti Fellowship Award for 2003–2004, instituted by the Department ofScience and Technology, Government of India, and is a recipient of the 2007 In-ternational Business Machines Corporation (IBM) Faculty Award. He is the Ed-itor for the IEEE TRANSACTIONS ON ELECTRON DEVICES in the CMOS devicesand technology area and is a Distinguished Lecturer (DL) of the IEEE ElectronDevices Society. He was the organizing committee Chair for the 17th Interna-tional Conference on very-large-scale integration (VLSI) design and the 14thInternational Workshop on the Physics of Semiconductor Devices and serveson the program/organizing committees of various international conferences in-cluding the IEEE Asian Solid-State Circuits Conference, the IEEE Conferenceon Nano-Networks, the Association for Computing Machinery (ACM)/IEEEInternational Symposium on Low Power Electronics and Design, the 11th IEEEVLSI Design and Test Symposium among others.

He was the Chairman of the IEEE Antennas and Propagation/Electron De-vices (AP/ED) Bombay Chapter during 2002–2003 and currently serves on theexecutive committee of the IEEE Bombay Section besides being the Vice-Chairof the IEEE Asia-Pacific Regions/Chapters Subcommittee.

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Device Design and Optimization Considerations for Bulk FinFETs