Design Considerations for Next Design Considerations for Next Generation Wireless Power Aware Generation Wireless Power Aware

MicrosensorMicrosensor NodesNodes

D. Wentzloff, B. Calhoun, R. Min, A. Wang, N. Ickes, A. Chandrakasan

Massachusetts Institute of Technology

Emerging Emerging MicrosensorMicrosensor ApplicationsApplications

Industrial Plants and Power Line Monitoring(courtesy ABB)

Operating Room of the Future(courtesy John Guttag)

NASA/JPL sensorwebsTarget Tracking & Detection

(Courtesy of ARL)Location Awareness

(Courtesy of Mark Smith, HP)

Websign

Sensor System RequirementsSensor System Requirements

10 – 100mTransmission Distance

Small Size

Extended Lifetime

Spatial Density

Data Rate

Application Characteristics

5 years

1 “AA” battery

0.1-10 nodes/m2

bps to kbps

Typical Values

Predictable ConstraintsPredictable Constraints Unpredictable DiversityUnpredictable Diversity

Network roles:relay, sensor, aggregator

Environment: event and signal statistics

User/Application: required latency, quality

ApplicationApplication--specific designs specific designs provide energy efficient point provide energy efficient point

solutionssolutions

PowerPower--aware designs aware designs adapt adapt energy consumption to energy consumption to

operating conditionsoperating conditions

Power Aware Power Aware MicrosensorMicrosensor ConsiderationsConsiderations

Energy Harvesting

API and Control

RF Innovations

Low-Rate Digital Computation

Energy-Scalable Algorithms

MAC and Protocols

Power Aware Power Aware MicrosensorMicrosensor

NetworksNetworks

)/(10 SVleakage

TI −∝

API

HW

OS & MIDDLEWARE

SW

First Generation Wireless First Generation Wireless MicrosensorMicrosensor

Battery

Mic.

AmpLow-Pass

Filter ADC

ThresholdDetector

DC/DC Converter

Processor FIFO

FIFO

Static RAM Flash ROM

Implemented on an FPGA

Antenna

Clock Recovery

Shifter

Control

Radio IC

Power Amp.

Sensor Processor Radio

206MHz StrongARM 2.4GHz ISM band4-channel acoustic

Fine Grain Shut Down ControlFine Grain Shut Down Control

AmpFilter

ThresholdDetector

ADC Processor

RAM ROMFPGA RF IC

LNA

PA

3.3V Analog PowerOnOff

Radio PowerOnOff

RF (PLL, etc…)ActiveStandby

TransmitterOnOff

A/D ConverterActiveSoftware

Shutdown

Anti-Aliasing PrefilterActiveStandby

ReceiverOnOff

StrongARM ProcessorActiveIdleSleep

Active Power Management: DVS, variable ECC and packet size, variable transmit power, agile algorithms

OSOS--Controlled Power Down ModesControlled Power Down Modes

Data collection: 1024 samples at 1kSPS

(Processor alternates between idle/active)

LOB Calculation

(Processor active full-time)

Data transmission

(Radio transmitter active)

Sleep

(All systems power down)

Time (s)

Pow

er (m

W)

0

100

200

300

400

500

0 0.02 0.04 0.06 0.08 0.1 0.12

Processor Idle:low = idlehigh = active

Processor Sleep:low = sleephigh = active or idle

Dynamic Voltage ScalingDynamic Voltage Scaling

Digitally adjustable DC-DC converter powers SA-1110 core

µOS selects appropriate clock frequency based on workload and latency constraints

SA-1110

Control

µOS

Controller

5

3.6V

Vout

Leakage : Low Duty Cycle ConcernLeakage : Low Duty Cycle Concern

FFT Execution Time

Tota

l Cha

rge

flow

)/(10 SVleakage

TI −∝

Duty Cycle (%)To

tal E

nerg

y/Sw

itchi

ng E

nerg

y

Leakage Dominates Switching Energy for Low Duty Leakage Dominates Switching Energy for Low Duty Cycles Cycles –– “Off” State“Off” State--centric Optimizationcentric Optimization

Power Aware RadioPower Aware Radio

PLLXilinx

Rx Power Control

Demod& slice

0-20dBm

Tx Power Control

VregData

Fine-grain shutdown through regulators and bias controlVariable 6-level PA allows efficient transmission for 10m to 100m

SA1110

Vreg

: Power Down Control

RF StartRF Start--up Energy Overheadup Energy Overhead

Ener

gy p

er b

it (n

J)

10000

1000

100

1010 100 1000 10000 100000

Packet size (bits)

Energy Energy = = PPtx_electronicstx_electronics ((TTtranmsittranmsit + + TTstartstart)) + P+ Poutout TTtransmittransmit

Significant loss in energy efficiency for small packet sizes

Startup Costs are Fundamental Startup Costs are Fundamental ––Innovative Circuits and Protocols RequiredInnovative Circuits and Protocols Required

Next Generation Sensor NodesNext Generation Sensor Nodes

Ultra Low-Voltage Digital Circuits

Design for 100mV Supply

Region of Observation Base Station

Network API/Simulation

Ultra-Wideband Radio

Sensor&

A/D

SensorSpecific

Cores(FFT,

Matched Filters,etc.)

Low-EndSensor

DSPProcessor

ProtocolProcessor

(Basedbandand MAC)

RFTransceiver

Energy Source and Regulation

High-speed & Low-power Time Domain Processing

How to simulate 1000’s nodes?

Sensor System-on-a-Chip

Compact Form Factor (mm3 – cm3) Low Rate Radio link (10-100kbs) System Power < 100µW

Q

QSET

CLR

D

Digital

DVDD

DGND

LNA

AVDD

AGND

RF Front End

Mixed-Signal Design

How to Integrate RF & Digital?

Energy Processing

How to Scavenge 100µW?

Energy Scavenging: VibrationEnergy Scavenging: Vibration--toto--Electric EnergyElectric Energy

1010µµW from generator possibleW from generator possibleMEMS Generator Controller

Programmable Software FabricsProgrammable Software Fabrics

FPGA (Xilinx)

05

1015202530354045

Pow

er (%

)

Cache Control GCLK EBOX I/O,PLL

Processor (StrongARM-1100)

[Montanaro, JSSC ‘96]

CLB CLB

CLBCLB

65%21%

9%5%

InterconnectClock

I/OCLB

““Software” Energy Dissipation is Dominated by Software” Energy Dissipation is Dominated by Overhead and NOT by Useful WorkOverhead and NOT by Useful Work

Leakage Mitigation Using MTCMOSX3 X2 X1 X0

Y3

Y2

Y1

Y0

P0

P1

P2

P3

P4P5P6

P7

pc

pc

VDD

0 50 100 150 200 250 8

10

12

14

16

Dela

y ,n s

Sleep Transistor Width, W/L

A: X=00000000->11111111Y=00000000->10000001

B: X=01111111->11111111Y=10000001->10000001

Vector A

Vector B

Sleep High VT Device

Low VTLogic Virtual

Ground

Device Sizing is a Major Concern in Multiple

Threshold CMOS

Leakage Reduction Using MTCMOSLeakage Reduction Using MTCMOS

A

A

A XOR B

B=1

A=0

0

1

Look at A=0 and B=1.Sneak Leakage!!

B

A

Power Aware Architectures Power Aware Architectures

Single butterfly architecture (4 multipliers, 6 adders)

Data Memory

Twiddle ROM

Dat

a A

ddre

ss

Twiddle Address

R/W AB

XY

W

Control Logic

Butterfly structure

A

BW

X=A+BW

Y=A-BW

FFT Computation

Power Scalable MultiplierPower Scalable Multiplier(modified Baugh(modified Baugh--WooleyWooley))

X{15:0}

32x32

16x3216x32

64x32

128x32

32x32

16x3216x32

64x32

128x32

Control Logic

Y{1

5:8

}

X{15:8}

11

1

Z{15:0}

00

00

00

00

00

00

00

0

Y{15:0}

8-bit feed through

Power Scalable MemoryPower Scalable Memory

Address(write/read)data (write)

Data (read)

gatinginput

0

0

Adder used only in16-bit modeAdder used in 8-bitAnd 16-bit mode

First Generation Power Aware FFT First Generation Power Aware FFT

Mem

ory

Ban

k 0

Mem

ory

Ban

k 1Butterfly

Datapath

Control

Twid

dle

RO

Ms

• 0.18µm process• 2.1mm x 3mm• VT0n = 0.45V, VT0p = -0.44V• Vdd = 1.8V

564 nJ304 nJ512 pt.216 nJ121 nJ256 pt.81 nJ46 nJ128 pt.16-bit8-bit

Measured energy dissipation

Technology Parameters

Power programmable from 128pts to 512ptsand 8 bits and 16 bits

Energy Efficiency of Digital ComputationEnergy Efficiency of Digital Computation

Single butterfly architecture (4 multipliers, 6 adders)

Data Memory

Twiddle ROM

Dat

a A

ddre

ss

Twiddle Address

R/W AB

XY

W

Control Logic

Butterfly structure

A

BW

X=A+BW

Y=A-BW

Optim

al (Vdd , V

th )

Supp

ly V

olta

ge (V

DD)

FFT Computation

Threshold Voltage (Vth)

Exploit Sub-threshold Operation for Sensor Circuits

Adaptive VAdaptive VDDDD/V/VTT ArchitectureArchitecture

TempCircuit to be biased

to optimum VDD/VT point

PhaseDetector

N/PBody BiasGeneratorMatched Delay Line

N

LookupTable

PowerConverter

VDD

ClockWorkload

P

MAC

0.17

5 V

166 kHz clockdata

[Miyazaki, ISSCC ’02]

New Energy Metrics in DSM InterconnectNew Energy Metrics in DSM Interconnect

02468

1012141618

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

Normalized Energy, Normalized Energy, EE

0

10

20

30

0 1 2 3

Standard modelStandard model

Normalized Energy, Normalized Energy, EE# of

tran

sitio

ns o

f co

st

# of

tran

sitio

ns o

f co

st EE SubSub--micron modelmicron modelBUS

d2

d1

l2

l1

VDD

CL

CL

CI

3==L

I

CCλ

# of

tran

sitio

ns o

f co

st

# of

tran

sitio

ns o

f co

st EE

Extended Busn+a lines

Recovered DataInput Data (n bits)

... DecoderEncoder

Minimizing Transition Activity is not the Minimizing Transition Activity is not the Right approach to Minimize PowerRight approach to Minimize Power

Computation vs. CommunicationComputation vs. Communication

1E-111E-101E-091E-081E-071E-061E-051E-041E-03

1 10 100 1000 10000

Energy for Electronics + Transmit

R2 Propagation LossLimit (no electronics)Assuming 10pJ/bit/m2

Ener

gy (J

)

Distance (m)

Computation: 1nJ/op (µ-Processor) and Communication (@10m): 150nJ/bit @10 m: ~150 instructions/transmitted bit on a low-power processor@10m: > 1Million instructions/transmitted bit using dedicated hardware

Compute, Don’t CommunicateCompute, Don’t Communicate

Fast Startup TransmitterFast Startup Transmitter

/N , /N+1

PFDfref

Σ−∆channel

data LPF

Variable loop filter

E/bit = 10nJ/bit

Variable loop bandwidthFixed loop bandwidth

New Opportunities: “Digital” UWB RadioNew Opportunities: “Digital” UWB Radio

Pulse Generator

CLK Generator

T/HLNA

BUFFER

A/D

A/D

A/D

A/D

Reg

Reg

Reg

Coarse

Acquisition

&

Fine

Tracking

Data Out

Code

Generator

Data In

Minimal Front-end components: leverage low-power digital circuits

3-4 bits A/D sufficient (Newaskar, Blazquez, Chandrakasan, SIPS ‘02)

MultihopMultihop and the Characteristic Distanceand the Characteristic Distance

DD

E = h α1 + α2D

h( )2

D/hD/h D/hD/h D/hD/h

number of hops

per-hop distance

DD

minh

E = 2α1D

dchar

Direct Transmission

Multihop Transmission

E = α1 + α2D2

Tx &Rx Radio Electronics

attenuation,power amp

path loss exponent

0.05

0.1

0.15

0.2

0.25

0 50 100 150 200

1 hop

2 hops

3 hops

4 hops

dcharE, E

nerg

y (

E, E

nerg

y ( m

Jm

J ))

α1 = 30 nJ/bitα2 = 10-11/bit1000 bits

D, Total Distance (meters)D, Total Distance (meters)

where dchar = α1α2

Characteristic Distance for Multihop Transmission

MultiMulti--Hop Routing AnalysisHop Routing Analysis

Take advantage of dense sensor networks by using several shorter hops to transmit long distancesPlot of total power used to transmit a given distance for 1, 2, 3, and 4 hops

Large power step in each trace from turning on external PATrace out lowest curve for energy efficiency (i.e. use 3 hops @ 1000 m)

Multi-hop routing is more energy efficient for this particular radio

Adds overhead to the protocolAdds latency to the network

12 3 hops

Direct hop

0 1000 2000 30000

500

1000

1500

2000

2500

Link Distance [m]To

tal P

ower

[mW

] 4 hops3 hops

2 hops

1 hop

API and Middleware LayerAPI and Middleware Layer

TxPower

EnergyReliability

RadioProcessor

Code Selection

Voltage/Frequency

Power-Awareness Manager

Latency Range

Application/Protocol

set_max_energy(Energy energy)set_max_latency(Time latency)set_min_reliability(Prob probReception)set_range(int nearestNodes, Node[] who,

float meters)

Power Aware API: performance of communication defined and exposed as a basis for trade-offs

Quality of communicationQuality of communication defined along four axes:defined along four axes:

Reliability (BER)“How reliably?”

Energy (µJ)“How much energy?”

Latency (ms)“How soon?”“To whom?”

ConcernRange (m)

Metric

APIAPI--Controlled Operational Policy Controlled Operational Policy

Radiated Power

Convolutional Code

Rel

iabi

lity

(log

BER

)

Reliability (log BER)

Rel

iabi

lity

(log

BER

)

Range (m)

+0 dBm+3 dBm+5 dBm+10 dBm+15 dBm+20 dBm

UncodedR=2/3, K=3R=1/2, K=3R=1/2, K=5R=1/2, K=7

Operational PoliciesRadiated Power Convolutional Code

Ene

rgy

(J)

µAMPS-1 Node1000 bits

Total Communication Energy

Range (m)

Range (m)

higher quality

Energy scales gracefully with communication quality

higher quality

ConclusionsConclusions

Exciting new applications enabled by a network of low-power wireless sensing devicesPower Aware Design Methodology supersedes Energy Efficient DesignSlower is Better – exploit sub-threshold operation as fastest switching speed is not neededCommunication-centric design

Energy per operation (mW/MIPS) will scale with technologyCommunication costs (nJ/bit) will not scale at the same rate

Low Energy Sensor Design Requires a SystemLow Energy Sensor Design Requires a System--level level Approach Approach –– Tight Coupling Between Fabrics, Tight Coupling Between Fabrics,

Algorithms and ProtocolsAlgorithms and Protocols