Design and Verification for PCS Layer of PCI Express Using

Copyright © 2011 IJECCE, All right reserved151

International Journal of Electronics Communication and Computer EngineeringVolume 2, Issue 2, ISSN (Online): 2249–071X, ISSN (Print): 2278–4209

Design and Verification for PCS Layer of PCI ExpressUsing VHDL

Hemant Kumar Soni, Mr. Vikas Gupta, Mrs. Deepti Agrawal(Electronics & Communication) TIT Bhopal

ABSTRACT- The aim of this paper is to design and verifythe physical layer implementation by using ISE 8.1 fromXilinx and Spartan 3 FPGA to reduce the cost andhardware as well without affecting the performance andreliability of PCI Express. PCI is the third generation highperformance I/O bus used to interconnect peripheraldevices in applications such as computing andcommunicating platform. PCI Express is an all incompassing I/O device interconnect bus that hasapplication in the Mobile, Desktop, Workstation, Server,Embedded computing and communication platform. PCSis the sub layer of the physical layer of PCI Express 1.0.The major constituents of this layer are transmitter andreceiver.Transmitter comprises of 8b/10b encoder. ThePrimary purpose of this scheme is to embed a clock intothe serial bit stream of transmitter lanes withadvancement in the design by reducing the utilizedhardware resources within FPGA. No clock is transmittedalong with the serial data bit stream. This eliminates EMInoise and provides DC balance.Receiver comprises ofspecial symbol detector, elastic buffer and 8b/10b decoder.. 8b/10b decoder gives 8bit character and data/controlsignals. Disparity error and Decode error can be knownthough this module. If any error is present in the receiveddata then loopback signal is generated. This work usesVHDL to model different blocks of the PCS of physicallayer of PCI Express. The RTL code is simulated,synthesized and implemented using the ISE 8.1 fromXilinx and the Spartan 3 FPGA was targeted forimplementation.In this paper we have reduced the hardware as well as costof total system without affecting the speed of the PCIExpress.

Index Terms or Keywords: FPGA (Field-ProgrammableGate Array), PCI-SIG (Peripheral ComponentInterconnect Special Interest Group), VHDL (Very HighSpeed IC Hardware description Language)

I. INTRODUCTION

As per the Study of the references, designing forTransmitter of PCS Layer of x1PCI express had beenimplemented on the logical implementation basis usingthe mixed style of modeling in VHDL. Due to which theexact control over the hardware utilized was in the handof synthesis tools. As for the work we had tried toimplement the abstracted design more on to a hardwareimplementation basis. This not only reduces the actual

hardware utilization for the specific logic but also givesus a complete control on any of the instant segmentwithin the design.

A PCI Express interconnect that two devices together isreferred to as Link. A link consist of either x1, x2, x4,x8, x12, x16 or x32 signal pairs in each direction. Thesesignals are referred to as Lanes. PCI Express is rapidlyestablishing itself as the successor to PCI, providinghigher performance, increased flexibility and scalabilityfor next-generation systems, as well as maintainingsoftware compatibility with existing PCI applications.As PCI Express becomes the standard interconnect forleading-edge embedded applications, system designersmust address the challenges associated with theusability of this new protocol. Buses are designed toconnect more than two devices together in a system.Devices may include the CPU, main memory, and I/Odevices. They consist of three types of signals: Data,Address, and Control. In addition to these signals, theremay be utility lines defined as part of the bus to supplypower and ground to the devices connected to it.Different types of buses that are common in practice areSPI (Serial Peripheral Interface) , I2C (Inter IntegratedCircuit), ISA (Industry Standard Architecture), VESA(Video Electronics Standards Association, VL Bus),PCI (Peripheral Component Interconnect), USB(Universal Serial Bus), AGP (Advanced Graphics Port),PCI Express.PCI: The PCI bus clock is 33 MHz the address buswidth is 32-bits (4GB memory address space), althoughPCI optionally supports 64-bit address bus. The data buswidth is implemented as either 32-bits or 64-bitsdepending on bus performance requirement. Theaddress and data bus signals are multiplexed on thesame pins (AD bus) to reduce pin count. PCI isintroduced by INTEL, PCI–SIG in 1993.PCI Express: PCI Express is used in consumer, server,and industrial applications, both as a motherboard levelinterconnects and as an expansion card interface foradd-in boards. A key difference between PCIe andearlier PC buses is a topology based on point-to-pointserial links, rather than shared parallel bus architecture.To improve bus performance, reduce overall systemcost and take advantage of new developments incomputer design the PCI Express architecture had to be



re-designed, which can be made by physical layerimplementation and by using low cost FPGA.In this Paper we had tried to design a low cost PCIExpress solution with reduced hardware utilization of aLow cost FPGA, overall making an efficient solutionfor the low cost market segment.

II. LOW COST REDUCED HARDWAREUTILIZATION FPGA SOLUTION FOR PCI

EXPRESS IMPLEMENTATIONS

1- Xilinx Low Cost Spartan3 FPGA2- PCI Express Core Design and Implemented Using

VHDL with Physical Layer Interface

The Spartan®-3 family of Field-Programmable GateArrays is specifically designed to meet the needs of highvolume, cost-sensitive consumer electronic applications.The eight-member family offers densities ranging from50,000 to five million system gates. The Spartan-3family builds on the success of the earlier Spartan-IIEfamily by increasing the amount of logic resources, thecapacity of internal RAM, the total number of I/Os, andthe overall level of performance as well as by improvingclock management functions. Numerous enhancementsderive from the Virtex®-II platform technology. TheseSpartan-3 FPGA enhancements, combined withadvanced process technology, deliver more functionalityand bandwidth per dollar than was previously possible,setting new standards in the programmable logicindustry. Because of their exceptionally low cost,Spartan-3 FPGAs are ideally suited to a wide range ofconsumer electronics applications; including broadbandaccess, home networking, display/projection and digitaltelevision equipment. The Spartan-3 family is a superioralternative to mask programmed ASICs. FPGAs avoidthe high initial cost, the lengthy development cycles,and the inherent inflexibility of conventional ASICs.Also, FPGA programmability permits design upgradesin the field with no hardware replacement necessary, animpossibility with ASICs. Its basic feature is Low-cost,high-performance logic solution for high-volume,consumer-oriented applications- Densities up to 74,880logic cells.

III. DIFFERENT COMPUTER BUSES

Table 1-1: Different Buses and their speedsDevice Speed (bit/s) Speed (byte/s)I2C 3.4 Mbit/s 425 Kb/sISA 8-Bit/4.77MHz

9.6 Mbit/s 1.2 Mb/s

ISA 16-Bit/8.33MHz

42.4 Mbit/s 5.3 Mb/s

EISA 8-16-32- 320 Mbit/s 32 Mb/s

Bit/8.33 MHzPCI 32-Bit/33MHz

1,067 Mbit/s 133.33 Mb/s

PCI Express 1.0(x1 link)

2,000 Mbit/s 250 Mb/s

PCI 64-Bit/33MHz

2,133 Mbit/s 266.7 Mb/s

PCI 32-Bit/66MHz

2,133 Mbit/s 266.7 Mb/s

AGP 1x 2,133 Mbit/s 266.7 Mb/sPCI Express 1.0(x2 link)

4,000 Mbit/s 500 Mb/s

AGP 2x 4,266 Mbit/s 533.3 Mb/sPCI 64-Bit/66MHz

4,266 Mbit/s 533.3 Mb/s

PCI-X DDR 16-Bit

4,266 Mbit/s 533.3 Mb/s

PCI 64-Bit/100MHZ

6,399 Mbit/s 800 Mb/s


8,000 Mbit/s 1,000 Mb/s

AGP 4x 8,533 Mbit/s 1,067 Mb/sPCI-X 133 8,533 Mbit/s 1,067 Mb/sPCI-X QDR 16-Bit

8,533 Mbit/s 1,067 Mb/s


16,000 Mbit/s 2,000 Mb/s

AGP 8x 17,066 Mbit/s 2,133 Mb/sPCI-X DDR 17,066 Mbit/s 2,133 Mb/sPCI Express 1.0(x16 link)

32,000 Mbit/s 4,000 Mb/s


32,000 Mbit/s 4,000 Mb/s

AGP 8x 64-Bit 34,133 Mbit/s 4,266 Mb/sPCI Express (x32link)

64,000 Mbit/s 8,000 Mb/s


64,000 Mbit/s 8,000 Mb/s


1,28,000Mbit/s

16,000 Mb/s

In the above different computer buses we have workedon PCI Express 1.0 (x1 link) which has a speed of 2,000Mbit/s or 250 Mb/s.

IV. RESULT

VHDL codes are written for 8b/10b encoder/decoder,elastic buffer blocks of PCS of Physical layer of PCIExpress. These RTL codes are simulated, synthesizedand implemented using the ISE 8.1 tool from Xilinx andSpartan 3 FPGA.Results are as follows:-At the transmitting end



i. When d_k = 0 (for data sequence) aftertransmission of 8 bit data as a result we havegot 10 bit encoded data as shown in figure 1.

ii. According to the data sequence, disparitychanged is as shown in figure 2.

iii. After sending another data sequence of 8 bitwe have found that the total no. of 0`s areequals to the total no. of 1`s which showsconstant disparity which is shown in figure3.

iv. When d_k = 1 (for command signal) aftersending the 8 bit command signal as a resultwe have got 10 bit encoded signal which isshown in figure 4.

v. Figure 5 shows the command signal inHexadecimal form.

1- For normal data sequence

2- For showing disparity change effect

3- For constant disparity where total no. of 1= total no.of 0

4- For sending the command signal

5- Command signal in Hexadecimal form

V. CONCLUSION & FUTURE WORKPhysical Coding sub layer of Physical Layer of PCIExpress has been designed by using ISE 8.1 from Xilinxand Spartan 3 FPGA.8b/10b Buffer capable of encode 8 bit character anddata/control signal into 10 bit symbol. If there is anyinvalid data, encoder detects that. Elastic Buffer detectsthe underflow and overflow of the FIFO. It adds SKPsymbol when the Buffer is not half filled. To maintainhalf-filled state it adds SKP symbol. It also removesSKP symbol whenever the buffer filled more than half-filled state. The purpose of synchronization and to avoidthe data loss is fulfilled through Elastic Buffer. Thismodule also detects the overflow/underflow.8b/10b decoder decodes 10 bit symbols into 8 bitcharacter and data/control signal. It detects disparityerror and decoder error through which the validity ofreceived data is known. PCS is the major block wherefuture developments are done. Usually in later cameversions of PCI Express of 1.0, major developmentswere in the physical coding sublayer. The Encodingscheme has been changed in the PCI Express 3.0 as8b/10b to 128b/130b. This almost overcomes theoverhead as in PCI Express 1.0.Device utilization summarySelected Device: 3s400pq208-4No. of Slices:

88 out of 3584 2%



No. of Slice Flip Flops:99 out of 7168 1%Number of 4 input LUTs:136 out of 7168 1%Number of bonded IOBs:24 out of 141 17%Number of GCLKs:

1 out of 8 12%Timing Summary:Minimum period: 7.248ns (Maximum Frequency:499.969MHz)Minimum input arrival time before clock: 5.976nsMaximum output required time after clock: 12.307nsMaximum combinational path delay: 9.344nsWith the above summary it’s been clearly indicated thatthe 500Mbps rate has been achieved for PCI Express 1.0(x1 link) and the Synthesis summary indicates areduction in the overall hardware utilization forimplementing the core.Only 2 % of the total hardware slices had been utilizedwithout affecting the performance of the channel data.

VI. REFERENCES

1. PCI Express Design & System Architecture ByEdward Solari, Brad Congdon for PCI Expressspecification

2. A complete architecture solution on “PCIExpress System Architecture” by MindShare,Inc, Ravi Buduck, Don Anderson, Tom Shanley,Addison Wesley Publications, September 2003.

3. Basic information about PCI Express on “PCIExpress Base Specification” v1.1, released byPCI-SIG, 2002.Overview of PCI xpress,technical details for hardware & ftwarecompatibilityhttp://zone.ni.com/devzone/cda/tut/p/id/3540

4. History of PCI Express on http://www.pcisig.com5. software working solution on “A Hardware and

Software Developer's” Guide by Adam Wilen,Justin Schade, and Ron Thornburg

6. “PHY Interface for the PCI Express TMArchitecture”, version 1.00, April 2003.

7. PCI Local Bus Standard, Revision 2.1 – June1995, PCI Special Interested Group for PCIBuses

8. http://www.ati.amd.com9. For details of Intel’s PCI Express

http://www.intel.com

10. For details about VHDL ( Spartan 3) coding andfeatures www.xilinx.com

11. standards of PCI Express onwww.pcisecuritystandards.org

12. Technical support on PCI Express Testing withJ_Bert N4903A, Agilent, 2006

13. For Details for VHDL on J.Bhaskar, VHDL - AStarters Guide, 2nd Edition, ©2005 (SudhakarYalamanchili)

14. A detail study of VHDL on Douglas Perry,“VHDL: Programming By Example, 4 edition”

http://zone.ni.com/devzone/cda/tut/p/id/3540

http://www.pcisig.com

http://www.ati.amd.com

http://www.intel.com

www.xilinx.com

www.pcisecuritystandards.org

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Design and Verification for PCS Layer of PCI Express Using