Dayle Kotturi and Stephanie Allison Facility Advisory Committee Meeting [email protected]@slac.stanford.edu, [email protected] April 20-21,

Dayle Kotturi and Stephanie Allison Facility Advisory Committee Meeting [email protected], [email protected] 20-21, 2006

Timing

Outline Block diagram overview of the timing system

Where were we at time of last FAC?

What has happened since then?

How will this work anyway?

How does it look from a users point of view?

What do we still not know?

Tasks remaining: plans/schedule


Timing System

Constant 120 Hz

Logic

MKSU MPS

MPG

EVG

EVR

PNET

Arrives within 2.7 ms(1-360 Hz beam pulse)

eg rate limit

PNET

Arrives within 24.9 ms(3-120 Hz beam pulses)

EVR

PNET pattern of instructions for next LCLS beam pulse, timestamp and operator rate limits

CPU

CPU

LCLS MPG “LE20”

SLC-AWARE IOC SLC-AWARE IOC

CPU

LCLS beam loss

monitor(new)

PEP beam loss

monitor(existing)

LINAC vacuum interlock (existing)

Within 1/360 s

LCLS vacuum (new)

LCLS power

supplies (new)

Orbit tolerances

KickerSBBD

LaserLaser status

RF 476 MHz reference

clock

Gated data acquisition application (eg. BPM)

Gated data acquisition application (eg. BPM)

BPM

hw

BPM

hw

Needs to be added so that LCLS vacuum leak detection shuts off klystron

FIDO360 Hz fiducial

EVG Fanout

EVR

CPU

Pockels Cell

Controller

LCLS MPS/

Reconditioned120 Hz

Logic


Where were we at time of last FAC?

PNET driver done

EVG/EVR 100 series hardware in house could send events from EVG to EVR but not PNET data

Working with other labs and Micro-Research Finland (MRF) to consolidate our requests for a new version of the hardware


What has happened since then?Received the EVG/EVR 200 series VME hardware (which sends up to 2K data buffer)Adapted driver and device support to:

send the PNET data buffer (measured 66 µs transfer) be OSI (running on mvme6100, RTEMS4.7) with help from Till Straumann, Eric Bjorklund, Timo Korhonen, Jukka Pietarinen and Bob Dalesio

Wrote Timing Trigger System Engineering ManualReceived the EVR 200 series PMC moduleInstalled fiber optic network in Bldg 280 for testing


What has happened since then? (2)Stephanie is setting up a hardware teststand with separate IOCs for EVG and EVR in Bldg 34 for CPE engineers to do:

Timing comparison with existing CAMAC timing system (MPG/PDU)Timing measurements – jitter, etcShakedown by the experts

Test stand to include:EVG, PNET, EVR, EVR transition module, EVG fanout laterInputs: PNET pattern from CAMAC timing system, fiducial trigger, and 476Mhz clockOutputs: EVR front panel and back transition moduleInfrastructure: VME crates, dedicated terminal server, dedicated PC, fiber between EVG and EVREPICS: test databases and displays, EVR done, EVG in-progress


How will this work anyway?

8-b

it Eve

nt C

od

e

8-b

it MP

S D

ata

(Sh

are

d D

ata

Bu

s)

8-b

it Eve

nt B

uffe

r

8-b

it Eve

nt C

od

e

8-b

it Eve

nt C

od

e

8-b

it MP

S D

ata

(Sh

are

d D

ata

Bu

s)

8-b

it Eve

nt B

uffe

r

8-b

it Eve

nt C

od

e. . .. . .

EVG EVR

8-b

it Eve

nt C

od

e

8-b

it MP

S D

ata

(Sh

are

d D

ata

Bu

s)

8-b

it Eve

nt B

uffe

r

8-b

it Eve

nt C

od

e

8-b

it Eve

nt C

od

e

8-b

it Eve

nt C

od

e

Time (nsec)

8.4 16.8 25.2 33.6 42.0 50.4 58.8 65.2

8-b

it Eve

nt B

uffe

r

8-b

it MP

S D

ata

(Sh

are

d D

ata

Bu

s)


EVG/EVR data sources by type

Event Buffer byte17Timestamp byte 1


Event Buffer byte23Timestamp byte7

Event Buffer byte24Operator Requests

Event Buffer byte25Other data

.

.

.

Max Buffer is

2048 Bytes(34.42 µs)

LCLS expected

size is < 30 bytes

(0.5 µs)

Event BufferSequence RAM

Events queued to send

Event Code360 Hz fiducial

Event CodeBeam On

Event CodeRF On

Event CodeLaser Trigger

.

.

.

MPS Data

MPS DataStatus byte N

MPS DataResend byte N

MPS DataResend byte N

8-bit MPS DataResend byte N

MPS DataStatus byte N+1

Event CodeSBBD

Event Code10 Hz event

Event Code1 Hz event

Event CodeHLA DAQ


Event Buffer byte 1PNET byte 1

Event Buffer byte 0PNET byte 0

Event Buffer byte15PNET byte 15

No change in MPS status

MPS DataResend byte N+1

MPS DataResend byte N+1

change in MPS status

.

.

.

No change in MPS status

Countdown to send0.00 ms

Event CodeBPM Trigger

Event CodeDump Circ Buffers

Countdown to send8.4 ns




Countdown to sendOperator request

Countdown to sendOperator request




Event CodeSBBD


Two SBBD event codes shown. First is case to send beam to undulator; second is timed to

prevent beam from reaching undulator. It’s one OR the other, per seq RAM.


Timescale for event code transfer

360 Hz fiducial

Time after fiducial that event code is sent (millisec)LCLS timeslot shown

RF event

0.5 1.0

BPM event

0.0

Laser event

Beam On

2.52.01.5

1 Hz event

10 Hz event

Event Code


Timescale for event buffer transfer

Time to send 16 byte event buffer from EVG to EVR: 66.4 µs


Timescale for MPS data transfer

16.8 ns

MPS EVG EVR

8-bit MPS Data(Shared Data Bus)

8-bit MPS Data(Shared Data

Bus)

Shared Data Bus

<=100 ns(Transition Module)


How does it look to a user?

Programmable Delay

Event Code

Trigger

Event Data in EVR


PNET data display


EVR diagnostics for h/w engineers


EVR event diagnostics for h/w engs


What do we still not know?

Verify jitter

Verify fiber optic performance (multi vs single mode)

Licensing agreement with MRF


Tasks remaining: plansFinish PMC-EVR driver

EVG sequence RAM programming at 360 Hz

EVG rules definition

MPS hardware interface

Migrate PNET receiver data records to EVR data records

Full-integration of PMC-EVR with VME-EVR software for easier maintenance

Operator interface – panels to set rate limits, do single shot

Fanout and transition module integration and testing

Installation at sector 20


Interface Control Document + review, MayEVG input and outputHW and SW trigger list per subsystemApplications using the timing patternRecord (maybe IOC) timestampingBeam-synchronous acquisition and controlUse writeup provided by Bob Dalesio

Design Document + review, JuneBeam-Synchronous Control: rules and algorithm for creating EVG trigger sequences on a pulse-to-pulse basis – algorithm changes based on user requestsBeam-Synchronous Acquisition: mechanism for users to request pulse-by-pulse acquisition (single-shot or buffered) across multiple IOCs based on specified conditionsProper timing pattern in-place before a fiducial for record processing after fiducial

Implementation of above design plus:Integration with SLC-aware BPM acquisitionMissing functionality in existing EVG and EVR records for HW upgradeUser-friendly database layer on top of low-level EVR records

Tasks remaining: high-level s/w plans


Tasks remaining: schedule

We’re in the process of redoing/updating the work breakdown schedule. A draft is due by end of April and final version in May.

Documents

Dayle Kotturi and Stephanie Allison Facility Advisory Committee Meeting [email protected]@slac.stanford.edu, [email protected] April 20-21,