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DATE 99Design, Automation and Test

in Europe Conference 1999

March 9-12, 1999ICM/Neue MesseMunich, Germany

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Design, Automation and Testin Europe

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Dominique Borrione, TIMA, Grenoble, FranceRolf Ernst, Technical University of Braunschweig, Germany

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TTaabbllee ooff CCoonntteennttssDesign, Automation and Test in Europe DATE’99

Event Steering Board ................................................................................................................................. xviiConference Organizing Committee ........................................................................................................ xviiiProgram Topic Co-Chairs.......................................................................................................................... xixConference Committee Continued ........................................................................................................xxVendors Committee.......................................................................................................................................xxTechnical Program Committee ................................................................................................................. xxiReviewers ......................................................................................................................................................xxvWelcome to DATE 1999 ............................................................................................................................xxviBest Paper Awards ....................................................................................................................................xxviiTutorials .................................................................................................................................................... xxviii

Plenary Keynote SessionEmbedded System Design The European Technology DriverModerator: R. Ernst, TU Braunschweig, D

Higher Product Complexity and Shorter Development Time Continuous Challenge to Design and Test Environment ....................................................................................... 2

J. Junkkari

Automotive Electronics A Challenge for Systems Engineering ........................................................................ 4P. Thoma

Testing in Nanometer Technologies..................................................................................................................... 5T. Williams

1A: Verification of Sequential CircuitsModerators: H. Eveking, Darmstadt TU, D; C. Meinel, Trier U, D

Computing Timed Transition Relations for Sequential Cycle-based Simulation .................................................... 8G. Cabodi, P. Camurati, C. Passerone, S. Quer

Symbolic Reachability Analysis of Large Finite State Machines using Don’t Cares .............................................13Y. Hong, P. Beerel

1B: Architectural Issues in Low Power DesignModerators: G. De Micheli, Stanford U, USA; L. Benini, Bologna U, IT

FSMD Functional Partitioning for Low Power....................................................................................................22E. Hwang, F. Vahid, Y. Hsu

A New Parameterizable Power Macro-Model for Datapath Components .............................................................29G. Jochens, L. Kruse, E. Schmidt, W. Nebel

1C: Design Reuse Repository and IP ArchitectureModerators: R. Seepold, FZI Karlsruhe, D; L. Claesen, IMEC/KU Leuven, B

An Efficient Reuse System for Digital Circuit Design .........................................................................................38A. Reutter, W. Rosenstiel

vi

An MPEG-2 Video Encoder LSI with Scalabiity for HDTV based onThree-Layer Cooperative Architecture ................................................................................................................44

M. Ikeda, T. Kondo, K. Nitta, K. Suguri, T. Yoshitome, T. Minami, J. Naganuma, T. Ogura

2A: High Level VerificationModerators: L. Claesen, IMEC/KU Leuven, B; L. Pierre, Provence U, F

Formal Verification of Word-Level Specifications ..............................................................................................52S. Höreth, R. Drechsler

Automatic Verification of Scheduling Results in High-Level Synthesis ...............................................................59H. Eveking, H. Hinrichsen, G. Ritter

Verifying Imprecisely Working Arithmetic Circuits............................................................................................65M. Huhn, K. Schneider, T. Kropf, G. Logothetis

2B: System-Level Power OptimizationModerators: W. Nebel, Oldenburg U, D; E. Macii, Politecnico di Torino, IT

Battery-Powered Digital CMOS Design..............................................................................................................72M. Pedram, Q. Wu

Dynamic Power Management for Non-Stationary Service Requests.....................................................................77E. Chung, G. De Micheli, L. Benini, A. Bogliolo

On Reducing Transitions through Data Modifications .........................................................................................82R. Murgai, M. Fujita

2C: Reconfigurability and Other Issues in Embedded System DesignModerators: D. Verkest, IMEC, B; P. van der Wolf, Philips Research, NL

Kernel Scheduling in Reconfigurable Computing................................................................................................90R. Maestre, R. Hermida, M. Fernandez, F. Kurdahi, N. Bagherzadeh, H. Singh

CRUSADE: Hardware/Software Co-Synthesis of Dynamically Reconfigurable HeterogeneousReal-Time Distributed Embedded Systems .........................................................................................................97

B. Dave

Exploiting Conditional Instructions in Code Generation for Embedded VLIW Processors..................................105R. Leupers

2E: Embedded Core Test ApproachesModerators: Y. Zorian, LogicVision, USA; M. Lobetti Bodoni, Italtel, IT

Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks ....................................................112D. Nikolos, H. Vergos, T. Haniotakis, Y. Tsiatouhas

An Effective BIST Architecture for Fast Multiplier Cores .................................................................................117A. Paschalis, D. Gizopoulos, N. Kranitis, M. Psarakis, Y. Zorian

A CAD Framework for Generating Self-Checking Multipliers based on Residue Codes.....................................122I. Noufal, M. Nicolaidis

vii

3A: Use of Combinational VerificationModerators: P. Camurati, Politecnico di Torino, IT; C. Meinel, Trier U, D

An Efficient Filter-based Approach for Combinational Verification ..................................................................132R. Mukherjee, J. Jain, K. Takayama, M. Fujita, J. Abraham, D. Fussell

Using Combinational Verification for Sequential Circuits .................................................................................138R. Ranjan, V. Singhal, F. Somenzi, R. Brayton

Combinational Equivalence Checking using Satisfiability and Recursive Learning ............................................145J. Marques-Silva, T. Glass

Formally Verified Redundancy Removal ..........................................................................................................150S. Hendricx, L. Claesen

3B: Gate Level Power Estimation and OptimizationModerators: M. Pedram, U Southern California, USA; G. Guardini, STMicroelectronics, IT

Logic Transformation for Low Power Synthesis................................................................................................158K. Kim, S. Kang, T. Hwang, C. Liu

Glitch Power Minimization by Gate Freezing....................................................................................................163L. Benini, G. De Micheli, A. Macii, E. Macii, M. Poncino, R. Scarsi

Spanning Tree based State Encoding for Low Power Dissipation ......................................................................168W. Nöth, R. Kolla

Peak Power Estimation using Genetic Spot Optimization for Large VLSI Circuits.............................................175M. Hsiao

3C: Special Session Virtual Socket Interface AllianceOrganizer and Chair: R. Seepold, FZI Karlsruhe, D

Virtual Socket Interface Alliance ......................................................................................................................182R. Seepold

Speakers:

VSI Builds Momentum to Solve Design Reuse ImperativeL. Rosenberg

The VSI System-Level Perspective on the Mix and Match of Virtual ComponentsM. Genoe

Introduction to Virtual Component InterfaceG. Matthew

3E: Fault Diagnosis Techniques for Analogue CircuitsModerators: J. Huertas, CNM Sevilla, ES; A. Ivanov, UBC Vancouver, CAN

A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester.............................................184E. Cota, L. Carro, M. Lubaszewski

Minimal Length Diagnostic Tests for Analog Circuits using Test History..........................................................189A. Gomes, A. Chatterjee

Parametric Fault Diagnosis for Analog Systems using Functional Mapping .......................................................195S. Cherubal, A. Chatterjee

viii

4A: Resource Sharing in Architectural SynthesisModerators: W. Rosenstiel, FZI Karlsruhe/Tuebingen U, D; P. Eles, Linköping U, SE

Temporal Partitioning Combined with Design Space Exploration forLatency Minimization of Run-Time Reconfigured Designs ...............................................................................202

M. Kaul, R. Vemuri

Time Constrained Modulo Scheduling with Global Resource Sharing ...............................................................210C. Jäschke, F. Beckmann, R. Laur

Polynomial Methods for Allocating Complex Components ...............................................................................217J. Smith, G. De Micheli

Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs........223N. Mansouri, R. Vemuri

4B: Mixed Signal Characterization and TestModerators: A. Richardson, Lancaster U, UK; H. Kerkhoff, Twente UT, NL

A Digital Partial Built-In-Self-Test Structure for a High Performance Automatic Gain Control Circuit ..............232A. Lechner, J. Ferguson, A. Richardson, B. Hermes

Design, Characterization and Modeling of a CMOS Magnetic Field Sensor.......................................................239L. Latorre, Y. Bertrand, P. Nouet, F. Pressecq, P. Hazard

Fast, Robust DC and Transient Fault Simulation for Nonlinear Analogue Circuits .............................................244Z. Yang, M. Zwolinski

On Analog Signature Analysis ..........................................................................................................................249F. Novak, B. Hvala, S. Klavzar

4C: System Design Methodologies: Modelling, Analysis, Refinement and SynthesisModerators: N. Zergainoh, TIMA, Grenoble, F; M. Kovac, TU Zagreb, CRO

The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and SynthesisConcepts of Electronic Systems ........................................................................................................................256

A. Jantsch, A. Hemani, S. Kumar

MOCSYN: Multiobjective Core-based Single-Chip System Synthesis...............................................................263R. Dick, N. Jha

A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement .............................................271R. Cmar, L. Rijnders, P. Schaumont, S. Vernalde, I. Bolsens

4E: High Level Test SynthesisModerators: Z. Peng, Linköping U, SE; B. Rouzeyre, LIRMM, F

Synthesis of Controllers for Full Testability of Integrated Datapath-Controller Pairs..........................................278J. Carletta, M. Nourani, C. Papachristou

Channel-based Behavioral Test Synthesis for Improved Module Reachability ...................................................283Y. Makris, A. Orailoglu

Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths.......................289N. Nicolici, B. Al-Hashimi

ix

5A: High-Level System SimulationModerators: H. Fleurkens, Philips Research, NL; M. Pfaff, Linz U, A

A Retargetable, Ultra-Fast Instruction Set Simulator .........................................................................................298J. Zhu, D. Gajski

High-Speed Software-based Platform for Embedded Software of aSingle-Chip MPEG-2 Video Encoder LSI with HDTV Scalability.....................................................................303

K. Ochiai, H. Iwasaki, J. Naganuma, M. Endo, T. Ogura

Fast Hardware-Software Co-Simulation Using VHDL Models ..........................................................................309B. Tabbara, M. Sgroi, A. Sangiovanni-Vincentelli, E. Filippi, L. Lavagno

5B: Analogue Circuit Sizing and SynthesisModerators: G. Gielen, KU Leuven, B; F. Silveira, INESC, PT

Systematic Biasing of Negative Feedback Amplifiers........................................................................................318C. Verhoeven, A. van Staveren

Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints ............................323R. Schwencker, J. Eckmueller, H. Graeb, K. Antreich

Hierarchical Constraint Transformation using Directed Interval Search for Analog System Synthesis ................328N. Dhanwada, A. Nunez-Aldana, R. Vemuri

5C: VHDL-AMS and HDL InteroperabilityModerators: T. Kazmierski, Southampton U, UK; A. Vachoux, XEMICS S.A., CH

A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog Systems...................338A. Doboli, R. Vemuri

Reasoning about VHDL and VHDL-AMS using Denotational Semantics..........................................................346P. Breuer, N. Madrid, C. Kloos, J. Bowen, R. France, M. Petrie

A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstract State Machine ........................353H. Sasaki

5E: Transistor Level TestModerators: J. Figueras, UP Catalunya, ES; C. Landrault, LIRMM, F

Design for Testability Method for CML Digital Circuits ...................................................................................360B. Antaki, Y. Savaria, N. Xiong, S. Adham

On the Design of Self-Checking Functional Units based on Shannon Circuits....................................................368M. Favalli, C. Metra

Parametric Built-In Self-Test of VLSI Systems .................................................................................................376D. Niggemeyer, M. Rüffer

6A: Hot Topic Hardware Synthesis from C/C++ ModelsOrganizer and Chair: Giovanni De Micheli, Stanford U, USA

Hardware Synthesis from C/C++ Models..........................................................................................................382G. De Micheli

C for System Level Design ...............................................................................................................................384G. Arnout

x

Hardware Synthesis from C/C++ ......................................................................................................................387A. Ghosh, J. Kunkel, S. Liao

C-based Synthesis Experiences with a Behavior Synthesizer, “Cyber” ...............................................................390K. Wakabayashi

6B: Analogue Modelling and SimulationModerators: H. Graeb, TU Munich, D; C. Descleves, Dolphin Integration, F

Efficient Techniques for Accurate Extraction and Modeling of Substrate Coupling in Mixed-Signal IC’s ..........396J. Costa, L. Silveira, M. Chou

A Power Estimation Model for High-Speed CMOS A/D Converters..................................................................401E. Lauwers, G. Gielen

An Analog Performance Estimator for Improving the Effectiveness ofCMOS Analog Systems Circuit Synthesis.........................................................................................................406

A. Nunez-Aldana, R. Vemuri

An Accurate Error Control Mechanism for Simpli fication before Generation Algorithms..................................412O. Guerra, J. Rodríguez-García, E. Roca, F. Fernández, A. Rodríguez-Vázquez

6C: Hot Topic Chip Package Co-DesignOrganizer and Chair: Ivo Bolsens, IMEC, B

Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics ..........................418P. Feldman, S. Kapur, D. Long

Potentials of Chip-Package Co-Design for High-Speed Digital Applications .....................................................423G. Tröster

A Single-Package Solution for Wireless Transceivers .......................................................................................425P. Wambacq, S. Donnay, H. Ziad, M. Engels, H. De Man, I. Bolsens

6E: Panel Scaling Towards Nanometer Technologies: Design for Test ChallengesCo-organized with IEEE Design and Test of Computers and MEDEA Program A-401Organizer: Michael Nicolaidis, TIMA, FModerator: Yervant Zorian, LogicVision, USA

Scaling Deeper to Submicron: On-Line Testing to the Rescue ...........................................................................432M. Nicolaidis, Y. Zorian

Panelists:Richard Ferrand, ST Microelectonics, F; Keith Baker, Phil ips, NL; Rob Roy, Intel, USA;Michael Nicolaidis, TIMA, F; Gunnar Carlsson, Ericsson, SE; Gunter Krampl, Siemens, D

7A: Functional VerificationModerators: E. Villar, Cantabria U, ES; A. Balboni, Italtel, IT

Functional Verification Methodology for Microprocessors using the Genesys Test-Program GeneratorApplication to the x86 Microprocessors Family.................................................................................................434

L. Fournier, Y. Arbetman, M. Levinger

Symbolic Functional Vector Generation for VHDL Specifications ....................................................................442F. Ferrandi, F. Fummi, L. Gerli, D. Sciuto

xi

7B: Bit-Level Logic and Analogue SimulationModerators: P. Schwarz, FhG IIS/EAS Dresden, D; M. Koch, FH Stralsund, D

Interpretable Symbolic Small-Signal Characterization of Large Analog Circuits usingDeterminant Decision Diagrams .......................................................................................................................448

X. Tan, C. Shi

Cycle-based Simulation with Decision Diagrams ..............................................................................................454R. Ubar, J. Raik, A. Morawiec

Efficient Switching Activity Simulation under a Real Delay Model using a Bitparallel Approach ......................459M. Bühler, M. Papesch, K. Kapp, U. Baitinger

7E: Partial and Boundary Scan TestModerators: E. Aas, Trondheim U, NOR; T.W. Williams, Synopsys Inc., USA

Full Scan Fault Coverage with Partial Scan.......................................................................................................468X. Lin, I. Pomeranz, S. Reddy

At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks ...................................473J. Shin, H. Kim, S. Kang

8A: New Languages for System Specification and DesignModerators: C. Delgado-Kloos, U Carlos III de Madrid, ES; W. Fornaciari, Politecnico di Milano, IT

OpenJ: An Extensible System Level Design Language......................................................................................480J. Zhu, D. Gajski

EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability .............485A. Halambi, P. Grun, V. Ganesh, A. Khare, N. Dutt, A. Nicolau

Data Type Analysis for Hardware Synthesis from Object-Oriented Models .......................................................491M. Radetzki, A. Stammermann, W. Putzke-Röming, W. Nebel

8B: Circuit Analysis and DesignModerator: A. Trullemans-Anckaert, UCL, B

How to Use Knowledge in an Analysis Process.................................................................................................498H. Holzheuer

Digital MOS Circuit Partitioning with Symbolic Modeling ...............................................................................503L. Ribas, J. Carrabina

High Speed GaAs Subsystem Design using Feed through Logic........................................................................509J. Montiel-Nelson, V. de Armas, R. Sarmiento, A. Núñez, S. Nooshabadi

8C: Logic SynthesisModerators: R. Drechsler, Freiburg U, D; M. Berkelaar, Eindhoven UT, NL

Integrating Symbolic Techniques in ATPG-based Sequential Logic Optimization .............................................516E. San Millán, L. Entrena, J. Espejo, S. Chiusano, F. Corno

An Algorithm for Face-Constrained Encoding of Symbols using Minimum Code Length ..................................521M. Martínez, M. Avedillo, J. Quintana, J. Huertas

Algorithms for Solving Boolean Satisfiability in Combinational Circuits...........................................................526L. Guerra e Silva, L. Silveira, J. Marques-Silva

xii

Wavefront Technology Mapping ......................................................................................................................531L. Stok, M. Iyer, A. Sullivan

8E: IDDX Testing and Defect ModellingModerators: K. Baker, Philips ED&T, NL; J. Segura, Illes Balears U, ES

On-Chip Transient Current Monitor for Testing of Low-Voltage CMOS IC ......................................................538V. Stopjaková, H. Manhaeve, M. Sidiropulos

Exploring the Combination of IDDQ and iDDt Testing: Energy Testing.................................................................543J. Rius, J. Figueras

Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip using HDL .................................549M. Santos, J. Teixeira

9A: HW/SW Interface Synthesis and PartitioningModerators: K. Kuchcinski, Linköping U, SE; J. Calvez, IRESTE, F

Combining Software Synthesis and Hardware/Software Interface Generation to MeetHard Real-Time Constraints .............................................................................................................................556

S. Vercauteren, D. Verkest, J. Van Der Steen

Operating System Sensitive Device Driver Synthesis from Implementation IndependentProtocol Specification ......................................................................................................................................562

M. O’Nils, A. Jantsch

Codex-dp: Co-Design of Communicating Systems using Dynamic Programming ..............................................568J. Chang, M. Pedram

9B: Physical Design IssuesModerator: F. Johannes, TU Munich, D

Efficient 3D Modelling for Extraction of Interconnect Capacitances in Deep Submicron Dense Layouts............576A. Toulouse, D. Bernard, C. Landrault, P. Nouet

Post-Placement Residual-Overlap Removal with Minimal Movement ...............................................................581S. Nag, K. Chaudhary

Iterative Improvement based Multi-Way Netlist Partitioning for FPGAs............................................................587H. Krupnova, G. Saucier

9C: Reliability and Symmetry in Architectural SynthesisModerators: F. Kurdahi, UC Irvine, USA; R. Hermida, U Complutense Madrid, ES

Self Recovering Controller and Datapath Codesign ...........................................................................................596S. Hamilton, A. Orailoglu, A. Hertwig

Identification and Exploitation of Symmetries in DSP Algorithms.....................................................................602C. van Eijk, E. Jacobs, B. Mesman, A. Timmer

Exploiting State Equivalence on the Fly while Applying Code Motion and Speculation.....................................609L. dos Santos, J. Jess

xiii

9D: Panel Single Chip or Hybrid System Integration?Organizer and Moderator: Ivo Bolsens, IMEC, B

Single Chip or Hybrid System Integration? .......................................................................................................616I. Bolsens

Panelists: Wojtek Maly, CMU, USA; Ludo Deferm, IMEC, B; Jo Borel, ST, F; Harry Veendrick, Philips, NL

9E: Testing Regular Structures and Delay FaultsModerators: L. Bouzaida, STMicroelectronics, F; D. Bhatacharya, Texas Instruments, USA

Testing the Configurable Interconnect/Logic Interface of SRAM-based FPGA’s...............................................618M. Renovell, J. Portal, J. Figueras, Y. Zorian

Industrial Evaluation of DRAM Tests ...............................................................................................................623A. van de Goor, J. de Neef

ATPG Tools for Delay Faults at the Functional Level .......................................................................................631M. Michael, S. Tragoudas

10A: RetimingModerators: M. Berkelaar, Eindhoven UT, NL; R. Drechsler, Freiburg U, D

Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence..........................638P. Kalla, M. Ciesielski

Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits....................................643M. Papaefthymiou, E. Friedman, X. Liu

Retiming Sequential Circuits with Multiple Register Classes.............................................................................650K. Eckl, C. Legl

10B: Modelling of InterconnectsModerator: T. Akino, Kinki U, JP

Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs ..............................658L. Ye, F. Chang, P. Feldmann, R. Chadha, N. Nagaraj, F. Cano

Coupled Noise Estimation for Distributed RC Interconnect Model ....................................................................664J. Wang, Q. Yu, E. Kuh

Projective Convolution: RLC Model-Order Reduction using the Impulse Response...........................................669B. Sheehan

10C: Design Reuse Methodologies for Virtual Components and IPModerators: R. Seepold, FZI Karlsruhe, D; J. Agaesse, Thomson-CSF, F

The Design Space Layer: Supporting Early Design Space Exploration for Core-based Designs..........................676M. Jacome, H. Peixoto, A. Royo, J. Lopez

Specification and Validation of Distributed IP-based Designs with JavaCAD....................................................684M. Dalpasso, A. Bogliolo, L. Benini

Object-Oriented Reuse Methodology for VHDL ...............................................................................................689C. Barna, W. Rosenstiel

xiv

10D: Embedded Tutorial Multilanguage System DesignModerator: Ahmed Amine Jerraya, TIMA, F

Multi-Language System Design........................................................................................................................696A. Jerraya, R. Ernst

Contributors: Rolf Ernst, TU Braunschweig, D; Ahmed Amine Jerraya, TIMA, F

10E: RAM BISTModerators: W. Daehn, Siemens AG, D; G. Carlsson, Ericsson, SE

Symmetric Transparent BIST for RAMs ...........................................................................................................702S. Hellebrand, H. Wunderlich, V. Yarmolik

On Programmable Memory Built-In Self Test Architectures..............................................................................708K. Zarrineh, S. Upadhyaya

A Physical Design Tool for Built-in Self-Repairable Static RAMs.....................................................................714K. Chakraborty, A. Gupta, M. Bhattacharya, S. Kulkarni, P. Mazumder

11B: Panel Java, VHDL-AMS, Ada or C for System Level Specifications?Organizer and Chair: Wolfgang Nebel, Oldenburg U, DCo-Organizer: Giulio Gorla, Italtel, IT

Java, VHDL-AMS, Ada, or C for System Level Specifications?........................................................................720W. Nebel

Case Study: System Model of Crane and Embedded Control .............................................................................721E. Moser, W. Nebel

Panelists: Tom Kazmierski, U Southampton, UK; Eugenio Villar, U Cantabria, ES;Daniel D. Gajski, UC Irvine, USA; Eduard Moser, Bosch, D; Judith Benzakki, U Evry Val d’Essonne, F

11C: Hot Topic IP and ReuseOrganizer and Chair: Wolfgang Rosenstiel, FZI Karlsruhe, D

Virtual Components Application and Customization .........................................................................................726J. Agaësse, B. Laurent

Design Methodology for IP Providers ...............................................................................................................728J. Haase

Speakers: R. Seepold, FZI Karlsruhe, D; R. Haase , SICAN, D; J.F. Agaësse, Thomson-CSF, F

11D: Special Session Large European Programs in Microelectronic System and Circuit DesignOrganizers: D. Borrione, TIMA, F; P. Dewilde, TU Delft, NLChair: I. Bolsens, IMEC, B

Large European Programs in Microelectronic System and Circuit Design..........................................................734P. Dewilde

Speakers:

MEDEA The Microelectronic Development Program for European Applications Status of the Design-Oriented Program and Future Plan

A. Sauer

xv

Electronic Systems Design in the IST ProgramH. Forster

ITEA Information Technology and European AdvancementE. Daclin

11E: Sequential Circuit Test GenerationModerators: E. Gramatova, Slovak Academy of Sciences, SLK; A. Benso, Politecnico di Torino, IT

Sequential Circuit Test Generation using Decision Diagram Models..................................................................736J. Raik, R. Ubar

Illegal State Space Identification for Sequential Circuit Test Generation............................................................741M. Konijnenburg, J. van der Linden, A. van de Goor

FreezeFrame: Compact Test Generation using a Frozen Clock Strategy.............................................................747Y. Santoso, M. Merten, E. Rudnick, M. Abramovici

Posters

Approximate Equivalence Verification of Sequential Circuits Via Genetic Algorithms......................................754F. Corno, M. Sonza Reorda, G. Squillero

Interval Diagram Techniques for Symbolic Model Checking of Petri Nets.........................................................756K. Strehl, L. Thiele

Variable Reordering for Shared Binary Decision Diagrams using Output Probabilities ......................................758M. Thornton, J. Williams, R. Drechsler, N. Drechsler

Increasing Efficiency of Symbolic Model Checking by Accelerating Dynamic Variable Reordering ..................760C. Meinel, C. Stangier

Influence of Caching and Encoding on Power Dissipation of System-Level Buses forEmbedded Systems...........................................................................................................................................762

W. Fornaciari, D. Sciuto, C. Silvano

Emulation of a Fast Reactive Embedded System using a Real Time Operating System ......................................764K. Weiß, T. Steckstor, W. Rosenstiel

The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach ...................766J. Maestro, D. Mozos, R. Hermida

Codesign of Embedded Systems based on Java and Reconfigurable Hardware Components ..............................768J. Fleischmann, K. Buchenrieder, R. Kress

ADOLT An ADaptable On-Line Testing Scheme for VLSI Circuits .............................................................770A. Maamar, G. Russell

Integrated Resource Assignment and Scheduling of Task Graphs using Finite Domain Constraints....................772K. Kuchcinski

A Method of Distributed Controller Design for RTL Circuits ............................................................................774C. Papachristou, Y. Alzazeri

OTA Amplifiers Design on Digital Sea-of-Transistors Array.............................................................................776J. Choi, S. Bampi

xvi

A DAG-based Design Approach for Reconfigurable VLIW Processors .............................................................778C. Alippi, W. Fornaciari, L. Pozzi, M. Sami

A Fault List Reduction Approach for Efficient Bridge Fault Diagnosis..............................................................780J. Wu, E. Rudnick, G. Greenstein

An Object-based Executable Model for Simulation of Real-Time HW/SW Systems ..........................................782O. Pasquier, J. Calvez

An Efficient and Flexible Methodology for Modelling and Simulation ofHeterogeneous Mechatronic Systems ................................................................................................................784

S. Scherber, C. Müller-Schloer

Software Bit-Slicing: A Technique for Improving Simulation Performance .......................................................786P. Maurer, W. Schilp

Interoperability of Verilog/VHDL Procedural Language Interfaces to Build a Mixed Language GUI .................788F. Martinolle, C. Dawson, D. Corlette, M. Floyd

Experiences with Modeling of Analog and Mixed A/D Systems based on PWL Technique................................790J. Dabrowksi, A. Pulka

A One-Bit-Signature BIST for Embedded Operational Amplifiers in Mixed-SignalCircuits based on the Slew-Rate Detection ........................................................................................................792

I. Rayane, J. Velasco-Medina, M. Nicolaidis

Index of Authors ..........................................................................................................................................795

xvii

EEvveenntt SStteeeerriinngg BBooaarrddCHAIRGerry MusgraveBrunel University, UK

EDAA & VENDORS CHAIR(V)Herman BekeFrontier Design, B

SIGDA REPRESENTATIVEJim CohoonUniversity of Virginia,Charlottesville, USA

PUBLICITY(V)Fred SantamariaParis, F

US DAC REPRESENTATIVEMary Jane IrwinPenn State Univ, USA

IEEE REPRESENTATIVE(C)(T)Yervant ZorianLogicVision, USA

EDAALudwig EggermontPhillips SemiconductorsEindhoven, NL

Chris Dace(V)Synopsys (Northern Europe) Ltd, UK

RAS REPRESENTATIVEAlexander StempkovskyIPPM, Moscow, RUS

PROF SOCIETIES LIAISON(P)T.W.WilliamsSynopsys Inc, USA

ECSI & IFIP REPRESENTATIVEJean MermetECSI Association, Gieres, F

INDUSTRIAL LIAISONPeter Van StaaRobert Bosch, Reutlingen, D

EDA CONSORTIUMREPRESENTATIVEPamela ParrishEDA Consortium, San Jose, USA

EDA CONSORTIUMREPRESENTATIVELarry EberleSynopsys Inc, USA

FINANCE CHAIRGordon AdsheadManchester Design Technology,UK

FINANCEVolker DueppeSiemens AG, München, D

CONFERENCE SECRETARIAT(C)Sue MenziesEuropean ConferencesEdinburgh, UK

EXHIBITION SECRETARIAT(V)Jeremy KenyonEDALondon, UK

xviii

CCoonnffeerreennccee OOrrggaanniizziinngg CCoommmmiitttteeeeGENERAL CHAIR(E)Rolf ErnstBraunschweig University ofTechnology, D

HOT TOPICS & PANELSIvo BolsensIMEC, Leuven, B

TECHNICAL PROGRAMMECHAIR(E)Dominique BorrioneTIMA, Grenoble, F

HOT TOPICS & PANELS(E)Wolfgang RosenstielEberhard-Karls-UniversityTübingen, D

PAST PROGRAM CHAIR(E)Franz RammigUniversity of Paderborn, D

PAST GENERAL CHAIR(E)Patrick DewildeDelft University ofTechnology, NL

TUTORIALS(T)Luc ClaesenIMEC/K.U.Leuven, B

HOT TOPICS & PANELS(P)Giovanni De MicheliStanford U, USA

PROCEEDINGSAnne MignotteLIP/ENS Lyon, F

POSTERS(P)Donatella SciutoPolitecnico di Milano, IT

AWARDSHugo De ManIMEC, Leuven, B

AUDIO-VISUAL(E)(P)Peter MarwedelUniversity of Dortmund, D

SPECIAL DESIGNSESSIONS(E)Richard HagelauerUniversity of Linz, A

USERS FORUM CHAIR(E)Gabriele SaucierINPG/CSI, Grenoble, F

UNIVERSITY BOOTHUdo KebschullUniversity of Leipzig, D

LOCAL & UNIVERSITYSUPPORT(P)Frank JohannesTU Munich, D

FRINGE MEETINGS(E)Bernard CourtoisTIMA, Grenoble, F

ELECTRONIC REVIEWMASTERWolfgang MüllerUniversity of Paderborn, D

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PPrrooggrraamm TTooppiicc CCoo--CChhaaiirrssSYSTEM DESIGNFlavio WagnerUFRGS, BRZ

ANALOGUEGeorges GielenKU Leuven, B

LOW POWERJacques BenkoskiMomterey Design Systems,USA

DESIGN RE-USERalf SeepoldFZI Karlsruhe, D

CASE STUDIESKlaus KronlöfNokia, FIN

FSM SYNTHESISMichel BerkelaarEindhoven University ofTechnology, NL

FORMAL VERIFICATIONPaolo CamuratiPolitecnico di Torino, IT

HDL USE(E)Wolfgang NebelUniversity of Oldenburg, D

PHYSICAL DESIGN(E)Toshiro AkinoKinki U, J

CODESIGNAhmed JerrayaTIMA, Grenoble, F

ARCHITECTURALSYNTHESISFadi KurdahiUniversity of CaliforniaIrvine, USA

SIMULATIONPeter SchwarzFhG IIS/EAS DresdenD

DESIGN LANGUAGESEugenio VillarCantabria U, ES

TEST GENERATIONBen BennettsBennetts Associates, UK

DESIGN FOR TESTABILITYEinar AasTrondheim U, N

EMBEDDED TESTYervant ZorianLogicVision , USA

xx

CCoonnffeerreennccee CCoommmmiitttteeee CCoonnttiinnuueeddEASTERN EUROPEREPRESENTATIVE& TRAVEL GRANTSMarta RenczTU Budapest, H

HANDS-ON-TUTORIALSRudy LauwereinsLeuven U, B

HOT TOPICS & PANELSKari-Pekka EstolaNokia System Design, FIN

HOT TOPICS & PANELSErich BarkeHannover U, D

PCB SYMPOSIUM(V)Catherine WeissCadence Design Systems,Munich, D

ASPDAC REPRESENTATIVET. KozawaSTARC, JP

VVeennddoorrss CCoommmmiitttteeee

Herman Beke, Frontier Design, B, (Chair)

Hans-Detlef Boesch, Verysys, D

Chris Dace, Synopsys, UK

Francoise Lindecker, Mentor Graphics, D

Ingrid Verhulst, Sagantec, NL

Catherine Weiss, Cadence, D

(E) Event Steering Board

(C) Conference Committee

(T) Topic Chairs

(P) Technical Program Panels

(V) Vendors Committee

NB: Members of more than one Committee are only pictured once with indication of other Contributions

xxi

TTeecchhnniiccaall PPrrooggrraamm CCoommmmiitttteeee

Einar Aas, University of Trondheim, NJean-Francois Agaesse, Thomson-CSF, Semiconductors, F

Toshiro Akino, Kinki University, JPPete Bakowski, IRESTE, University of Nantes, F

Alessandro Balboni, Italtel spa, ITStefano Barbagallo, Italtel spa, IT

Dave Barton, Intermetrics Inc., USAClaus Baumgartner, Robert Bosch GmbH, D

James Beausang, Synopsys Inc., USAJürgen Becker, Technical University of Darmstadt, D

Bernd Becker, University of Freiburg, DTarek Ben-Ismail, Hewlett-Packard Laboratories, UKJacques Benkoski, Monterey Design Systems, USA

Ben Bennetts, Bennetts Associates, UKAlfredo Benso, Politecnico di Torino, IT

Judith Benzakki, University of Evry Val d’Essone, FMichel Berkelaar, Eindhoven University of Technology, NL

Victor Berman, Berman Associates, USAYves Bertrand, LIRMM, F

Jayaram Bhasker, Lucent Technologies, USAGabriel Bischoff, Compaq Computer Corporation, USA

Karl Brace, Compaq Computer Corporation, USAPeter T. Breuer, University Carlos III of Madrid, ES

Gerhard Büttner, Rohde&Schwarz GmbH, DJean-Paul Calvez, IRESTE/University of Nantes, FAlbert Camilleri, Hewlett-Packard Company, USA

Paolo Camurati, Politecnico di Torino, ITBernard Candaele, Thomson-CSF Communications, F

Gunnar Carlsson, Ericsson Telecom AB, SEHerman Casier, Alcatel Microelectronics, B

Luc Claesen, IMEC/KU Leuven, BSeverine Cremoux, Synopsys Inc., F

Mark Croft, Mentor Graphics (Europe), UKWilfried Daehn, Siemens AG, D

Wayne W.-M. Dai, University of California, Santa Cruz, USAGiovanni De Micheli, Stanford University, USA

Carlos Delgado Kloos, University Carlos III of Madrid, ESMario Diaz Nava, ST-Microelectronics, F

Rolf Drechsler, Albert-Ludwigs-University Freiburg, DChristian Dufaza, LIRMM, F

Nikil Dutt, University of California, Irvine, USAWolfgang Ecker, Siemens AG, D

Wolfgang Eisenmann, Motorola GmbH, DPetru Eles, Linköping University, SEChris Ellingham, Synopsys Inc., USAGünter Elst, FhG IIS/EAS Dresden, D

Hans Eveking, Technical University of Darmstadt, D

xxii

Joan Figueras, Universita Politecnica de Catalunya, ESHans Fleurkens, Philips Research Laboratories, NL

Paulo Flores, INESC, PTMarie-Lise Flottes, LIRMM, F

William Fornaciari, Politecnico di Milano, ESJohn Forrest, Consultant, UK

Norbert Fristacky, Slovak University of Technology, SLKHideo Fujiwara, Nara Inst. of Science & Technology, JP

Steve Furber, Manchester University, UKDaniel Gajski, University of California, Irvine, USA

Philippe Garcin, ST-Microelectronics, FMark Genoe, Alcatel, B

Vassilios Gerousis, Motorola Inc., USAGeorges Gielen, KU Leuven, B

Patrick Girard, LIRMM, FWolfram Glauert, University of Erlangen-Nürnberg, D

Giulio Gorla, Italtel, ITHelmut Graeb, Technical University of Munich, D

Elena Gramatova, Slovak Academy of Sciences, SLKCarlo Guardiani, ST-Microelectronics, IT

Rajesh K. Gupta, University of California, Irvine, USAJürgen Haase, SICAN, D

Richard Hagelauer, University of Linz, AThomas Harriehausen, Siemens Semiconductors, D

Jim Heaton, ICL, UKSybille Hellebrand, University of Stuttgart, D

Ahmed Hemani, Royal Institute of Technology, SERoman Hermida, University Complutense of Madrid, ES

Ronald Herrmann, Siemens AG, DHiromi Hiraishi, Kyoto Sangyo University, JP

Mokhtar Hirech, Synopsys Inc., USAAndrzej Hlawiczka, Institute of Electronics Gliwice, POL

Steve Hodgson, ICL, UKJose Luis Huertas, CNM Seville, ESMasaharu Imai, Osaka University, JP

Geert Janssen, Eindhoven University of Technology, NLAhmed Amine Jerraya, TIMA, Grenoble, F

Frank Johannes, Technical University of Munich, DSteven D. Johnson, Indiana University, USA

Takashi Kambe, Sharp Co., JPRohit Kapur, Synopsys, USA

Tom Kazmierski, University of Southampton, UKMartin Keim, University of Freiburg, D

Hans G. Kerkhoff, MESA/University of Twente, NLHitoshi Kitazawa, NTT, JP

Michael Koch, Fachhochschule Stralsund, DJürgen Koehl, IBM Deutschland Entwicklung GmbH, D

Mario Kovac, University of Zagreb, CRStanley J. Krolikoski, Cadence Design Systems, USA

Klaus Kronlöf, Nokia Research Center, FINThomas Kropf, University of Karlsruhe, D

xxiii

Krzysztof Kuchcinski, Linköping University, SEKayhan Kucukcakar, Escalade Corporation, USA

Ramayya Kumar, Verysys, DWolfgang Kunz, University of Frankfurt, D

Fadi Kurdahi, University of California, Irvine, USAChristian Landrault, LIRMM, F

Sylvie Lasserre, Thomson-CSF TTM, FMichael Lightner, University of Colorado, Boulder, USA

Stefan Linz, Siemens AG, DJuan Carlos Lopez, UPM Madrid, ES

Enrico Macii, Politecnico di Torino, ITJan Madsen, Technical University of Denmark, DK

Hans Manhaeve, KHBO-IMEC, BGrant Martin, Cadence Design Systems, USA

Natividad Martinez Madrid, University Carlos III of Madrid, ESPeter Marwedel, University of Dortmund, D

Peter Maxwell, Hewlett-Packard Company, USAChristoph Meinel, University of Trier, D

M. Ray Mercer, Texas A&M University, USAShin-ichi Minato, NTT Optical Network Systems Labs, JP

Bert Molenkamp, University of Twente, NLJean Paul Morin, ST-Microelectronics, FEduard Moser, Robert Bosch GmbH, D

Imed Moussa, TIMA, Grenoble, FYukihiro Nakamura, Kyoto University, JP

Wolfgang Nebel, University of Oldenburg, DMichael Nicolaidis, TIMA, Grenoble, F

Kevin O’Brien, LEDA s.a., FMichael J. Ohletz, Alcatel, B

Thomas Olbrich, Austria Mikro Systeme International AG, ASerafin Olcoz, SIDSA, ES

Piero Olivo, DEIS University of Bologna, ITHidetoshi Onodera, Kyoto University, JP

Antonis Paschalis, ‘NCSR’Demokritos, GRAdam Pawlak, University of Gliwice, POL

Massoud Pedram, University of Southern California, USAZebo Peng, Linköping University, SE

Rafael Peset-Llopis, Philips Research Laboratories, NLMarkus Pfaff Johannes, Kepler University Linz, ALaurence Pierre, CMI/University of Provence, FLarry Pileggi, Carnegie Mellon University, USA

Serge Pravossoudovitch, LIRMM, FPaolo Prinetto, Politecnico di Torino, IT

Franz Rammig, C-LAB/University of Paderborn, DAndrew Richardson, Lancaster University, UK

Miquel Roca, University of the Balearic Islands (UIB), ESWolfgang Rosenstiel, Eberhard-Karls-University Tübingen, D

Bruno Rouzeyre, LIRMM, FEduardo Sanchez, EPFL, Lausanne, CH

Luis Sanchez Fernandez, University Carlos III of Madrid, ESAlberto Sangiovanni-Vincentelli, University of California, Berkeley, USA

xxiv

Gabriele Saucier, INPG/CSI, FRolf Schlagenhaft, Technical University of Munich, D

Bernd Schürmann, University of Kaiserslautern, DPeter Schwarz, FhG IIS/EAS Dresden, D

Donatella Sciuto, Politecnico di Milano, ITCarl Sechen, University of Washington, USA

Ralf Seepold, FZI Karlsruhe, DRene Segers, Philips Semiconductors, NL

Jaume Segura, University of the Balearic Islands (UIB), ESEllen Sentovich, Cadence Berkeley Laboratories, USA

Sharad Seth, University of California, Santa Barbara, USASamvel Shoukourian, Yerevan State University, ARMLeon Stok, IBM T.J. Watson Research Center, USA

Marino Strik, Philips Research Laboratories, NLJ. Paulo Teixeira, INESC/IST, PT

Ad ten Berg, Philips Research Laboratories, NLHannu Tenhunen, Royal Institute of Technology, SE

Wolfgang Thronicke, C-LAB/University of Paderborn, DMasahiko Toyonaga, Matsushita Electric Ind Co Ltd, JP

Anne-Marie Trullemans-Anckaert, UCL Laboratoire de Microelectronique, BRen-Song Tsay, Axis Corp, USA

Shuji Tsukiyama, Chuo University, JPRaimund Ubar, Tallinn Technical University, EST

Alain Vachoux, EPFL, Lausanne, CHFrank Vahid, University of California, Riverside, USAPieter van der Wolf, Philips Research Laboratories, NLJef van Meerbergen, Philips Research Laboratories, NL

Diederik Verkest, IMEC, BEugenio Villar, University of Cantabria, ES

Kees Vissers, Philips Research Laboratories, NLFlavio Wagner, UFRGS, BRZ

Kenneth D.Wagner, S3 Incorporated, USARonald Waxman, EDA Standards Consulting, USA

Catherine Weiss, Cadence Design Systems, DKarl-Heinz Weiss, FZI Karlsruhe, DT.W. Williams, Synopsys Inc., USAJohn Willis, FTL Systems Inc., USA

Wayne Wolf, Princeton University, USAMartin D.F. Wong, University of Texas at Austin, USA

Allen C.-H. Wu, Tsing Hua University, ROCHans-Joachim Wunderlich, University of Stuttgart, D

Bernd Wurth, Siemens AG, DTianruo Yang, Linköping University, SEHiroto Yasuura, Kyushu University, JP

Takeshi Yoshimura, NEC, JPNacer-Eddine Zergainoh, TIMA, Grenoble, F

Yervant Zorian, LogicVision Inc., USA

xxv

RReevviieewweerrss

The Organizing Committee gratefully acknowledges the assistance of the following persons in the review process.

Rob AitkenAlberto AllaraAlejandro AlonsoAmer BaghdadiAnupam BasuLuca BeniniSimona BernardiGiovanni BezziPeter Bjorn-JorgensenMacej CiesielskiChristoph ClaussPascal CosteDebesh K. DasRainer DoemerUlrich DonathRainer DorschKlaus EcklEko FajarJosef FleischmannJean FrehelNorbert FröhlichAndreas GerstlauerLovic GhautierUwe GlaeserPeter GrunSumit GuptaJoachim HaaseAshok HalambiJuergen HaufeFabiano HesselAkihiko InoueTomoo InoueEugeni IsernNeal JaarsmaEtienne JacobsGerd JochensLech JozwiakAsheesh KhareGundolf KieferPeter Voigt KnudsenBernd KoenemannLars Kruse

Andreas LechnerPhilippe LemarrecSalvador Lopez MendozaDenis LugiezAndres Marin LopezNatividad Martinez MadridLiviu MicleaBurkhard NeurauterDan NicolaescuTakanori OkumaTimm OstermannJean-Luc PailletSimon PickinHarald PretlAndrea QuadriniStefano QuerJaan RaikDinesh RamanathanMichel RenovellKaushik RoyKamelesh RuparelJeroen RuttenHarald SackRajesh SatapathyFrank SchenkelEike SchmidtRobert SchwenkerChuck SiskaAnna SlobodovaMatteo Sonza ReordaChristian StangierZoltan SugarRonald TangelderHiroyuki TomiyamaPeter TrappeKoen van EijkMassimo VincenziArno WagnerHajime YamashitaShuqing ZhaoJianwen Zhu

xxvi

WWeellccoommee ttoo DDAATTEE 11999999DATE99 is the single unified European event bringing together researchers, users and vendors in the field of

electronic systems design engineering. It is the successor of the very successful DATE98 which attracted close to

4,000 participants from industry and academia.

DATE99 consists of a conference with tutorials and a commercial EDA tool exhibition. The conference is

divided into a scientific part, and a user’s forum. This volume constitutes the proceedings of the scientific part,

which addresses all aspects of research into technologies for electronic systems engineering. It covers the design

process, test, and tools for design automation of electronic products ranging from integrated circuits to distributed

large-scale systems. The user’s forum, which includes a PCB symposium, focuses on design experience and

industrial methodologies; identified as track D in the program; its proceedings are edited in a separate volume.

The DATE99 keynote session entitled Embedded System Design The European Technology Driver focuses

on system design. Jouko Junkkari, VP of Nokia Mobile Phones, gives an overview of mobile electronic systems

engineering while Peter Thoma, General Manager of BMW, outlines the different world of automotive electronic

systems engineering. Finally, Tom W Williams, Chief Scientist of Synopsys, looks at test problems in very deep

submicron systems.

The main part of DATE99 consists of original scientific contributions which were selected according to the

highest international standards. The Technical Programme Committee of two hundred members, with the help of

some tens of added experts, selected the superior quality papers of this volume. The essential role of the sixteen

track chairs deserves particular recognition. Sessions on high-level design, on verification and on formal methods

constitute track A; low power design, analog circuit design and physical design share track B; embedded system

design, IP and reuse are discussed in track C; the test community will find their sessions in track E. This year, poster

presentations are tightly integrated into the regular tracks, and are reported in these proceedings as short

two-page papers.

These regular sessions are complemented by an exciting mix of special sessions on hot topics, panel sessions on

controversial developments in the field as well as educational embedded tutorials which provide background

knowledge in emerging topics, all presented by technical leaders in the respective fields; these were organized by a

Special Session Committee chaired by Ivo Bolsens.

We wish to acknowledge our sponsors for their continued support to DATE: EDAA, EDAC, IEEE CS-TTTC,

ACM SIGDA, ECSI, IFIP WG10.5, the RAS. We thank all the members of the DATE Steering Board, of the

Conference Organizing Committee and of the Program Committee, for their hard work in preparing the very high

quality edition of DATE that concludes this millenium.

We hope that you will find these DATE99 proceedings a valuable source of information, and a reference for

many years.

Rolf Ernst, General Chair

Dominique Borrione, Technical Program Chair

xxvii

BBeesstt PPaappeerr AAwwaarrddss

Each year the Design, Automation and Test in Europe Conference presents awards to the authors of the mostoutstanding papers of previous year’s conference. The selection is based on the results of the reviewing process andthe voting by the conference participants.

The paper selected as the most outstanding in the field of CAD is:

Reduced-Order Modeling of Large Linear Passive Multi-Terminal Circuits UsingMatrix-Padé Approximation

by Roland W. Freund and Peter Feldmann of Lucent Technologies, Murray Hill USA

The authors present a novel algorithm and its implementation for accurate and fast simulation of large passive RLCnetworks containing in excess of 10,000 circuit elements. Such networks occur regularly in the modeling ofinterconnect networks in deep-submicron chips.

The paper selected as most outstanding in the field of Test is:

Measuring the Effectiveness of Various Design Validation Approaches for PowerPC

by Li-C. Wang, Magdy S. Abadir of Motorola, Austin Texas and Jing Zeng of IBM,Austin, Texas USA

These authors present a systematic and quantitative evaluation of different validation techniques to detect designerrors in complex, manually designed, embedded arrays on microprocessors. They show assertion tests to be themost effective technique and propose novel methods to improve its effectiveness.

Congratulations to the winners!

xxviii

TTuuttoorriiaallss

A1 Applied Formal Hardware Verification MethodsHans Eveking, TU Darmstadt, D

There are now two main areas of successful industrial application of formal verification techniques:(a) the verification of large blocks of combinational circuits which is faster and more efficient than simulationtechniques, and (b) the checking of equivalence or of temporal properties of finite state systems. Both types offormal verification rely on the efficient representation of Boolean functions or large state spaces by means ofdecision diagrams. The tutorial will first give an introduction to various types of decision diagrams (OBDD’s,OKFDD’s, *BMD’s). Examples of successful applications of decision diagrams to large blocks of combinationalcircuits will be presented afterwards. The specific problems of using VHDL as input language will be discussed.

Symbolic state space traversal methods allow for the exploration of very large state spaces. The methods can be usedto demonstrate the equivalence of two finite state machines or to verify temporal properties by model-checking. Inaddition, many applications use model-checking as a debugging rather than as a verification tool in order to detectbugs as early as possible and to reduce design time. The tutorial will give an introduction to symbolic state spacetraversal methods, and will again consider VHDL-related aspects.

B1 Testing Embedded-Core based System ChipsErik Jan Marinissen, Philips Research, NLYervant Zorian, LogicVision, USA

Audience: IC designers, test engineers, and their managers, but also (academic) researchers, test methodologydevelopers, and test tool developers.

Abstract: Advances in semiconductor process and design technology enable the design of complex systems-on-chips. Traditional IC design, in which every circuit is designed from scratch and reuse is limited to standard-celllibraries, is more and more replaced by a design style based on embedded large reusable modules, the so-calledcores. This core-based design style poses a series of new challenges, especially in the test domain. Therefore, testingof embedded cores is one of the current Hot Topics in the international test community.

This tutorial provides an introduction into core-based design and test, and an overview of current academic andindustrial practices in core test. The current status of industry-wide standardization in VSIA and IEEE P1500 isdiscussed. The main modules of the tutorial are (1) Core-Internal Test Methods, (2) Test Access and Control forEmbedded Cores, and (3) Testing Systems-on-Chips.

C1 Towards the Full Integration of CMOS RF Circuits for Wireless CommunicationMichiel Steyaert, KU Leuven, B

For several years the research in the possibilities of CMOS technologies for RF applications has grown enormously.The trend towards deep sub-micron technologies allows the operation frequency of CMOS circuits above 1GHz,which opens the way to integrated CMOS RF circuits. Several research groups have developed high performancedown-converters, low phase noise voltage controlled oscillators and dual modulus prescalers in standard CMOStechnologies. The research has already demonstrated fully integrated receivers and VCO circuits with no externalcomponents, nor tuning or trimming. Further research on low noise amplifiers, up-converters and synthesizers hasrecently resulted in fully integrated CMOS RF transceivers for DCS-1800 applications. In this tutorial an overviewof the trend towards the full integration of front-end circuits in CMOS technologies will be addressed. Sometechnology limitations, design procedures, analysis tools and RF circuits will be analyzed and discussed in detail.

xxix

A2 Hardware/Software Co-Design and JavaAhmed Amine Jerraya, IMAG, FWayne Wolf, Princeton U, USAWolfgang Rosenstiel, U Tuebingen, D

Hardware/Software Codesign has become a strategic technology for modern electronic systems, from VLSI singlechips containing embedded cores via boards to large distributed systems made of a heterogeneous network ofprocessors communicating via sophisticated protocols. Codesign is the enabling technology for industry and mayalso be the bottleneck for faster progress. This tutorial is designed to provide the attendees with a comprehensivebackground on the state of the arts and the future of codesign.

The tutorial is structured into three parts:

1. Introduction to hardware/software codesign: This part gives the basic concepts underlying codesign andintroduces the state of the arts model and techniques used in hardware/software codesign.

2. In-depth study of hardware/software partitioning: Hardware/software co-design techniques require both analysisof design metrics such as performance and area and synthesis algorithms to optimize the design. Afterintroducing the major problems, we will survey techniques for analyzing performance and area, then use thosetechniques to discuss several different types of co-synthesis algorithms.

3. Future trends, Java for embedded systems: Originally planned for embedded systems, Java became a generalpurpose wide spread programming language. Recently many new developments revisit Java for its use in thecontext of embedded systems. This tutorial part will especially concentrate on this subject. Key words areJavaBeans, Embedded Java, Personal Java, Java Card, Jini, Java and real time operating systems, and last butnot least Java for simulation and synthesis of hardware.

B2 Test and DFT for Practising EngineersS. Yadavalli, S. Kundu, S. Sengupta, R. Galivanche, Intel, USA

This tutorial will cover practical aspects of Design For Test (DFT), Automatic Test Pattern Generation (ATPG), andthe Manufacturing Test Flow.

Commonly used fault models in the industry: stuck-at, transition and the path delay faults will be reviewed. Realisticfault models for defects such as opens and bridges will also be discussed. Practical ways of extending traditionalATPG tools to address realistic fault models will be presented. The practical aspects of modeling circuits forefficient ATPG and fault simulation will be reviewed in the context of static and dynamic CMOS circuits, as well asmemory arrays.

DFT techniques commonly practiced in industry will be reviewed in detail, with emphasis on Built-In Self-Test(BIST) and scan-based DFT schemes. Both logic and memory BIST will be covered along with solutions to relatedpractical problems that enable and enhance coverage using BIST.

The methodology collateral that goes into successful ATPG of a complex design will be discussed. This includes adiscussion of scan design rules along with their scope and motivation, techniques and algorithms for selecting scancells where full scan is not possible, and the impact of violating scan design rules. The roles of related tools such asscan insertion, scan chain reordering and fault diagnosis will be treated.

A typical manufacturing test flow will be described, showing the steps involved in testing a chip from the wafer tothe completely packaged stage. The motivation and limitation of each step will be reviewed, and the reason fordifferent measurements at each test step will be discussed. Different types of testers involved at various steps andtheir capabilities will be presented.

C2 Low Power Metrics: From Circuits to SystemsJoan Figueras, PU Catalunya, ES

The power consumption of CMOS designs is becoming a critical factor to assure portability, reliability and low costcooling in competitive electronic systems. Metrics to estimate the power in CMOS are aimed to support thepower/energy prediction techniques used by the low-power synthesis tools. Adequate models with the rightcompromise of precision and simplicity are one of the key factors to achieve competitive low power designs.

xxx

In this tutorial a bottom up approach to the power estimation problem will be presented. For each topic the state ofthe art will be surveyed and application examples discussed. Topics dealt with are: Electrical Circuit level powermodeling techniques: capacitive switching power, short circuit power, leakage power. Logic Level metrics withspecial attention to colliding transitions, glitches and hazards. At RTL and System levels the different metrics andtechniques for low power design will be discussed and applications presented.

Intended Audience: Design engineers concerned on power/energy consumption. Researchers on design and test ofelectronic systems with power/energy concerns. Managers with a need to assess future directions of electronicdesign.

IInnddeexx ooff AAuutthhoorrss

Abraham, J....................................................... 132Abramovici, M. ................................................ 747Adham, S. ........................................................ 360Agaësse, J. ....................................................... 726Al-Hashimi, B.................................................. 289Alippi, C. ......................................................... 778Alzazeri, Y....................................................... 774Antaki, B.......................................................... 360Antreich, K. ..................................................... 323Arbetman, Y. ................................................... 434Arnout, G......................................................... 384Avedill o, M...................................................... 521Bagherzadeh, N.................................................. 90Baitinger, U...................................................... 459Bampi, S. ......................................................... 776Barna, C........................................................... 689Beckmann, F. ................................................... 210Beerel, P. ........................................................... 13Benini, L.............................................77, 163, 684

Bernard, D. ...................................................... 576Bertrand, Y. ..................................................... 239Bhattacharya, M............................................... 714Bogliolo, A. ............................................... 77, 684Bolsens, I. .........................................271, 425, 616Bowen, J. ......................................................... 346Brayton, R........................................................ 138Breuer, P.......................................................... 346Buchenrieder, K. .............................................. 768Bühler, M......................................................... 459Cabodi, G.............................................................8Calvez, J. ......................................................... 782Camurati, P. .........................................................8Cano, F. ........................................................... 658Carletta, J......................................................... 278Carrabina, J...................................................... 503Carro, L. .......................................................... 184Chadha, R. ....................................................... 658Chakraborty, K................................................. 714Chang, F. ......................................................... 658Chang, J. .......................................................... 568Chatterjee, A. ............................................189, 195

Chaudhary, K....................................................581Cherubal, S.......................................................195Chiusano, S. .....................................................516Choi, J. .............................................................776Chou, M. ..........................................................396Chung, E. ...........................................................77Ciesielski, M.....................................................638Claesen, L.........................................................150Cmar, R. ...........................................................271Corlette, D........................................................788Corno, F. ..................................................516, 754Costa, J.............................................................396Cota, E. ............................................................184Dabrowksi, J.....................................................790Dalpasso, M......................................................684Dave, B. .............................................................97Dawson, C........................................................788de Armas, V......................................................509De Man, H........................................................425De Micheli, G. .............................77, 163, 217, 382de Neef, J..........................................................623Dhanwada, N. ...................................................328Dick, R. ............................................................263Doboli, A..........................................................338Donnay, S.........................................................425dos Santos, L. ...................................................609Drechsler, N. ....................................................758Drechsler, R................................................52, 758Dutt, N. ............................................................485Eckl, K. ............................................................650Eckmueller, J. ...................................................323Endo, M............................................................303Engels, M. ........................................................425Entrena, L.........................................................516Ernst, R. ...........................................................696Espejo, J. ..........................................................516Eveking, H..........................................................59Favalli, M.........................................................368Feldmann, P......................................................418Feldmann, P......................................................658Ferguson, J. ......................................................232Fernández, F. ....................................................412

Fernandez, M. .................................................... 90Ferrandi, F. ...................................................... 442Figueras, J. ................................................543, 618Filippi, E. ......................................................... 309Fleischmann, J.................................................. 768Floyd, M. ......................................................... 788Fornaciari, W. ...........................................762, 778Fournier, L. ...................................................... 434France, R.......................................................... 346Friedman, E...................................................... 643Fujita, M. ................................................... 82, 132Fummi, F. ........................................................ 442Fussell, D. ........................................................ 132Gajski, D...................................................298, 480Ganesh, V. ....................................................... 485Gerli, L. ........................................................... 442Ghosh, A.......................................................... 387Gielen, G.......................................................... 401Gizopoulos, D. ................................................. 117Glass, T............................................................ 145Gomes, A. ........................................................ 189Graeb, H. ......................................................... 323Greenstein, G. .................................................. 780Grun, P. ........................................................... 485Guerra e Silva, L. ............................................. 526Guerra, O. ........................................................ 412Gupta, A. ......................................................... 714Haase, J............................................................ 728Halambi, A....................................................... 485Hamilton, S. ..................................................... 596Haniotakis, T.................................................... 112Hazard, P. ........................................................ 239Hellebrand, S. .................................................. 702Hemani, A........................................................ 256Hendricx, S. ..................................................... 150Hermes, B. ....................................................... 232Hermida, R................................................. 90, 766Hertwig, A. ...................................................... 596Hinrichsen, H. .................................................... 59Holzheuer, H. ................................................... 498Hong, Y. ............................................................ 13Höreth, S............................................................ 52Hsiao, M. ......................................................... 175Hsu, Y................................................................ 22Huertas, J. ........................................................ 521Huhn, M............................................................. 65Hvala, B........................................................... 249

Hwang, E............................................................22Hwang, T..........................................................158Ikeda, M. ............................................................44Iwasaki, H. .......................................................303Iyer, M. ............................................................531Jacobs, E. .........................................................602Jacome, M. .......................................................676Jain, J. ..............................................................132Jantsch, A. ................................................256, 562Jäschke, C.........................................................210Jerraya, A. ........................................................696Jess, J. ..............................................................609Jha, N. ..............................................................263Jochens, G. .........................................................29Junkkari, J. .......................................................... 2Kalla, P.............................................................638Kang, S.....................................................158, 473Kapp, K. ...........................................................459Kapur, S. ..........................................................418Kaul, M. ...........................................................202Khare, A. ..........................................................485Kim, H. ............................................................473Kim, K. ............................................................158Klavzar, S.........................................................249Kloos, C. ..........................................................346Kolla, R. ...........................................................168Kondo, T. ...........................................................44Konijnenburg, M..............................................741Kranitis, N. .......................................................117Kress, R............................................................768Kropf, T..............................................................65Krupnova, H. ....................................................587Kruse, L..............................................................29Kuchcinski, K. ..................................................772Kuh, E. .............................................................664Kulkarni, S. ......................................................714Kumar, S. .........................................................256Kunkel, J. .........................................................387Kurdahi, F. .........................................................90Landrault, C......................................................576Latorre, L. ........................................................239Laur, R. ............................................................210Laurent, B.........................................................726Lauwers, E........................................................401Lavagno, L. ......................................................309Lechner, A........................................................232Legl, C. ............................................................650

Leupers, R........................................................ 105Levinger, M. .................................................... 434Liao, S. ............................................................ 387Lin, X. ............................................................. 468Liu, C............................................................... 158Liu, X. ............................................................. 643Logothetis, G. .................................................... 65Long, D............................................................ 418Lopez, J. .......................................................... 676Lubaszewski, M. .............................................. 184Maamar, A. ...................................................... 770Macii, A........................................................... 163Macii, E. .......................................................... 163Madrid, N. ....................................................... 346Maestre, R.......................................................... 90Maestro, J. ....................................................... 766Makris, Y. ........................................................ 283Manhaeve, H. ................................................... 538Mansouri, N. .................................................... 223Marques-Silva, J........................................145, 526Martínez, M. .................................................... 521Martinolle, F. ................................................... 788Maurer, P. ........................................................ 786Mazumder, P.................................................... 714Meinel, C. ........................................................ 760Merten, M. ....................................................... 747Mesman, B....................................................... 602Metra, C........................................................... 368Michael, M....................................................... 631Minami, T. ......................................................... 44Montiel-Nelson, J. ............................................ 509Morawiec, A. ................................................... 454Moser, E. ......................................................... 721Mozos, D. ........................................................ 766Mukherjee, R. .................................................. 132Müller-Schloer, C............................................. 784Murgai, R........................................................... 82Nag, S. ............................................................. 581Naganuma, J. ............................................. 44, 303Nagaraj, N........................................................ 658Nebel, W..................................... 29, 491, 720, 721Nicolaidis, M. ...................................122, 432, 792Nicolau, A........................................................ 485Nicolici, N. ...................................................... 289Niggemeyer, D. ................................................ 376Nikolos, D........................................................ 112Nitta, K. ............................................................. 44

Nooshabadi, S...................................................509Nöth, W............................................................168Nouet, P....................................................239, 576Noufal, I. ..........................................................122Nourani, M. ......................................................278Novak, F...........................................................249Núñez, A. .........................................................509Nunez-Aldana, A. .....................................328, 406O’Nils, M. ........................................................562Ochiai, K. .........................................................303Ogura, T.....................................................44, 303Orailoglu, A..............................................283, 596Papachristou, C.........................................278, 774Papaefthymiou, M.............................................643Papesch, M. ......................................................459Paschalis, A. .....................................................117Pasquier, O. ......................................................782Passerone, C. ....................................................... 8Pedram, M..................................................72, 568Peixoto, H.........................................................676Petrie, M...........................................................346Pomeranz, I. .....................................................468Poncino, M. ......................................................163Portal, J. ...........................................................618Pozzi, L. ...........................................................778Pressecq, F........................................................239Psarakis, M. ......................................................117Pulka, A............................................................790Putzke-Röming, W............................................491Quer, S. ............................................................... 8Quintana, J........................................................521Radetzki, M. .....................................................491Raik, J. .....................................................454, 736Ranjan, R..........................................................138Rayane, I. .........................................................792Reddy, S. ..........................................................468Renovell, M......................................................618Reutter, A. ..........................................................38Ribas, L. ...........................................................503Richardson, A. ..................................................232Rijnders, L........................................................271Ritter, G..............................................................59Rius, J. .............................................................543Roca, E.............................................................412Rodríguez-García, J. .........................................412Rodríguez-Vázquez, A. .....................................412Rosenstiel, W...................................... 38, 689, 764

Royo, A. .......................................................... 676Rudnick, E. ...............................................747, 780Rüffer, M. ........................................................ 376Russell, G. ....................................................... 770Sami, M. .......................................................... 778San Millán, E. .................................................. 516Sangiovanni-Vincentelli, A............................... 309Santos, M......................................................... 549Santoso, Y........................................................ 747Sarmiento, R. ................................................... 509Sasaki, H.......................................................... 353Saucier, G. ....................................................... 587Savaria, Y. ....................................................... 360Scarsi, R........................................................... 163Schaumont, P. .................................................. 271Scherber, S....................................................... 784Schilp, W. ........................................................ 786Schmidt, E. ........................................................ 29Schneider, K. ..................................................... 65Schwencker, R. ................................................ 323Sciuto, D...................................................442, 762Seepold, R........................................................ 182Sgroi, M........................................................... 309Sheehan, B. ...................................................... 669Shi, C............................................................... 448Shin, J.............................................................. 473Sidiropulos, M.................................................. 538Sil vano, C. ....................................................... 762Sil veira, L. ................................................396, 526Singh, H............................................................. 90Singhal, V. ....................................................... 138Smith, J............................................................ 217Somenzi, F. ...................................................... 138Sonza Reorda, M.............................................. 754Squill ero, G...................................................... 754Stammermann, A.............................................. 491Stangier, C. ...................................................... 760Steckstor, T...................................................... 764Stok, L. ............................................................ 531Stopjaková, V................................................... 538Strehl, K........................................................... 756Suguri, K............................................................ 44Sulli van, A. ...................................................... 531Tabbara, B. ...................................................... 309Takayama, K.................................................... 132

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Session Index

KKeeyynnoottee SSeessssiioonn -- EEmmbbeeddddeedd SSyysstteemm DDeessiiggnn TThhee EEuurrooppeeaann TTeecchhnnoollooggyy DDrriivveerr1A: Verification of Sequential Circuits

Improved techniques for the approximate and exact reachability analysis of sequential systems are presentedconsidering don’ t cares and long counting sequences.

1B: Architectural Issues in Low Power DesignDesign exploration at the architectural level is key for achieving power eff icient systems. The first paper of thissession presents a new partitioning technique for FSHD that enables efficient power management. The second paperproposes a new parameterizable macromodel for behavioral datapath components.

1C: Design Reuse Repository and IP ArchitectureThe first paper presents a reuse system that has been implemented and is used for digital circuit design. It supports“design for reuse” and “reuse of design” customised for intra-company reuse. The second paper documents a newarchitecture of a video encoder with a scalability for HDTV.

2A: High Level VerificationNovel high level verification techniques for dedicated datapath word-level decision diagrams, imprecise arithmetic,as well as for automatic scheduling and model checking are presented.

2B: System-Level Power OptimizationPower optimisation at the system level is recognised as an increasingly important task. The first paper in this sessionintroduces a new way of looking at the problem by considering battery li fe in the cost function used for theoptimisation. The second paper deals with OS-based power management of non stationary workloads. Finally, thethird paper proposes new encoding schemes for reducing interface power.

2C: Reconfigurability and Other Issues in Embedded System DesignThis session focuses on the challenges and opportunities that reconfigurable platforms offer for co-design andemulation of embedded systems. Further issues addressed are code generation for embedded VLIW processors andthe role of high-level estimations to decide on resource sharing.

2E: Embedded Core Test ApproachesThis session brings a number of solutions for testing embedded cores. From delay fault testing to functional testingof cores used in today’s system-on-chip.

3A: Use of Combinational VerificationCore techniques of combinational verification may be combined or can be applied to sequential verification

problems.3B: Gate Level Power Estimation and Optimization

This session addresses logic synthesis for low power issues. The first paper introduces a set of logic transformationsthat enable power reductions of gate-level netlists. The second paper proposes a new approach for post layout glitchpower minimisation. A novel state encoding algorithm is presented in the third contribution. Finally, the fourthpaper deals with peak power estimation methods.

3C: Special Session Virtual Socket Interface AllianceThe first presentation wil l present the technical objectives and background of the work of VSI All iance. The drivingfactors and actual achievements will be shown in the context of actual research, development and standardizationtrends. The second talk is focused on Virtual prototyping of complete mixed hardware (HW)-software (SW) systemsthat require well-defined multi-level description of the VC interfaces. The third presentation will introduce the VSIVirtual Component Interface, and show how this can map the transactions used in System Level Design onto a rangeof on-chip bus implementations for different cost/performance tradeoffs.

3E: Fault Diagnosis Techniques for Analogue CircuitsThis session presents new techniques to diagnose faults in analogue circuits. The first method consists of using anadaptive tester that learns a reference behaviour in a first step. The second method uses information coming fromprevious samples to resolve ambiguities. The last method consists of using a non-linear regression model using priorcircuit simulations.

4A: Resource Sharing in Architectural SynthesisThis session addresses different resource sharing approaches. Whereas the first paper concentrates on temporalpartitioning of reconfigurable processors, the second paper discusses resource sharing among multiple processes,while the third one deals with optimising the allocation of complex components. The last paper investigates postsynthesis formal verification of RTL designs generated by high level synthesis.

4B: Mixed Signal Characterization and TestProblems relating to characterisation and test of complex mixed signal systems will be addressed in this session. Thefirst paper will present a digital partial BIST solution for an AGC that aims to reduce test time and complexity. Thesecond paper will look at characterisation and modelling issues in a new magnetic field sensor and the final twoshort papers will address the problems of analogue simulation and test response handling.

4C: System Design Methodologies: Modelling, Analysis, Refinement and SynthesisThe first paper presents main concepts in the electronic system design such as: modelling, analysis and synthesis.The second paper addresses a system synthesis algorithm which partitions and schedules embedded systemsspecifications to intellectual property cores in an integrated circuit. Finally, the third paper proposes a refinementmethodology to move the DSP functions from a floating point to a fixed point representation in the case ofimplementing these functions in hardware (ASIC).

4E: High Level Test SynthesisThis session deals with high-level synthesis of testable designs. The first paper presents a technique to test datapath-controller pairs in an integrated fashion. The second paper addresses the issues of module reachability for testpurpose during high-level synthesis. The last paper describes a BIST insertion technique used in a partial intrusionBIST environment.

5A: High-Level System SimulationThe design of a complex system (like that of an MPEG encoder) needs improved simulation methods on higherlevels of abstraction. Fast instruction set simulation, C-based simulation and VHDL-based HW/SW-cosimulationare very promising methods. Three posters present additional approaches for modelling and simulation of complexsystems.

5B: Analogue Circuit Sizing and SynthesisNew developments in analogue circuit sizing and synthesis are discussed, both at the level of basic circuits andhigher levels. First, a systematic biasing method is presented. Next, an automatic sizing approach that considersstructural constraints. Finally, constraint transformation at higher levels is described.

5C: VHDL-AMS and HDL InteroperabilityThe papers in this session cover various aspects of analogue and mixed-signal modelling using VHDL and VHDL-AMS as well as mixed-language hardware description issues, VHDL-Verilog interoperability and formal semantics.

5E: Transistor Level TestTransistor level DFT for Current Mode Logic is addressed in the first paper. The next paper deals with pass-transistor implementations of self-checking circuits. The last paper presents a new approach for parametric on-chiptesting.

6A: Hot Topic Hardware Synthesis from C/C++ ModelsDesigners often use programming languages to model hardware, because of the ease of simulating the high-levelbehaviour (possibly in conjunction with software), of migrating software code to hardware and of using legacymodels. Hardware synthesis from programming language models is challenging, due to the lack of an underlyinghardware semantics. Nevertheless, synthesis from C/C++ subsets has become reality, and this session wil presentcurrent approaches, their advantages and limitations.

6B: Analogue Modelling and SimulationThe first paper deals with substrate coupling modelling. The second paper presents a new model for high-levelperformance estimation of converters. The following two papers present qualitative performance modelling forsimulation oriented synthesis and efficient symbolic performance modelling.

6C: Hot Topic Chip Package Co-DesignTraditionally there has been very limited interaction between IC design and packaging design. It is expectedhowever, that for some applications the increasingly aggresive system performance requirements will necessitate aconcurrent design of ICs and packages in the future. For high-performant systems, chip-package co-design meansthe optimal distribution of the routing between on-chip and off-chip interconnections. Also, future telecom productswill benefit from the availiability of these integrated passives to achieve lower cost, better performance and fasterdevelopment time. Finally, the modeling and simulation problems have to be addressed. An overview of existingsolution techniques, such as efficient extraction algorithms and reduced-order modeling methods will be presented.Current challenges and open problems will also be discussed.

6E: Panel Scaling Towards Nanometer Technologies: Design for Test ChallengesThe continuous scaling in microelectronics results in numerous challenges that test technology should overcome,such as reduced noise margins; reduced accessibility; increased inadequacy between IC generations and AutomaticTest Equipment, and complex defect behavior, making performance and other spurious faults predominant. Thepanel will discuss the relevance of these challenges to nanometer technologies and try to identify potential solutionsfor them.

7A: Functional VerificationFunctional correctness assessment represents one of the primary and most time-consuming tasks of the completedesign process. In this session, two different approaches to the problem are presented. The first one describes arigorous methodology for microprocessor design verification. The second presents a new approach for functionalvector generation based on a precise behavioural error model and a controllability metric on VHDL code coverageevaluation.

7B: Bit-Level Logic and Analogue SimulationDecision Diagrams related to the well-known BDDs offer a new method for improved simulation efficiencyboth in the analogue and digital area. The symbolic calculation of the transfer function of linear systems givesadditional insight into the main functionality of analogue circuits. Precise delay models (covering hazards andglitches) and effective bitparallel evaluation is the basis of switching activity simulation especially as applied inlow-power design

7C: Panel Standards Roadmap for the 21st CenturyThe well known growth in complextiy of electronic systems has pushed designers towards the use of standardsmethods to deal with this complexity and with shrinking time to market requirements. The standards developmentprocess has unfortunately not kept pace with this increased need. In an effort to cope with this problem, manyindustry consortiums such as VSIA, EDA Industry Council and EDAC have been formed to rationalize the approachto standards development. One typical emphasis has been to circumvent the traditional standards developmentbodies in the hope of speeding up the process and focusing in on specific industry needs. Arguably, this approachhas actually slowed the process and injected a health dose of company politics into an otherwise cooperativeventure.

7E: Partial and Boundary Scan TestAn original 3-phase procedure based on structural and functional analysis for partial scan is presented, together witha novel solution to execute dynamic interconnect test at the board level.

8A: New Languages for System Specification and DesignThis session presents new languages for heterogeneous system specifications, to support design space explorationand an optimization strategy for synthesis of data types from high level specifications.

8B: Circuit Analysis and DesignThe first paper presents a knowledge enriched approach for signal integrity analysis. Automatic recognition andmodelling of logic gates out of a switch-level network is the topic of the second paper. Finally, the design of fastarithmetic circuits using GaAs based Feed Through Logic is presented.

8C: Logic SynthesisThis session contains four papers which advance the state-of-the-art in various basic logic synthesis techniques.

8E: IDDX Testing and Defect ModellingDefect modelling and defect detection are very important for test. This session explores traditional IDDQ testingplus IDDT testing, where T=transient. In addition, defect-oriented fault simulation is presented.

9A: HW/SW Interface Synthesis and PartitioningThe papers presented in this session concentrate on interface synthesis and partitioning of HW/SW embeddedsystems. The first paper combines software synthesis and automatic HW/SW interface generation to meet hard real-time constraints for digital communication systems. Generation of the software part of the HW/SW interface is thetopic of the second paper. The third paper discusses the use of dynamic programming for HW/SW partitioning andmapping of communicating processes.

9B: Physical Design IssuesIn this session three different aspects of physical design are discussed. The first paper presents a set of analyticalformulations for 3D modelling of interlayer capacitances. In the second paper the sequence-pair approach is appliedto systematically remove overlaps between placed objects. An improved iterative partitioning method for FPGAs isproposed in the third paper.

9C: Reliability and Symmetry in Architectural SynthesisThe first paper discusses the synthesis of reliable self recovering architectures while avoiding redundancies in thecontroller. The last two papers exploit symmetries in architectural synthesis in order to speed -up the design tools.

9D: Panel Single Chip or Hybrid System Integration?If we continue to increase the complexity of ICs at the same pace as we did from 1960 onwards, this complexity willhave reached half a billion transistors per chip, within a decade from now. And the clock period is “expected” to bewell below the one nanosecond. This panel will discuss future trends of cost, power, speed, reliability and signalintegrity. If we don’t believe these excessive numbers, design styles and methods as well as integration technologyneed to be changed to cope with the complexity and performance of future embedded systems This panel willdiscuss the consequences for deep-submicron IC design and possible way outs for the roadblocks.

9E: Testing Regular Structures and Delay FaultsThis session includes presentations on minimum length test patterns for SRAM-based FPGA structures, industrialevaluation of a large number of memory test algorithms on DRAM circuits, and functional ATPG tools for delayfaults.

10A: RetimingThis session presents three papers which extend the usability of retiming in asynthesis environment.

10B: Modelling of InterconnectsIn deep submicron design the modelling of interconnect becomes increasingly important. The first paper describestechnologies for the modelling and analysis of parasitic coupling effects for large VLSI design. The other two paperspresent different approaches to modelling and reduction of interconnect networks.

10C: Design Reuse Methodologies for Virtual Components and IPThe first paper presents a design space layer that is introduced to support both IP-based design methodologies andtraditional design methodologies. The second paper introduces a Java-CAD framework that uses remote componentsand that supports secure Internet protocol for a smooth transition between component evaluation. The third paperpresents a methodology to decrease re-design effort. This methodology is implemented on an already existing reusemanagement system.

10D: Embedded Tutorial Multilanguage System DesignThe design of large systems, like a mobile telecommunication terminal or the electronic parts of an airplane or a car,may require the participation of several groups belonging to different companies and using different design methods,languages and tools. The concept of multilanguage specification aims at coordinating different cultures through theunification of the languages, formalism, and notations. There are two main approaches for multilanguage design: thecompositional approach and the cosimulation-based approach. The compositional approach aims at integrating thepartial specification of sub-systems into a unified representation which is used for the verification and design of theglobal behavior. The cosimulation-based approach consists in interconnecting the design environments associated toeach of the partial specifications. Compared with the deep specification integration accomplished by thecompositional approaches, cosimulation is an engineering solution to multilanguage design that performs just ashallow integration of the partial specifications. This session discusses the key issues for multilanguage systemdesign.

10E: RAM BISTThe first two papers address built-in self-test of Random Access Memories. Symmetric transparent BIST ispresented as a self-test method that does not destroy the content of the RAM. The second paper presentsarchitectural differences of BIST engines for RAMs. The authors of the third paper discuss self repair of RAMs andthe implications on yield.

11B: Panel Java, VHDL-AMS, Ada or C for System Level Specifications?The technical panel will compare and discuss the suitablity of new and established languages for creating executablespecifications of heterogeneous embedded systems. The comparison will be made by champions of the languagesbased on a common example. In particular the panel will focus on issues like modelling efficiency in differentdomains, execution performance and reusability.

11C: Hot Topic IP and ReuseThe session will present different views on the same hot topic : IP and Reuse from the perspective of the IP providerand the IP user. Discussing and presenting each viewpoint, while the topic will be introduced by the state of the artpresentation to guide participants into the reuse domain. At the end, a panel discussion is planned to invite theattendees to actively participate in the discussion by asking burning questions to the presentors

11D: Special Session Large European Programs in Microelectronic System and Circuit DesignVery large European programs in Microelectronic System and Circuit Design are presently under way or beingdesigned. The scope and breadth of these programs is very large, with many companies and research groupsparticipating. The speakers at this hot topic session are executives who are primarily responsible for these programs.They will present achievements of ongoing programs and future plans of continuing and starting programs. Thepresentations will be followed by a discussion on the method and the principles.

11E: Sequential Circuit Test GenerationThe first paper presents a novel approach to testing sequential circuits by using multi-level decision diagrams. Thesecond paper presents an ATPG system which focuses on discovering the illegal state space. The last contributionintroduces a new testing strategy based on a frozen clock strategy which temporarily suspends the sequentialbehaviour of the circuit.

Posters