CSE 140 Discussion SectionMidterm #2 ReviewMingjing Chen

Flip-Flops ConversionImplement a JK flip-flop with a SR flip-flop and a minimal AND-OR-NOT network. Solve the combinational logic design problemS = f1(J, K, Q)R = f2(J, K, Q)

Flip-Flops ConversionHow to attain the specification of the combinational circuit?

S = f1(J, K, Q)R = f2(J, K, Q)Truth table for combinational logic0xx0x00x01101001

JKQprevQSR00000011010001101001101111011110

Flip-Flops ConversionTruth table for combinational logic0xx0x00x011010010001111001JKQprevKmap for SS = J Qprev0001111001JKQprevKmap for RR = K Qprev

JKQprevQSR00000011010001101001101111011110

xx000110

Sequential Circuit DesignA state machine is described by the following state equations.(1). Write the state table.2-bit states: Q1, Q01 input: x1 output: y

Sequential Circuit DesignDesign the system with two JK flip-flops and a minimal AND-OR-NOT network.

0Xx11Xx00Xx00Xx0

Sequential Circuit Designxx01xx100001111001Q1Q0XKmap for J1J1 = XQ0+XQ001xx10xx0001111001Q1Q0XKmap for K1K1 = X Q0+X Q00xx01xx00001111001Q1Q0XKmap for J0x00xx01x0001111001Q1Q0XKmap for K0J0 = XQ1K0 = X Q1011101110001111001Q1Q0XKmap for yy = Q1+Q0

XQ1(t)Q0(t)J1K1J0K0y00010011010001111001101111001111

0X1Xx1x01X0Xx0x1

0Xx11Xx00Xx00Xx0

TimingCircuit implemented using two T flip-flops and a D flip-flop.Timing characteristics:T flip-flop: clock-to-Q maximum delay tpcq = 2nsclock-to-Q minimum delay tccq = 1.8nssetup time tsetup = 1nshold time thold = 1.5nsD flip-flop: clock-to-Q maximum delay tpcq = 2.5nsclock-to-Q minimum delay tccq = 2.3nssetup time tsetup = 2.5nshold time thold = 2nsNAND gate: propagation delay tpd = 1nscontamination delay tcd = 0.8nsInverter: propagation delay tpd = 0.5nscontamination delay tcd = 0.3ns

TimingHow many paths?TQTQDQ

Timing3 pathsTQTQDQP1P2P3

TimingWhat is the maximum clock frequency of this circuit?P1: tpcq(D) + tpd(NAND) + tsetup(T)

Timingwhat is the maximum clock skew that the circuit can tolerate before it might experience a hold time violation?

P1: tccq(D) + tcd(NAND) >= thold(T) + skewP2: tccq(T) + tcd(NOT) >= thold(D) + skewP3: tccq(T) + tcd(NAND) >= thold(T) + skew2.3 + 0.8 >= 1.5 + skew1.8 + 0.3 >= 2 + skew1.8 + 0.8 >= 1.5 + skewMax skew = 0.1ns

Decoder & MUXthree-input Boolean function f(a, b, c) = Pm(1, 2, 4, 7) + Pd(3)01x110100001111001abcf = abc + a'bc + abc + abc + (abc)

Decoder & MUXImplement the function using a minimal network of 2:4 decoders and OR gatesf = abc + a'bc + abc + abc + (abc) = abc + a'bc + abc + abc0123s1s00123s1s0InIncabab

Decoder & MUXImplement the function using a minimal network of 4:1 multiplexers.f = abc + a'bc + abc + abc + (abc) = abc + a'bc + abc + abc0123s1s0abOutcccc

Decoder & MUXImplement the function using a minimal network of 2:1 multiplexersf = ac+ab+bc+abc = af(1, b, c) + af(0, b, c) = a(bc+bc) + a (b+c)a10sb10sccb10s1c