CSD87355Q5D Synchronous Buck NexFET™ Power … · Output Current (A) Efficiency (%) Power Loss (W) 0 5 10 15 20 25 30 35 40 45 74 0 76 1 78 2 80 3 82 4 84 5 86 6 88 7 90 8 92 9

Output Current (A)

Effi

cien

cy (

%)

Pow

er L

oss

(W)

0 5 10 15 20 25 30 35 40 4574 0

76 1

78 2

80 3

82 4

84 5

86 6

88 7

90 8

92 9

94 10

96 11

D000

VGS = 5 VVIN = 12 VVOUT = 1.3 VLOUT = 0.29 PHfSW = 500 kHzTA = 25qC

VDDBOOT

VDD

ENABLE

PWM

VIN

VIN

VOUT

Driver ICCSD87355Q5D

TG Control FET

Sync FET

DRVH

LL

DRVL

GND

ENABLE

PWM

VSW

PGND

TGR

BG

P0116-01

1

2

3 VSW

VSW

VSW

4 BG5TGR

6TG

PGND

(Pin 9)

7VIN

8VIN

Product

Folder

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Now

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

CSD87355Q5DSLPS575A –MARCH 2016–REVISED SEPTEMBER 2017

CSD87355Q5D Synchronous Buck NexFET™ Power Block

1

1 Features1• Half-Bridge Power Block• 92.5% System Efficiency at 25 A• Up to 45-A Operation• High-Frequency Operation (Up to 1.5 MHz)• High-Density SON 5-mm × 6-mm Footprint• Optimized for 5-V Gate Drive• Low Switching Losses• Ultralow Inductance Package• RoHS Compliant• Halogen Free• Pb-Free Terminal Plating

2 Applications• Synchronous Buck Converters

– High-Frequency Applications– High-Current, Low Duty Cycle Applications

• Multiphase Synchronous Buck Converters• POL DC-DC Converters• IMVP, VRM, and VRD Applications

3 DescriptionThe CSD87355Q5D NexFET™ power block is anoptimized design for synchronous buck applicationsoffering high-current, high-efficiency, and high-frequency capability in a small 5-mm × 6-mm outline.Optimized for 5-V gate drive applications, this productoffers a flexible solution capable of offering a high-density power supply when paired with any 5-V gatedrive from an external controller/driver.

TEXT ADDED FOR SPACINGTop View

.Ordering Information(1)

Device Media Qty Package Ship

CSD87355Q5D 13-Inch Reel 2500 SON 5 mm × 6 mmPlastic Package

Tape andReelCSD87355Q5DT 7-Inch Reel 250

(1) For all available packages, see the orderable addendum atthe end of the data sheet.

TEXT ADDED FOR SPACING

TEXT ADDED FOR SPACING

TEXT ADDED FOR SPACINGTypical Circuit Typical Power Block Efficiency and Power Loss

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CSD87355Q5DSLPS575A –MARCH 2016–REVISED SEPTEMBER 2017 www.ti.com

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Table of Contents1 Features .................................................................. 12 Applications ........................................................... 13 Description ............................................................. 14 Revision History..................................................... 25 Specifications......................................................... 3

5.1 Absolute Maximum Ratings ...................................... 35.2 Handling Ratings....................................................... 35.3 Recommended Operating Conditions....................... 35.4 Thermal Information .................................................. 35.5 Power Block Performance ........................................ 35.6 Electrical Characteristics........................................... 45.7 Typical Power Block Device Characteristics............. 55.8 Typical Power Block MOSFET Characteristics......... 7

6 Application and Implementation ........................ 10

6.1 Application Information............................................ 106.2 Typical Application .................................................. 13

7 Layout ................................................................... 157.1 Layout Guidelines ................................................... 157.2 Layout Example ...................................................... 16

8 Device and Documentation Support.................. 178.1 Community Resources............................................ 178.2 Trademarks ............................................................. 178.3 Electrostatic Discharge Caution.............................. 178.4 Glossary .................................................................. 17

9 Mechanical, Packaging, and OrderableInformation ........................................................... 189.1 Q5D Package Dimensions...................................... 189.2 Land Pattern Recommendation .............................. 199.3 Stencil Recommendation ........................................ 19

4 Revision History

Changes from Original (March 2016) to Revision A Page

• Added footnote for ZDS(ON) in the Electrical Characteristics table. ......................................................................................... 4• Deleted the Q5D Tape and Reel Information section .......................................................................................................... 19

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3

CSD87355Q5Dwww.ti.com SLPS575A –MARCH 2016–REVISED SEPTEMBER 2017

Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Pulse duration ≤ 50 µS. Duty cycle ≤ 0.01.

5 Specifications

5.1 Absolute Maximum RatingsTA = 25°C (unless otherwise noted) (1)

MIN MAX UNIT

VoltageVIN to PGND –0.8 30 VTG to TGR –8 10 VBG to PGND –8 10 V

Pulsed current rating, IDM(2) 120 A

Power dissipation, PD 12 W

Avalanche energy EASSync FET, ID = 89 A, L = 0.1 mH 396 mJControl FET, ID = 50 A, L = 0.1 mH 125 mJ

Operating junction temperature, TJ –55 150 °C

5.2 Handling RatingsMIN MAX UNIT

Tstg Storage temperature range –55 150 °C

5.3 Recommended Operating ConditionsTA = 25° (unless otherwise noted)

MIN MAX UNITVGS Gate drive voltage 4.5 10 VVIN Input supply voltage 27 VƒSW Switching frequency CBST = 0.1 μF (min) 200 1500 kHz

Operating current 45 ATJ Operating temperature 125 °C

(1) Device mounted on FR4 material with 1 inch2 (6.45 cm2) Cu.(2) RθJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inches × 1.5 inches

(3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s boarddesign.

5.4 Thermal InformationTA = 25°C (unless otherwise stated)

THERMAL METRIC MIN TYP MAX UNIT

RθJAJunction-to-ambient thermal resistance (min Cu) (1) (2) 102 °C/WJunction-to-ambient thermal resistance (max Cu) (1) (2) 50 °C/W

RθJCJunction-to-case thermal resistance (top of package) (2) 20 °C/WJunction-to-case thermal resistance (PGND pin) (2) 2 °C/W

(1) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins andusing a high current 5 V driver IC.

5.5 Power Block PerformanceTA = 25° (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Power loss, PLOSS(1)

VIN = 12 V, VGS = 5 V, VOUT = 1.3 V,IOUT = 25 A, ƒSW = 500 kHz,LOUT = 0.29 µH, TJ = 25ºC

2.8 W

VIN quiescent current, IQVIN TG to TGR = 0 V ,BG to PGND = 0 V 10 µA

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HD

HG

LG

LD

M0189-01

5x6 Q

FN

TTA

MIN

Rev1

LS

HS

HD

HG

LG

LD

M0190-01

5x6 Q

FN

TTA

MIN

Rev1

LS

HS

4



(1) Equivalent based on application testing. See Application and Implementation section for details.

5.6 Electrical CharacteristicsTA = 25°C (unless otherwise stated)

PARAMETER TEST CONDITIONSQ1 CONTROL FET Q2 SYNC FET

UNITMIN TYP MAX MIN TYP MAX

STATIC CHARACTERISTICSBVDSS Drain-to-source voltage VGS = 0 V, IDS = 250 μA 30 30 VIDSS Drain-to-source leakage current VGS = 0 V, VDS = 24 V 1 1 μA

IGSSGate-to-source leakage current VDS = 0 V,

VGS = +10 / –8 V 100 100 nA

VGS(th) Gate-to-source threshold voltage VDS = VGS, IDS = 250 μA 1.00 1.90 0.75 1.20 V

ZDS(ON)(1) Drain-to-source ON impedance

VIN = 12 V, VGS = 5 V,VOUT = 1.3 V, IOUT = 25 A,ƒSW = 500 kHz,LOUT = 0.29 µH

3.9 0.9 mΩ

gfs Transconductance VDS = 3 V, IDS = 20 A 90 151 SDYNAMIC CHARACTERISTICSCISS Input capacitance

VGS = 0 V, VDS = 15 V,ƒ = 1 MHz

1430 1860 3570 4640 pFCOSS Output capacitance 716 930 1730 2240 pFCRSS Reverse transfer capacitance 25 32 52 67 pFRG Series gate resistance 0.6 1.2 0.7 1.4 Ω

Qg Gate charge total (4.5 V)

VDS = 15 V,IDS = 20 A

10.5 13.7 24.3 31.5 nCQgd Gate charge – gate-to-drain 2.3 4.1 nCQgs Gate charge – gate-to-source 3.2 5.6 nCQg(th) Gate charge at Vth 1.7 2.8 nCQOSS Output charge VDS = 15 V, VGS = 0 V 18 40 nCtd(on) Turn on delay time

VDS = 15 V, VGS = 4.5 V,IDS = 20 A, RG = 2 Ω

8 10 nstr Rise time 18 14 nstd(off) Turn off delay time 13 27 nstf Fall time 3 6 nsDIODE CHARACTERISTICSVSD Diode forward voltage IDS = 20 A, VGS = 0 V 0.8 1.0 0.8 1.0 VQrr Reverse recovery charge Vdd = 17 V, IF = 20 A,

di/dt = 300 A/μs43 82 nC

trr Reverse recovery time 23.8 32.3 ns

Max RθJA = 50°C/Wwhen mounted on1 inch2 (6.45 cm2) of2 oz. (0.071-mm thick)Cu.

Max RθJA = 102°C/Wwhen mounted onminimum pad area of2 oz. (0.071-mm thick)Cu.

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Ambient Temperature (qC)

Out

put C

urre

nt (

A)

0 10 20 30 40 50 60 70 80 900

5

10

15

20

25

30

35

40

45

50

D003

400 LFM200 LFM100 LFMNat. conv.

Board Temperature (qC)

Out

put C

urre

nt (

A)

0 15 30 45 60 75 90 105 120 1350

5

10

15

20

25

30

35

40

45

50

D005

Output Current (A)

Pow

er L

oss

(W)

0 5 10 15 20 25 30 35 40 450

1

2

3

4

5

6

7

8

9

10

D001 Junction Temperature (qC)

Pow

er L

oss,

Nor

mal

ized

-50 -25 0 25 50 75 100 125 1500.5

0.6

0.7

0.8

0.9

1

1.1

D002

5



5.7 Typical Power Block Device CharacteristicsTJ = 125°C, unless stated otherwise. The Typical Power Block System Characteristic curves Figure 3, , and Figure 4 arebased on measurements made on a PCB design with dimensions of 4” (W) × 3.5” (L) × 0.062” (H) and 6 copper layers of 1-oz. copper thickness. See Application and Implementation for detailed explanation.

VIN = 12 V VGS = 5 V VOUT = 1.3 VƒSW = 500 kHz LOUT = 0.29 µH

Figure 1. Power Loss vs Output Current


Figure 2. Normalized Power Loss vs Temperature


Figure 3. Safe Operating Area (SOA) – Thermal AirflowMeasurement PCB Vertical Mount


Figure 4. Typical Safe Operating Area (SOA)

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Output Voltage (V)

Pow

er L

oss,

Nor

mal

ized

SO

A T

empe

ratu

re A

dj. (qC

)

0.5 1.3 2.1 2.9 3.7 4.5 5.30.8 -6.4

1 0.0

1.2 6.4

1.4 12.9

1.6 19.3

1.8 25.7

D008Output Inductance (nH)

Pow

er L

oss,

Nor

mal

ized

SO

A T

empe

ratu

re A

dj. (qC

)

10 150 290 430 570 710 850 990 11300.925 -2.5

0.95 -1.7

0.975 -0.8

1 0.0

1.025 0.8

1.05 1.7

1.075 2.5

1.1 3.4

D009

Switching Frequency (kHz)

Pow

er L

oss,

Nor

mal

ized

SO

A T

empe

ratu

re A

dj. (qC

)

50 200 350 500 650 800 950 1100 1250 1400 15500.8 -7.0

0.9 -3.5

1 0.0

1.1 3.5

1.2 7.0

1.3 10.4

1.4 13.9

1.5 17.4

D006Input Voltage (V)

Pow

er L

oss,

Nor

mal

ized

SO

A T

empe

ratu

re A

dj. (qC

)

0 3 6 9 12 15 180.9 -3.3

0.95 -1.7

1 0.0

1.05 1.7

1.1 3.3

1.15 5.0

1.2 6.7

1.25 8.3

1.3 10.0

1.35 11.7

D007

6



Typical Power Block Device Characteristics (continued)TJ = 125°C, unless stated otherwise. The Typical Power Block System Characteristic curves Figure 3, , and Figure 4 arebased on measurements made on a PCB design with dimensions of 4” (W) × 3.5” (L) × 0.062” (H) and 6 copper layers of 1-oz. copper thickness. See Application and Implementation for detailed explanation.

VIN = 12 V VGS = 5 V VOUT = 1.3 VLOUT = 0.29 µH IOUT = 45 A

Figure 5. Normalized Power Loss vs Switching Frequency

VIN = 12 V VOUT = 1.3 V LOUT = 0.29 µHƒSW = 500 kHz IOUT = 45 A

Figure 6. Normalized Power Loss vs Input Voltage

VIN = 12 V VGS = 5 V ƒSW = 500 kHzLOUT = 0.29 µH IOUT = 45 A

Figure 7. Normalized Power Loss vs. Output Voltage

VIN = 12 V VGS = 5 V VOUT = 1.3 VƒSW = 500 kHz IOUT = 45 A

Figure 8. Normalized Power Loss vs Output Inductance

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Qg - Gate Charge (nC)

VG

S -

Gat

e-to

-Sou

rce

Vol

tage

(V

)

0 2 4 6 8 10 12 14 16 18 200

1

2

3

4

5

6

7

8

D014Qg - Gate Charge (nC)

VG

S -

Gat

e-to

-Sou

rce

Vol

tage

(V

)

0 4 8 12 16 20 24 28 32 36 40 440

1

2

3

4

5

6

7

8

D015

VGS - Gate-to-Source Voltage (V)

I DS -

Dra

in-t

o-S

ourc

e C

urre

nt (

A)

0 0.5 1 1.5 2 2.5 3 3.50.001

0.01

0.1

1

10

100

D012

TC = 125° CTC = 25° CTC = -55° C


I DS -

Dra

in-t

o-S

ourc

e C

urre

nt (

A)

0 0.5 1 1.5 2 2.50.001

0.01

0.1

1

10

100

D013

TC = 125° CTC = 25° CTC = -55° C

VDS - Drain-to-Source Voltage (V)

I DS -

Dra

in-t

o-S

ourc

e C

urre

nt (

A)

0 0.04 0.08 0.12 0.16 0.20

10

20

30

40

50

60

70

80

90

100

D011

VGS = 4.5 VVGS = 6.0 VVGS = 8.0 V


I DS -

Dra

in-t

o-S

ourc

e C

urre

nt (

A)

0 0.1 0.2 0.3 0.4 0.50

10

20

30

40

50

60

70

80

90

100

D010

VGS = 4.5 VVGS = 6.0 VVGS = 8.0 V

7



5.8 Typical Power Block MOSFET CharacteristicsTA = 25°C, unless stated otherwise.

Figure 9. Control MOSFET Saturation Figure 10. Sync MOSFET Saturation

VDS = 5 V

Figure 11. Control MOSFET Transfer

VDS = 5 V

Figure 12. Sync MOSFET Transfer

ID = 20 A VDD = 15 V

Figure 13. Control MOSFET Gate Charge

ID = 20 A VDD = 15 V

Figure 14. Sync MOSFET Gate Charge

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RD

S(o

n) -

On-

Sta

te R

esis

tanc

e (m:

)

0 1 2 3 4 5 6 7 8 9 100

2

4

6

8

10

12

14

D020

TC = 25° C, I D = 20 ATC = 125° C, I D = 20 A


RD

S(o

n) -

On-

Sta

te R

esis

tanc

e (m:

)

0 1 2 3 4 5 6 7 8 9 100

1

2

3

4

5

6

7

8

D021

TC = 25° C, I D = 20 ATC = 125° C, I D = 20 A

TC - Case Temperature (° C)

VG

S(t

h) -

Thr

esho

ld V

olta

ge (

V)

-75 -50 -25 0 25 50 75 100 125 150 1750.6

0.8

1

1.2

1.4

1.6

1.8

D018 TC - Case Temperature (° C)

VG

S(t

h) -

Thr

esho

ld V

olta

ge (

V)

-75 -50 -25 0 25 50 75 100 125 150 1750.3

0.4

0.5

0.6

0.7

0.8

0.9

1

1.1

1.2

1.3

D019


C -

Cap

acita

nce

(pF

)

0 3 6 9 12 15 18 21 24 27 301

10

100

1000

10000

D016

Ciss = Cgd + CgsCoss = Cds + CgdCrss = Cgd


C -

Cap

acita

nce

(pF

)

0 3 6 9 12 15 18 21 24 27 301

10

100

1000

10000

D017

Ciss = Cgd + CgsCoss = Cds + CgdCrss = Cgd

8



Typical Power Block MOSFET Characteristics (continued)TA = 25°C, unless stated otherwise.

ƒ = 1 MHz VGS = 0

Figure 15. Control MOSFET Capacitance

ƒ = 1 MHz VGS = 0

Figure 16. Sync MOSFET Capacitance

ID = 250 µA

Figure 17. Control MOSFET VGS(th)

ID = 250 µA

Figure 18. Sync MOSFET VGS(th)

Figure 19. Control MOSFET RDS(ON) vs VGS Figure 20. Sync MOSFET RDS(ON) vs VGS

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TAV - Time in Avalanche (ms)

I AV -

Pea

k A

vala

nche

Cur

rent

(A

)

0.01 0.1 11

10

100

1000

D026

TC = 25q CTC = 125q C

TAV - Time in Avalanche (ms)

I AV -

Pea

k A

vala

nche

Cur

rent

(A

)

0.01 0.1 110

100

1000

D027

TC = 25q CTC = 125q C

VSD - Source-to-Drain Voltage (V)

I SD -

Sou

rce-

to-D

rain

Cur

rent

(A

)

0 0.2 0.4 0.6 0.8 10.0001

0.001

0.01

0.1

1

10

100

D024

TC = 25qCTC = 125qC

VSD - Source-to-Drain Voltage (V)

I SD -

Sou

rce-

to-D

rain

Cur

rent

(A

)

0 0.2 0.4 0.6 0.8 10.0001

0.001

0.01

0.1

1

10

100

D025

TC = 25qCTC = 125qC

TC - Case Temperature (qC)

Nor

mal

ized

On-

Sta

te R

esis

tanc

e

-75 -50 -25 0 25 50 75 100 125 150 1750.6

0.8

1

1.2

1.4

1.6

D022

VGS = 4.5 VVGS = 8.0 V

TC - Case Temperature (qC)

Nor

mal

ized

On-

Sta

te R

esis

tanc

e

-75 -50 -25 0 25 50 75 100 125 150 1750.6

0.8

1

1.2

1.4

1.6

D023

VGS = 4.5 VVGS = 8.0 V

9



Typical Power Block MOSFET Characteristics (continued)TA = 25°C, unless stated otherwise.

ID = 20 A VGS = 8 V

Figure 21. Control MOSFET Normalized RDS(ON)

ID = 20 A VGS = 8 V

Figure 22. Sync MOSFET Normalized RDS(ON)

Figure 23. Control MOSFET Body Diode Figure 24. Sync MOSFET Body Diode

Figure 25. Control MOSFET Unclamped Inductive Switching Figure 26. Sync MOSFET Unclamped Inductive Switching

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+

-Input

Supply

Ci

PWM

Driver

Driver

Control

FET

Sync

FET

Co

Switch

Node

Power Block

Components

Power Stage

Components

Lo

IL

Load

10



6 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

6.1 Application InformationThe CSD87355Q5D NexFET power block is an optimized design for synchronous buck applications using 5-Vgate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest power loss andhighest system efficiency. As a result, a new rating method is needed which is tailored towards a more systemscentric environment. System level performance curves such as Power Loss, Safe Operating Area, andnormalized graphs allow engineers to predict the product performance in the actual application.

6.1.1 Equivalent System PerformanceMany of today's high performance computing systems require low power consumption in an effort to reducesystem operating temperatures and improve overall system efficiency. This has created a major emphasis onimproving the conversion efficiency of today’s Synchronous Buck Topology. In particular, there has been anemphasis in improving the performance of the critical Power Semiconductor in the Power Stage of thisapplication (see Figure 27). As such, optimization of the power semiconductors in these applications, needs to gobeyond simply reducing RDS(ON).

Figure 27.

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PWMDriver

Driver

Switch

NodeCo

Load

RPCB CESR

CINPUT

CESL

LDRAIN

LDRAIN

LSOURCE

LSOURCE

Control

FET

Sync

FET

Lo

IL

Input

Supply

CTOTAL

11



Application Information (continued)The CSD87355Q5D is part of TI’s Power Block product family which is a highly optimized product for use in asynchronous buck topology requiring high current, high efficiency, and high frequency. It incorporates TI’s latestgeneration silicon which has been optimized for switching performance, as well as minimizing losses associatedwith QGD, QGS, and QRR. Furthermore, TI’s patented packaging technology has minimized losses by nearlyeliminating parasitic elements between the Control FET and Sync FET connections (see Figure 28). A keychallenge solved by TI’s patented packaging technology is the system level impact of Common SourceInductance (CSI). CSI greatly impedes the switching characteristics of any MOSFET which in turn increasesswitching losses and reduces system efficiency. As a result, the effects of CSI need to be considered during theMOSFET selection process. In addition, standard MOSFET switching loss equations used to predict systemefficiency need to be modified in order to account for the effects of CSI. Further details behind the effects of CSIand modification of switching loss equations are outlined in TI’s Application Note SLPA009.

Figure 28.

The combination of TI’s latest generation silicon and optimized packaging technology has created abenchmarking solution that outperforms industry standard MOSFET chipsets of similar RDS(ON) and MOSFETchipsets with lower RDS(ON). Figure 29 and Figure 30 compare the efficiency and power loss performance of theCSD87355Q5D versus industry standard MOSFET chipsets commonly used in this type of application. Thiscomparison purely focuses on the efficiency and generated loss of the power semiconductors only. Theperformance of CSD87355Q5D clearly highlights the importance of considering the Effective AC On-Impedance(ZDS(ON)) during the MOSFET selection process of any new design. Simply normalizing to traditional MOSFETRDS(ON) specifications is not an indicator of the actual in-circuit performance when using TI’s Power Blocktechnology.

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Out

put C

urre

nt (

A)

0 5 10 15 20 25 30 35 40 45 500

1

2

3

4

5

6

7

8

9

D031

PowerBlock RDS(ON) = 3.9 m:/1.5 m:

Discrete HS/LS RDS(ON) = 3.9 m:/1.5 m:



Out

put C

urre

nt (

A)

0 5 10 15 20 25 30 35 40 45 5080

82

84

86

88

90

92

94

D030

PowerBlock HS/LS RDS(ON) = 3.9 m:/1.5 m:



12



Application Information (continued)

VIN = 12 V VOUT = 1.3 V LOUT = 0.3 µHƒSW = 500 kHz VDD= 5 V TA = 25°C

Figure 29. Efficiency

VIN = 12 V VOUT = 1.3 V LOUT = 0.3 µHƒSW = 500 kHz VDD = 5 V TA = 25°C

Figure 30. Power Loss

Table 1 compares the traditional DC measured RDS(ON) of CSD87355Q5D versus its ZDS(ON). This comparisontakes into account the improved efficiency associated with TI’s patented packaging technology. As such, whencomparing TI’s Power Block products to individually packaged discrete MOSFETs or dual MOSFETs in astandard package, the in-circuit switching performance of the solution must be considered. In this example,individually packaged discrete MOSFETs or dual MOSFETs in a standard package would need to have DCmeasured RDS(ON) values that are equivalent to CSD87355Q5D’s ZDS(ON) value in order to have the sameefficiency performance at full load. Mid to light-load efficiency will still be lower with individually packaged discreteMOSFETs or dual MOSFETs in a standard package.

Table 1. Comparison of RDS(ON) vs ZDS(ON)

PARAMETERHS LS

UNITTYP MAX TYP MAXEffective AC On-Impedance ZDS(ON) (VGS = 5 V) 3.9 - 0.9 - mΩ

DC Measured RDS(ON) (VGS = 4.5 V) 3.9 4.7 1.5 1.8 mΩ

6.1.2 Power Loss CurvesMOSFET centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices.In an effort to simplify the design process for engineers, Texas Instruments has provided measured power lossperformance curves. Figure 1 plots the power loss of the CSD87355Q5D as a function of load current. This curveis measured by configuring and running the CSD87355Q5D as it would be in the final application (seeFigure 31).The measured power loss is the CSD87355Q5D loss and consists of both input conversion loss andgate drive loss. Equation 1 is used to generate the power loss curve.

(VIN × IIN) + (VDD × IDD) – (VSW_AVG × IOUT) = Power Loss (1)

The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°Cunder isothermal test conditions.

6.1.3 Safe Operating Curves (SOA)The SOA curves in the CSD87355Q5D data sheet provides guidance on the temperature boundaries within anoperating system by incorporating the thermal resistance and system power loss. Figure 3 to Figure 4 outline thetemperature and airflow conditions required for a given load current. The area under the curve dictates the safeoperating area. All the curves are based on measurements made on a PCB design with dimensions of4” (W) × 3.5” (L) × 0.062” (T) and 6 copper layers of 1-oz. copper thickness.

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VDD

ENABLE

PWM

GND

BOOT

DRVH

LL

DRVL

VDD

PWM

VIN

VOUT

Driver ICCSD87355Q5D

A

V

Averaging

CircuitV

A

Output Current (IOUT)

A

Input Current (IIN)

VInput Voltage (VIN)

Averaged Switch

Node Voltage

(VSW_AVG)

VIN

VSW

PGND

TG

TGR

BG

Gate Drive

Voltage (VDD)

Control

FET

Sync

FET

Gate Drive

Current (IDD)

13



6.1.4 Normalized CurvesThe normalized curves in the CSD87355Q5D data sheet provides guidance on the Power Loss and SOAadjustments based on their application specific needs. These curves show how the power loss and SOAboundaries will adjust for a given set of system conditions. The primary Y-axis is the normalized change in powerloss and the secondary Y-axis is the change is system temperature required in order to comply with the SOAcurve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature issubtracted from the SOA curve.

6.2 Typical Application

Figure 31.

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14



Typical Application (continued)6.2.1 Design Example: Calculating Power Loss and SOAThe user can estimate product loss and SOA boundaries by arithmetic means (see Operating Conditions).Though the Power Loss and SOA curves in this data sheet are taken for a specific set of test conditions, thefollowing procedure will outline the steps the user should take to predict product performance for any set ofsystem conditions.

6.2.2 Operating Conditions• Output Current = 25 A• Input Voltage = 7 V• Output Voltage = 1.4 V• Switching Frequency = 800 kHz• Inductor = 0.2 µH

6.2.2.1 Calculating Power Loss• Power Loss at 25 A = 3.62 W (Figure 1)• Normalized Power Loss for input voltage ≈ 0.99 (Figure 6)• Normalized Power Loss for output voltage ≈ 1.02 (Figure 7)• Normalized Power Loss for switching frequency ≈ 1.06 (Figure 5)• Normalized Power Loss for output inductor ≈ 1.03 (Figure 8)• Final calculated Power Loss = 3.62 W × 0.99 × 1.02 × 1.06 × 1.03 ≈ 3.99 W

6.2.2.2 Calculating SOA Adjustments• SOA adjustment for input voltage ≈ –0.24ºC (Figure 6)• SOA adjustment for output voltage ≈ 0.63ºC (Figure 7)• SOA adjustment for switching frequency ≈ 2.12ºC (Figure 5)• SOA adjustment for output inductor ≈ 0.91ºC (Figure 8)• Final calculated SOA adjustment = –0.24 + 0.63 + 2.12 + 0.91 ≈ 3.42CIn the previous design example, the estimated power loss of the CSD87355Q5D would increase to 4 W. Inaddition, the maximum allowable board and/or ambient temperature would have to decrease by 3.4ºC. Figure 32graphically shows how the SOA curve would be adjusted accordingly.1. Start by drawing a horizontal line from the application current to the SOA curve.2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.

In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambienttemperature of 3.4ºC. In the event the adjustment value is a negative number, subtracting the negative numberwould yield an increase in allowable board/ambient temperature.

Figure 32. Power Block SOA

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15



(1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University ofMissouri – Rolla

7 Layout

7.1 Layout GuidelinesThere are two key system-level parameters that can be addressed with a proper PCB design: electrical andthermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. Thefollowing sections provide a brief description on how to address each parameter.

7.1.1 Electrical PerformanceThe Power Block has the ability to switch voltages at rates greater than 10 kV/µs. Take special care with thePCB layout design and placement of the input capacitors, Driver IC, and output inductor.• The placement of the input capacitors relative to the Power Block’s VIN and PGND pins should have the

highest priority during the component placement routine. It is critical to minimize these node lengths. As such,ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 33).The example in Figure 33 uses 6 × 10-µF ceramic capacitors (TDK Part # C3216X5R1C106KT or equivalent).Notice there are ceramic capacitors on both sides of the board with an appropriate amount of viasinterconnecting both layers. In terms of priority of placement next to the Power Block, C5, C7, C19, and C8should follow in order.

• The Driver IC should be placed relatively close to the Power Block Gate pins. TG and BG should connect tothe outputs of the Driver IC. The TGR pin serves as the return path of the high-side gate drive circuitry andshould be connected to the Phase pin of the IC (sometimes called LX, LL, SW, PH, etc.). The bootstrapcapacitor for the Driver IC will also connect to this pin.

• The switching node of the output inductor should be placed relatively close to the Power Block VSW pins.Minimizing the node length between these two components will reduce the PCB conduction losses andactually reduce the switching noise level.

• In the event the switch node waveform exhibits ringing that reaches undesirable levels, the use of a BoostResistor or RC snubber can be an effective way to reduce the peak ring level. The recommended BoostResistor value will range between 1 Ω to 4.7 Ω depending on the output characteristics of Driver IC used inconjunction with the Power Block. The RC snubber values can range from 0.5 Ω to 2.2 Ω for the R and 330pF to 2200 pF for the C. Refer to TI App Note SLUP100 for more details on how to properly tune the RCsnubber values. The RC snubber should be placed as close as possible to the Vsw node and PGND seeFigure 33. (1)

7.1.2 Thermal ConsiderationsThe Power Block has the ability to use the GND planes as the primary thermal path. As such, the use of thermalvias is an effective way to pull away heat from the device and into the system board. Concerns of solder voidsand manufacturability problems can be addressed by the use of three basic tactics to minimize the amount ofsolder attach that will wick down the via barrel:• Intentionally space out the vias from each other to avoid a cluster of holes in a given area.• Use the smallest drill size allowed in your design. The example in Figure 33 uses vias with a 10 mil drill hole

and a 16 mil capture pad.• Tent the opposite side of the via with solder-mask.

In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules andmanufacturing capabilities.

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http://www.ti.com/lit/pdf/SLUP100

VIN

V SW

PGND

BG

TGTGR

VSW V SW

Output Inductor

Input Capacitors

Power Block

Input Capacitors

Output Capacitors

Driver IC

Bottom LayerTop Layer

RC Snubber

Power BlockLocation on Top

Layer

16



7.2 Layout Example

Figure 33. Recommended PCB Layout (Top View)

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17



8 Device and Documentation Support

8.1 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.

8.2 TrademarksNexFET, E2E are trademarks of Texas Instruments.All other trademarks are the property of their respective owners.

8.3 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

8.4 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

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http://www.ti.com/corp/docs/legal/termsofuse.shtml

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http://e2e.ti.com

http://support.ti.com/

http://www.ti.com/lit/pdf/SLYZ022

M0187-01

E1

E

q

c

56

78 1

23

4

L

d1

f

K

b

d3

L

E1

e

a

E2

D2

Top View Bottom View

Front View

Side View

5

9

67

8

12

34

qc1

D1

d2

d

Pinout

Position Designation

Pin 1 VIN

Pin 2 VIN

Pin 3 TG

Pin 4 TGR

Pin 5 BG

Pin 6 VSW

Pin 7 VSW

Pin 8 VSW

Pin 9 PGND

Exposed Tie Bar May Vary

18



9 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.

9.1 Q5D Package Dimensions

DIMMILLIMETERS INCHES

MIN MAX MIN MAXa 1.40 1.5 0.055 0.059b 0.360 0.460 0.014 0.018c 0.150 0.250 0.006 0.010

c1 0.150 0.250 0.006 0.010d 1.630 1.730 0.064 0.068d1 0.280 0.380 0.011 0.015d2 0.200 0.300 0.008 0.012d3 0.291 0.391 0.012 0.015D1 4.900 5.100 0.193 0.201D2 4.269 4.369 0.168 0.172E 4.900 5.100 0.193 0.201E1 5.900 6.100 0.232 0.240E2 3.106 3.206 0.122 0.126e 1.27 TYP 0.050f 0.396 0.496 0.016 0.020L 0.510 0.710 0.020 0.028θ 0.00 — — —K 0.812 0.032

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M0208-01

0.341 (0.013)

0.410 (0.016)

14

58

0.250 (0.010)

0.300 (0.012)

0.300 (0.012)

Stencil Opening0.300 (0.012)

0.950 (0.037)

PCB Pattern

1.290 (0.051)

0.610 (0.024)

1.680(0.066)

1.710(0.067)

M0188-01

0.650 (0.026)0.650 (0.026)

0.620 (0.024)0.620

(0.024)

0.415 (0.016)

14

58

0.345 (0.014)

3.480 (0.137)

0.850 (0.033) 0.850 (0.033)

0.530 (0.021)

0.400 (0.016)

6.240 (0.246)

1.920(0.076)

4.460(0.176)

4.460(0.176)

1.270(0.050)

19



9.2 Land Pattern Recommendation

NOTE: Dimensions are in mm (inches).

9.3 Stencil Recommendation

NOTE: Dimensions are in mm (inches).

Text For Spacing For recommended circuit layout for PCB designs, see application note SLPA005 – ReducingRinging Through PCB Layout Techniques.

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http://www.ti.com/lit/pdf/SLPA005

PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

CSD87355Q5D ACTIVE LSON-CLIP DQY 8 2500 Pb-Free (RoHSExempt)

CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 87355D

CSD87355Q5DT ACTIVE LSON-CLIP DQY 8 250 Pb-Free (RoHSExempt)

CU NIPDAU Level-1-260C-UNLIM -55 to 150 87355D

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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PACKAGE OPTION ADDENDUM

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Addendum-Page 2

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

CSD87355Q5D LSON-CLIP

DQY 8 2500 330.0 12.4 5.3 6.3 1.8 8.0 12.0 Q2

CSD87355Q5DT LSON-CLIP

DQY 8 250 180.0 12.4 5.3 6.3 1.8 8.0 12.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 19-Sep-2017

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

CSD87355Q5D LSON-CLIP DQY 8 2500 367.0 367.0 35.0

CSD87355Q5DT LSON-CLIP DQY 8 250 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

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Pack Materials-Page 2

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