Copyright © 2007 Elsevier3- Ders-6: Ardışıl Mantık Devreleri Tasarımı

Copyright © 2007 Elsevier 3-<1>

Ders-6: Ardışıl Mantık Devreleri Tasarımı


Introduction

• Outputs of sequential logic depend on current and prior input values – it has memory.

• Some definitions:– State: all the information about a circuit necessary to

explain its future behavior

– Latches and flip-flops: state elements that store one bit of state

– Synchronous sequential circuits: combinational logic followed by a bank of flip-flops


State Elements

• The state of a circuit influences its future behavior

• State elements store state– Bistable circuit– SR Latch– D Latch– D Flip-flop


Bistable Circuit

• Fundamental building block of other state elements

• Two outputs: Q, Q

• No inputs

QQQ

Q

I1

I2

I2 I1


Bistable Circuit Analysis

Q

Q

I1

I2

0

1

1

0

• Consider the two possible cases:– Q = 0: then Q = 1 and Q = 0 (consistent)

– Q = 1: then Q = 0 and Q = 1 (consistent)

• Bistable circuit stores 1 bit of state in the state variable, Q (or Q )

• But there are no inputs to control the state

Q

Q

I1

I2

1

0

0

1


SR (Set/Reset) Latch

R

S

Q

Q

N1

N2

• SR Latch

• Consider the four possible cases:– S = 1, R = 0

– S = 0, R = 1

– S = 0, R = 0

– S = 1, R = 1


SR Latch Analysis

– S = 1, R = 0: then Q = 1 and Q = 0

– S = 0, R = 1: then Q = 0 and Q = 1

R

S

Q

Q

N1

N2

0

1

R

S

Q

Q

N1

N2

1

0


SR Latch Analysis

– S = 1, R = 0: then Q = 1 and Q = 0

– S = 0, R = 1: then Q = 0 and Q = 1

R

S

Q

Q

N1

N2

0

1

1

00

0

R

S

Q

Q

N1

N2

1

0

0

10

1


SR Latch Analysis

– S = 0, R = 0: then Q = Qprev

– S = 1, R = 1: then Q = 0 and Q = 0

R

S

Q

Q

N1

N2

1

1

R

S

Q

Q

N1

N2

0

0

R

S

Q

Q

N1

N2

0

0

0

Qprev = 0 Qprev = 1


SR Latch Analysis

– S = 0, R = 0: then Q = Qprev and Q = Qprev (memory!)

– S = 1, R = 1: then Q = 0 and Q = 0 (invalid state: Q ≠ NOT Q)

R

S

Q

Q

N1

N2

1

1

0

00

0

R

S

Q

Q

N1

N2

0

0

1

01

0

R

S

Q

Q

N1

N2

0

0

0

10

1

Qprev = 0 Qprev = 1


SR Latch Symbol

• SR stands for Set/Reset Latch– Stores one bit of state (Q)

• Control what value is being stored with S, R inputs– Set: Make the output 1 (S = 1, R = 0, Q = 1)

– Reset: Make the output 0 (S = 0, R = 1, Q = 0)

• Must do something to avoid

invalid state (when S = R = 1)S

R Q

Q

SR LatchSymbol


D Latch

D LatchSymbol

CLK

D Q

Q

• Two inputs: CLK, D– CLK: controls when the output changes

– D (the data input): controls what the output changes to

• Function– When CLK = 1, D passes through to Q (the latch is transparent)

– When CLK = 0, Q holds its previous value (the latch is opaque)

• Avoids invalid case when Q ≠ NOT Q


D Latch Internal Circuit

S

R Q

Q

Q

QD

CLKD

R

S

CLK

D Q

Q

S R Q QCLK D

0 X1 01 1

D


D Latch Internal Circuit

S

R Q

Q

Q

QD

CLKD

R

S

CLK

D Q

Q

S R Q

0 0 Qprev0 1 01 0 1

Q

10

CLK D

0 X1 01 1

D

X10

Qprev


D Flip-Flop

• Two inputs: CLK, D

• Function– The flip-flop “samples” D on the rising edge of CLK

• When CLK rises from 0 to 1, D passes through to Q

• Otherwise, Q holds its previous value

– Q changes only on the rising edge of CLK

• A flip-flop is called an edge-triggered device because it is activated on the clock edge D Flip-Flop

Symbols

D Q

Q


D Flip-Flop Internal Circuit

CLK

D Q

Q

CLK

D Q

Q

Q

Q

DN1

CLK

L1 L2

• Two back-to-back latches (L1 and L2) controlled by complementary clocks

• When CLK = 0– L1 is transparent

– L2 is opaque

– D passes through to N1

• When CLK = 1– L2 is transparent

– L1 is opaque

– N1 passes through to Q

• Thus, on the edge of the clock (when CLK rises from 0 1)– D passes through to Q


D Flip-Flop vs. D Latch

CLK

D Q

Q

D Q

Q

CLK

D

Q (latch)

Q (flop)


D Flip-Flop vs. D Latch

CLK

D Q

Q

D Q

Q

CLK

D

Q (latch)

Q (flop)


Registers

CLK

D Q

D Q

D Q

D Q

D0

D1

D2

D3

Q0

Q1

Q2

Q3

D3:0

4 4

CLK

Q3:0


Enabled Flip-Flops

InternalCircuit

D Q

CLKEN

DQ

0

1D Q

EN

Symbol

• Inputs: CLK, D, EN– The enable input (EN) controls when new data (D) is stored

• Function– EN = 1

• D passes through to Q on the clock edge

– EN = 0• the flip-flop retains its previous state


Resettable Flip-Flops

• Inputs: CLK, D, Reset

• Function:– Reset = 1

• Q is forced to 0

– Reset = 0• the flip-flop behaves like an ordinary D flip-flop

Symbols

D Q

Resetr


Resettable Flip-Flops

• Two types:– Synchronous: resets at the clock edge only

– Asynchronous: resets immediately when Reset = 1

• Asynchronously resettable flip-flop requires changing the internal circuitry of the flip-flop (see Exercise 3.10)

• Synchronously resettable flip-flop?

InternalCircuit

D Q

CLK

DQReset


Settable Flip-Flops

• Inputs: CLK, D, Set

• Funtion:– Set = 1

• Q is set to 1

– Set = 0• the flip-flop behaves like an ordinary D flip-flop

Symbols

D Q

Sets


Sequential Logic

• Sequential circuits: all circuits that aren’t combinational

• A problematic circuit:

• This circuit has no inputs and 1-3 outputs

X

Y

Z

time (ns)0 1 2 3 4 5 6 7 8

X Y Z


Sequential Logic

X Y Z

• Sequential circuits: all circuits that aren’t combinational

• A problematic circuit:

• This circuit has no inputs and 1-3 outputs

• It is an astable circuit that oscillates

• Its period depends on the delay of the inverters – which depends on the manufacturing process, temperature, etc

• The circuit has a cyclic path: output fed back to input

X

Y

Z

time (ns)0 1 2 3 4 5 6 7 8


Synchronous Sequential Logic Design

• Breaks cyclic paths by inserting registers

• These registers contain the state of the system

• The state changes at the clock edge, so we say the system is synchronized to the clock

• Rules of synchronous sequential circuit composition:– Every circuit element is either a register or a combinational circuit

– At least one circuit element is a register

– All registers receive the same clock signal

– Every cyclic path contains at least one register

• Two common synchronous sequential circuits– Finite State Machines (FSMs)

– Pipelines


Timing

• Flip-flop samples D at clock edge

• D must be stable when it is sampled

• Similar to a photograph, D must be stable around the clock edge

• If D is changing when it is sampled, metastability can occur


Input Timing Constraints

• Setup time: tsetup = time before the clock edge that data must be stable (i.e. not changing)

• Hold time: thold = time after the clock edge that data must be stable

• Aperture time: ta = time around clock edge that data must be stable (ta = tsetup + thold)

CLK

tsetup

D

thold

ta


Output Timing Constraints

• Propagation delay: tpcq = time after clock edge that the output Q is guaranteed to be stable (i.e., to stop changing)

• Contamination delay: tccq = time after clock edge that Q might be unstable (i.e., start changing)

CLK

tccq

tpcq

Q


Dynamic Discipline

• The input to a synchronous sequential circuit must be stable during the aperture (setup and hold) time around the clock edge.

• Specifically, the input must be stable– at least tsetup before the clock edge

– at least until thold after the clock edge


Dynamic Discipline

• The delay between registers has a minimum and maximum delay, dependent on the delays of the circuit elements

CL

CLKCLK

R1 R2

Q1 D2

(a)

CLK

Q1

D2

(b)

Tc


Setup Time Constraint

• The setup time constraint depends on the maximum delay from register R1 through the combinational logic.

• The input to register R2 must be stable at least tsetup before the clock edge.

CLK

Q1

D2

Tc

tpcq tpd tsetup

CL

CLKCLK

Q1 D2

R1 R2 Tc ≥





CLK

Q1

D2

Tc

tpcq tpd tsetup

CL

CLKCLK

Q1 D2

R1 R2 Tc ≥ tpcq + tpd + tsetup

tpd ≤





CLK

Q1

D2

Tc

tpcq tpd tsetup

CL

CLKCLK

Q1 D2

R1 R2 Tc ≥ tpcq + tpd + tsetup

tpd ≤ Tc – (tpcq + tsetup)


Hold Time Constraint

• The hold time constraint depends on the minimum delay from register R1 through the combinational logic.

• The input to register R2 must be stable for at least thold after the clock edge.

thold <CLK

Q1

D2

tccq tcd

thold

CL

CLKCLK

Q1 D2

R1 R2





thold < tccq + tcd

tcd >CLK

Q1

D2

tccq tcd

thold

CL

CLKCLK

Q1 D2

R1 R2





thold < tccq + tcd

tcd > thold - tccq CLK

Q1

D2

tccq tcd

thold

CL

CLKCLK

Q1 D2

R1 R2


Timing Analysis

CLK CLK

A

B

C

D

X'

Y'

X

Y

Timing Characteristics

tccq = 30 ps

tpcq = 50 ps

tsetup = 60 ps

thold = 70 ps

tpd = 35 ps

tcd = 25 ps

per

gate

tpd =

tcd =

Setup time constraint:

Tc ≥

fc = 1/Tc =

Hold time constraint:

tccq + tpd > thold ?


Timing Analysis

CLK CLK

A

B

C

D

X'

Y'

X

Y


tccq = 30 ps

tpcq = 50 ps

tsetup = 60 ps

thold = 70 ps

tpd = 35 ps

tcd = 25 ps

per

gate

tpd = 3 x 35 ps = 105 ps

tcd = 25 ps


Tc ≥ (50 + 105 + 60) ps = 215 ps

fc = 1/Tc = 4.65 GHz



(30 + 25) ps > 70 ps ? No!


Fixing Hold Time Violation


tccq = 30 ps

tpcq = 50 ps

tsetup = 60 ps

thold = 70 ps

tpd = 35 ps

tcd = 25 ps

per

gate

tpd =

tcd =


Tc ≥

fc =



CLK CLK

A

B

C

D

X'

Y'

X

Y

Add buffers to the short paths:


Fixing Hold Time Violation


tccq = 30 ps

tpcq = 50 ps

tsetup = 60 ps

thold = 70 ps

tpd = 35 ps

tcd = 25 ps

per

gate

tpd = 3 x 35 ps = 105 ps

tcd = 2 x 25 ps = 50 ps


Tc ≥ (50 + 105 + 60) ps = 215 ps

fc = 1/Tc = 4.65 GHz



(30 + 50) ps > 70 ps ? Yes!

CLK CLK

A

B

C

D

X'

Y'

X

Y

Add buffers to the short paths:


Violating the Dynamic Discipline

• Asynchronous (for example, user) inputs might violate the dynamic discipline

CLK

tsetup thold

taperture

D

Q

D

Q

D

Q ???

Cas

e I

Cas

e II

Cas

e II

I

D Q

CLK

butt

on


Metastability

• Any bistable device has two stable states and a metastable state between them

• A flip-flop has two stable states (1 and 0) and one metastable state

• If a flip-flop lands in the metastable state, it could stay there for an undetermined amount of time

metastable

stablestable


Flip-flop Internals

R

S

Q

Q

N1

N2

• Because the flip-flop has feedback, if Q is somewhere between 1 and 0, the cross-coupled gates will eventually drive the output to either rail (1 or 0, depending on which one it is closer to).

• A signal is considered metastable if it hasn’t resolved to 1 or 0

• If a flip-flop input changes at a random time, the probability that the output Q is metastable after waiting some time, t, is:

P(tres > t) = (T0/Tc ) e-t/τ

tres : time to resolve to 1 or 0

T0, τ : properties of the circuit


Metastability

• Intuitively:– T0/Tc describes the probability that the input changes at a bad

time, i.e., during the aperture time


– τ is a time constant indicating how fast the flip-flop moves away from the metastable state; it is related to the delay through the cross-coupled gates in the flip-flop


• In short, if a flip-flop samples a metastable input, if you wait long enough (t), the output will have resolved to 1 or 0 with high probability.


Synchronizers

D Q

CLK

SY

NC

• Asynchronous inputs (D) are inevitable (user interfaces, systems with different clocks interacting, etc.).

• The goal of a synchronizer is to make the probability of failure (the output Q still being metastable) low.

• A synchronizer cannot make the probability of failure 0.


Synchronizer Internals

D

Q

D2 Q

D2

Tc

tsetup tpcq

CLK CLK

CLK

tres

metastable

F1 F2

• A synchronizer can be built with two back-to-back flip-flops.

• Suppose the input D is transitioning when it is sampled by flip-flop 1, F1.

• The amount of time the internal signal D2 can resolve to a 1 or 0 is (Tc - tsetup).


Synchronizer Probability of Failure

D

Q

D2 Q

D2

Tc

tsetup tpcq

CLK CLK

CLK

tres

metastable

F1 F2

For each sample, the probability of failure of this synchronizer is:

P(failure) = (T0/Tc ) e-(Tc

- tsetup

)/τ


Synchronizer Mean Time Before Failure

• If the asynchronous input changes once per second, the probability of failure per second of the synchronizer is simply P(failure).

• In general, if the input changes N times per second, the probability of failure per second of the synchronizer is:

P(failure)/second = (NT0/Tc) e-(Tc

- tsetup

)/τ

• Thus, the synchronizer fails, on average, 1/[P(failure)/second]

• This is called the mean time between failures, MTBF:

MTBF = 1/[P(failure)/second] = (Tc/NT0) e(Tc

- tsetup

)/τ


Example Synchronizer

D D2 Q

CLK CLK

F1 F2

• Suppose: Tc = 1/500 MHz = 2 ns τ = 200 ps

T0 = 150 ps tsetup = 100 ps

N = 10 events per second• What is the probability of failure? MTBF?

P(failure) =

P(failure)/second =

MTBF =


Example Synchronizer

D D2 Q

CLK CLK

F1 F2

• Suppose: Tc = 1/500 MHz = 2 ns τ = 200 ps

T0 = 150 ps tsetup = 100 ps

N = 1 events per second• What is the probability of failure? MTBF?

P(failure) = (150 ps/2 ns) e-(1.9 ns)/200 ps

= 5.6 × 10-6

P(failure)/second = 10 × (5.6 × 10-6 ) = 5.6 × 10-5 / second MTBF = 1/[P(failure)/second] ≈ 5 hours


Registers

• Registers (or data registers) • A flip-flop

– Area: 10 to 20x of an SRAM cell

• In Xilinx FPGAs– Flip-flops– Distributed memory– Block memory


Data Registers

// an n-bit data registermodule register(clk, din, qout);parameter N = 4; // number of bits…input [N-1:0] din;output reg [N-1:0] qout; always @(posedge clk) qout <= din;


Data Registers

// an n-bit data register with asynchronous resetmodule register_reset (clk, reset_n, din, qout);parameter N = 4; // number of bits… input [N-1:0] din;output reg [N-1:0] qout;always @(posedge clk or negedge reset_n) if (!reset_n) qout <= {N{1'b0}}; else qout <= din;


Data Registers

// an N-bit data register with synchronous load and // asynchronous resetparameter N = 4; // number of bitsinput clk, load, reset_n; input [N-1:0] din;output reg [N-1:0] qout;

always @(posedge clk or negedge reset_n) if (!reset_n) qout <= {N{1'b0}}; else if (load) qout <= din;


A Register File – Read Part


A Register File – Write Part


A Register File

// an N-word register file with one-write and two-read portsparameter M = 4; // number of address bitsparameter N = 16; // number of words, N = 2**Mparameter W = 8; // number of bits in a wordinput clk, wr_enable;input [W-1:0] din;output [W-1:0] douta, doutb;input [M-1:0] rd_addra, rd_addrb, wr_addr;reg [W-1:0] reg_file [N-1:0];…assign douta = reg_file[rd_addra], doutb = reg_file[rd_addrb];always @(posedge clk) if (wr_enable) reg_file[wr_addr] <= din;

Try to synthesize it and see what happens!!


Basic Structure Design of 4x2 SRAM Chip


An Synchronous RAM

// a synchronous RAM module exampleparameter N = 16; // number of wordsparameter A = 4; // number of address bitsparameter W = 4; // number of wordsize in bitsinput [A-1:0] addr;input [W-1:0] din;input cs, wr, clk; // chip select, read-write control, and clock signalsoutput reg [W-1:0] dout;reg [W-1:0] ram [N-1:0]; // declare an N * W memory array

always @(posedge clk) if (cs) if (wr) ram[addr] <= din; else dout <= ram[addr];

Try to synthesize it and see what happens!!


Shift Registers

• Shift registers • Parallel/serial format conversion

– SISO (serial in serial out)

– SIPO (serial in parallel out)

– PISO (parallel in serial out)

– PIPO (parallel in parallel out)


Shift Registers


Shift Registers

// a shift register module examplemodule shift_register(clk, reset_n, din, qout);Parameter N = 4; // number of bits….output reg [N-1:0] qout;

always @(posedge clk or negedge reset_n) if (!reset_n) qout <= {N{1'b0}}; else qout <= {din, qout[N-1:1]};


A Shift Register with Parallel Load

// a shift register with parallel load module examplemodule shift_register_parallel_load (clk, load, reset_n, din, sin, qout);parameter N = 8; // number of bits….input [N-1:0] din; output reg [N-1:0] qout;

always @(posedge clk or negedge reset_n) if (!reset_n) qout <= {N{1'b0}}; else if (load) qout <= din; else qout <= {sin, qout[N-1:1]};


Universal Shift Registers

• A universal shift register can carry out – SISO

– SIPO

– PISO

– PIPO

• The register must have the following capabilities– Parallel load

– Serial in and serial out

– Shift left and shift right





// a universal shift register modulemodule universal_shift_register (clk, reset_n, s1, s0, …);parameter N = 4; // define the default size …always @(posedge clk or negedge reset_n) if (!reset_n) qout <= {N{1'b0}}; else case ({s1,s0}) 2'b00: ; // qout <= qout; // No change 2'b01: qout <= {lsi, qout[N-1:1]}; // Shift right 2'b10: qout <= {qout[N-2:0], rsi}; // Shift left 2'b11: qout <= din; // Parallel load endcase


Types of Counters

• Types of counters– Asynchronous

– Synchronous

• Asynchronous (ripple) counters– Binary counter (up/down counters)

• Synchronous counters– Binary counter (up/down counters)

– BCD counter (up/down counters)

– Gray counters (up/down counters)


Binary Ripple Counters



// a 3-bit ripple counter module examplemodule ripple_counter(clk, qout);…output reg [2:0] qout;wire c0, c1;// the body of the 3-bit ripple counterassign c0 = qout[0], c1 = qout[1];always @(negedge clk) qout[0] <= ~qout[0];always @(negedge c0) qout[1] <= ~qout[1];always @(negedge c1) qout[2] <= ~qout[2];

• Try to synthesize it and see what happens!!

• The output cannot be observed from simulators due to lacking initial values of qout.



// a 3-bit ripple counter with enable controlmodule ripple_counter_enable(clk, enable, reset_n, qout);…output reg [2:0] qout;wire c0, c1;assign c0 = qout[0], c1 = qout[1];always @(posedge clk or negedge reset_n) if (!reset_n) qout[0] <= 1'b0; else if (enable) qout[0] <= ~qout[0];always @(posedge c0 or negedge reset_n) if (!reset_n) qout[1] <= 1'b0; else if (enable) qout[1] <= ~qout[1];always @(posedge c1 or negedge reset_n) if (!reset_n) qout[2] <= 1'b0; else if (enable) qout[2] <= ~qout[2];


A Binary Ripple Counter

// an N-bit ripple counter using generate blocksparameter N = 4; // define the size of counter…output reg [N-1:0] qout;genvar i;generate for (i = 0; i < N; i = i + 1) begin: ripple_counter if (i == 0) // specify LSB always @(negedge clk or negedge reset_n) if (!reset_n) qout[0] <= 1'b0; else qout[0] <= ~qout[0]; else // specify the rest bits always @(negedge qout[i-1]or negedge reset_n) if (!reset_n) qout[i] <= 1'b0; else qout[i] <= ~qout[i];end endgenerate


A Binary Counter Example

module binary_counter(clk, enable, reset, qout, cout);parameter N = 4;…output reg [N-1:0] qout;output cout; // carry output

always @(posedge clk) if (reset) qout <= {N{1’b0}}; else if (enable) qout <= qout + 1;// generate carry outputassign #2 cout = &qout; // Why #2 is required ?


Binary Up/Down Counters --- version 1

module binary_up_down_counter_reset (clk, enable, reset, upcnt, qout, cout, bout);parameter N = 4;…output reg [N-1:0] qout;output cout, bout; // carry and borrow outputsalways @(posedge clk) if (reset) qout <= {N{1'b0}}; else if (enable) begin if (upcnt) qout <= qout + 1; else qout <= qout - 1; end assign #2 cout = &qout; // Why #2 is required ?assign #2 bout = |qout;



module up_dn_bin_counter (clk, reset, eup, edn, qout, cout, bout);Parameter N = 4;…output reg [N-1:0] qout;output cout, bout;

always @(posedge clk) if (reset) qout <= {N{1'b0}}; // synchronous reset else if (eup) qout <= qout + 1; else if (edn) qout <= qout - 1;assign #1 cout = (&qout)& eup; // generate carry outassign #1 bout = (~|qout)& edn; // generate borrow out



// the cascade of two up/down countersmodule up_dn_bin_counter_cascaded(clk, reset,eup, …);parameter N = 4;…output [2*N-1:0] qout;output cout, bout;wire cout1, bout1;

up_dn_bin_counter #(4) up_dn_cnt1 (clk, reset,eup, edn, …); up_dn_bin_counter #(4) up_dn_cnt2 (clk, reset, …);


A Modulo r Binary Counter

module modulo_r_counter(clk, enable, reset, qout, cout);parameter N = 4;parameter R= 10; // BCD counter…output reg [N-1:0] qout;…assign cout = (qout == R - 1);always @(posedge clk) if (reset) qout <= {N{1'b0}}; else begin if (enable) if (cout) qout <= 0; else qout <= qout + 1; end


Sequence Generators

• We only focus on the following three circuits– PR (pseudo random)-sequence generator

– Ring counter

– Johnson counter


Primitive Polynomials

nn

n

i

ii xaxaxaaxaxf

2

2100

)(


Maximal Length Sequence Generators


A PR-Sequence Generator Example

• A 4-bit example– primitive polynomial: 1 + x + x4



// an N-bit pr_sequence generator module --- in standard formmodule pr_sequence_generate (clk, qout);parameter N = 4; // define the default sizeparameter [N:0] tap = 5'b10011;…output reg [N-1:0] qout = 4’b0100; wire d; …assign d = ^(tap[N-1:0] & qout[N-1:0]);always @(posedge clk) qout <= {d, qout[N-1:1]};

Q: Write an N-bit pr_sequence generator in modular form.



// an N-bit pr_sequence generator module --- in standard formmodule pr_sequence_generate (clk, start, qout);parameter N = 4; // define the default size parameter [N:0] tap = 5'b10011;…output reg [N-1:0] qout;wire d;…assign d = ^(tap[N-1:0] & qout[N-1:0]);always @(posedge clk or posedge start) if (start) qout <= {1'b1, {N-1{1'b0}}}; else qout <= {d, qout[N-1:1]};


Ring Counters

// a ring counter with initial valuemodule ring_counter(clk, start, qout);parameter N = 4;…output reg [0:N-1] qout;…always @(posedge clk or posedge start) if (start) qout <= {1'b1,{N-1{1'b0}}}; else qout <= {qout[N-1], qout[0:N-2]};


Johnson Counters

// Johnson counter with initial valuemodule ring_counter(clk, start, qout);parameter N = 4; // define the default size…output reg [0:N-1] qout;…always @(posedge clk or posedge start) if (start) qout <= {N{1'b0}}; else qout <= {~qout[N-1], qout[0:N-2]};

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Copyright © 2007 Elsevier3- Ders-6: Ardışıl Mantık Devreleri Tasarımı