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Available online at www.sciencedirect.com

Electric Power Systems Research 78 (2008) 1597–1609

Control electronic platform based on floating-point DSPand FPGA for a NPC multilevel back-to-back converter

Francisco J. Rodrıguez 1, Santiago Cobreces 2, Emilio J. Bueno ∗,Alvaro Hernandez 3, Raul Mateos 4, Felipe Espinosa 5

Department of Electronics, University of Alcala, Alcala de Henares, Madrid, Spain

Received 3 May 2007; received in revised form 22 August 2007; accepted 1 February 2008Available online 14 March 2008

bstract

Modern energy concepts as Distributed Power Generation are changing the appearance of electric distribution and transmission and challengingower electronics researchers, which try to develop new solutions of electronic controllers. The aim is to enable the implementation of new and moreomplex control algorithms to verify the last standards related to the grid energy quality for new power converters, and, also, for equipments whichowadays are operating. This paper presents the design, implementation and test of a novel real-time controller for a Neutral Point Clamped (NPC)

three-level) multilevel converter based on a floating-point Digital Signal Processor (DSP) and on a Field-Programmable Gate Array (FPGA), byperating in a cooperative way. Although the proposed system can be readily applied to any power electronic application, in this work, it is focusedn the next system: a 150 kVA back-to-back three-level NPC Voltage Source Converter (VSC) for wind power applications.

2008 Elsevier B.V. All rights reserved.

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eywords: Electronic control system; Floating-point DSP- and FPGA-based co

. Introduction

Recent advances in power semiconductor devices, controlheory and microprocessor technology have allowed a remark-ble increase in the presence of power electronic convertersn both distribution and transmission lines. Some of their

pplications are high-voltage DC transmission, static VAR com-ensators, interconnection of Renewable Energy Sources andnergy Storage Systems to the utility, etc. From the utility

∗ Corresponding author. Tel.: +34 918856584; fax: +34 918856591.E-mail addresses: fjrs@depeca.uah.es (F.J. Rodrıguez),

obreces@depeca.uah.es (S. Cobreces), emilio@depeca.uah.es (E.J. Bueno),lvaro@depeca.uah.es (A. Hernandez), raul@depeca.uah.es (R. Mateos),spinosa@depeca.uah.es (F. Espinosa).

URLs: http://www.depeca.uah.es (F.J. Rodrıguez),ttp://www.depeca.uah.es (S. Cobreces), http://www.depeca.uah.esE.J. Bueno), http://www.depeca.uah.es (A. Hernandez),ttp://www.depeca.uah.es (R. Mateos), http://www.depeca.uah.es (F. Espinosa).1 Tel.: +34 918856561; fax: +34 918856591.2 Tel.: +34 918856566; fax: +34 918856591.3 Tel.: +34 918856584; fax: +34 918856591.4 Tel.: +34 918856563; fax: +34 918856591.5 Tel.: +34 918856545; fax: +34 918856591.

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378-7796/$ – see front matter © 2008 Elsevier B.V. All rights reserved.oi:10.1016/j.epsr.2008.02.003

system; NPC converters; Wind energy

nd the end-user point of view, these systems offer technical,nvironmental and economical benefits, by allowing the inte-ration of Distributed Power Generation System (DPGS) inhe utility grid. The power electronic interface usually includes

current-controlled voltage source converter (VSC) based onGBTs, which are controlled by Pulse Width Modulation (PWM)echniques with high switching frequencies to achieve high con-rollability and power quality.

Power quality, grid interconnection and disturbance sensi-ivity and rejection are considered by new incoming standards,hose aim is to make possible an efficient settling of new dis-

ributed energy sources. The electronic control platform plays aecisive role, not only in the fulfilment of these specifications,ut also in the adaptation, without requiring significant effort inlectronic development (in both control and power electronics).lso, the implementation of complex control algorithms, signalrocessing such as filtering and data conversion, communica-ion with the external system and the user interface, diagnosisnd protection functions, require a large amount of concen-

rated and distributed computational resources. Among thearious available digital processors with high efficient design,ow-cost, stand-alone and real-time controllers, two computingevices are popular: Digital Signal Processors (DSPs) and Field-

1 Systems Research 78 (2008) 1597–1609

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Table 1Specifications of the utility grid and the converter

GridUbase (base voltage) 400 Vωbase (base frequency) 2π50 rad/s

ConverterSn (nominal power) 150 kVA

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598 F.J. Rodrıguez et al. / Electric Power

rogrammable Gate Arrays (FPGAs). The main advantage ofSPs is their software flexibility, whereas FPGAs provide highererformances in repetitive and massive computations [1].

Real-time controllers based on integrated DSP–FPGA solu-ions are suitable options because they combine features fromoth devices. Thanks to its high computing capacity, the lowystem costs and its inherent flexibility, this power electronicontrolling solution has been previously proposed for the con-rol of a doubly fed induction generator [2], multi-cell converter3], or other systems [4–7]. The common result in all appli-ation is an improvement in the converter performance and aemarkable reduction in software development time.

Regarding DSPs, there still exist some differences, whichill be analysed in this paper, between fixed-point and floating-oint DSPs. In this work, a floating-point DSP is chosen, butts main drawback is the reduced amount of integrated periph-ry, therefore a FPGA is the device selected to implement theseeriphery modules. On the other hand, an interesting questionn any DSP–FPGA real-time control system is the task distri-ution. The proposal described here optimizes the developmentime and the computing power.

Although DSP and FPGA solutions have been already appliedefore, this paper is focused on adapting and improving thisype of solution to a 150 kVA back-to-back NPC VSC used onariable-speed wind turbines. This topology is considered as auitable option to verify the standards related to the grid energyuality and new utility grid codes, in countries with a high wind-nergy implantation [8].

The paper is organized as follows. Section 2 gives an

verview of the control algorithms executed in the controllatform. Section 3 explains why a floating-point DSP and aPGA have been selected as processing elements. The pro-osed controller structure and the hardware requirements for

ipti

Fig. 1. Control block diagram of the wind generation system based on a

TSW (switching period) 400 �sTS (sampling period) 200 �s

mplementing the control algorithms are also shown. Section 4escribes the design and implementation details of the real-timeontroller. The overall experimental set-up, results and discus-ions are given in Section 5, followed by conclusions in Section.

. VSC and control algorithms overview

Fig. 1 shows the control system of the 150 kVA back-to-backPC VSC used for variable-speed wind turbines [9]; whereas

he characteristic parameters for the converter and for the utilityrid are displayed in Table 1 [10].

The turbine is coupled to the induction generator throughspeed-up gear ratio. The variable-frequency variable-voltageower generated by the machine is rectified to DC by annsulated-gate-bipolar-transistor (IGBT) PWM bridge rectifierVSC2) that also supplies the lagging excitation current to theachine. The dc-bus power is inverted through an IGBT PWM

nverter (VSC1) and fed to the utility grid at a programmableower factor. The generator speed is controlled by indirect vec-or control with torque control and synchronous current controln the inner loops. The machine flux is controlled in an open

NPC multilevel back-to-back converter and full-power topology.

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F.J. Rodrıguez et al. / Electric Power

oop by the control of the current component id but, in normalonditions, the rotor flux is set to the rated value for fast transientesponse.

Line-side converter (VSC1) is also controlled, using directector and synchronous current control in the inner loops. Therid power is controlled from the dc-bus voltage control. Theine-side converter guarantees a low ac current harmonic dis-ortion and a controllable phase between the converter outputoltage and the grid voltage signals. The converter control struc-ure can be divided into two hierarchical levels:

The inner control structure controls the active and reactivepowers in a decoupled way. It is composed of a dc-bus voltageloop and output ac current control loops.The outer control structure, however, is strongly application-dependent: it depends on the actual generation system, andit should be able to operate either in stand-alone mode orfollowing the Transmission System Operator’s guidelines.

In the case of a Wind Energy System, the outer loop shoulduarantee that the injected energy keeps the grid voltage char-cteristics inside the allowed boundaries. It is divided into twoegulations:

The first regulation in these systems considers frequency-power. The grid frequency is an estimator of thegeneration-consumption power balance. When an increase inthe grid frequency happens, the generator should decreasethe injected power to balance the power contribution of thedifferent generators.Simultaneously, a second regulation law controls the gridvoltage by the injection of reactive power to the utility grid.When a low-grid voltage situation is detected, the generatorprovides reactive power (with a capacitive behaviour); on thecontrary, in high-grid voltage situations, the generator con-sumes grid reactive power, at which time it behaves as aninductor.

. Proposed control electronic system and controllgorithm requirements

Next, it is explained why a floating-point DSP and FPGAave been selected as processing elements. Also, the proposedontroller structure is described, as well as the synchronizationequirements in the control algorithms. Finally, the output andnput signals involved in the process are detailed.

.1. Selection of the digital processors for the controllectronic system

During the last decade, the trend in the control of powerlectronic converters is to use DSPs instead of general-purposerocessors. Control algorithms require a large number of

ultiplication–accumulation operations, and the architecture of

he DSPs is optimized to achieve this type of computing.Whenever a DSP has been chosen as processor, the next step

s to decide between fixed- or floating-point. In spite of the dif-

ait

ms Research 78 (2008) 1597–1609 1599

erences between the two types are becoming less significant,here still exist in the next items: cost, numeric representation ofata, data accuracy, ease of programming, and integrated periph-ry. More mathematical flexibility of the floating-point format,he accuracy and the reduced development time can make itn attractive solution for applications with data sets requiringeal arithmetic. For these reasons, in this work a floating-pointSP is selected, but its main drawback is the reduced amount of

ntegrated periphery. These characteristics determine the hard-are and software design of the control platform proposed in thisork. In this line, to implement the periphery modules necessary

n this application a FPGA can be the ideal device.Thanks to the reasons mentioned in the previous paragraph,

floating-point DSP and an FPGA are the chosen proces-ors for the proposed control electronic system, concretely:I TMS320C6713 DSP [11] and Xilinx XC2S200E FPGA

12]. Therefore, the FPGA is used for the implementation ofhe peripherals (i.e. PWM generators), the control of externalevices (i.e. ADCs), and also to execute some particular controllgorithms.

.2. Control structure

Fig. 2 proposes a control structure suitable for the applicationescribed in Section 2. It is divided into two parts: (1) the proces-or module, whose main device is the DSP; and (2) the peripheralnterface module divided into three different subsystems: (a) thePGA–DSP interface; (b) the co-processing module with thePGA; and (c) the power system interface which consists of theata acquisition system, the IGBT excitation drivers, the faultignal detection and the relay drivers.

The computational module shown in Fig. 2 is formed by theMS320C6713DSK board [13] and the DIGILAB 2E board

14]. The first one is a developing system designed for theI TMS320C6713 DSP, whereas the second one is based onXilinx SPARTAN2E FPGA.

.3. Relation and synchronization between theommutation and sampling periods

There is an inverse relation between the commutation fre-uency (PWM frequency) and the ripple induced for this signalo the load, i.e. the larger the commutation frequency is, themaller the ripple is in the load, resulting in a decrease in therid filter components. Nevertheless, the increase of the com-utation frequency implies more losses at the IGBTs of the

onverters. In this way, the commutation frequency becomes aommitment between the losses of the system and the ripplen the load. After carrying out an analysis of the commuta-ion losses at the IGBTs, and according to the correspondingemperature simulations [10], both periods have been fixed atPWM = TSW = 400 �s. Anyway, the system structure presentedere is suitable for a wide range of switching frequencies.

On the other hand, the relation between the sampling periodnd the commutation period should allow a sampling of thenstantaneous current at the maximum and minimum values ofhe carriers in the sinusoidal modulation, and the zero sequences

1600 F.J. Rodrıguez et al. / Electric Power Systems Research 78 (2008) 1597–1609

ropose

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Fig. 2. Block diagram of the p

n the vector modulation. This method reduces the high orderarmonics in the grid current [15]. So, the configured sam-ling period is TS = 200 �s, and the sampling instants shoulde correctly synchronized.

.4. Driving signals for the IGBTs

Fig. 3 shows a branch from one of the VSCs in the converter,here x can be the phase a, b or c. The excitation board for

very pair of IGBTs (each package is formed by one IGBT),

lso shown in Fig. 3, has two inputs: the signals UP/DOWN andNABLE. The digital system requires 24 transmitters of opticalber in order to excite the 12 pairs of IGBTs of the system inig. 1. On the other hand, every driver returns back a status signal

MaTc

Fig. 3. VSC branch of a three levels NPC

d control electronic structure.

y optical fiber, so it is necessary to include 12 optical receiversn the power system interface.

.5. Signal acquisition from the power electronic system:ensors

Table 2 describes the converter signals, necessary forhe control electronic system. The acquisition system shouldimultaneously acquire at least these 17 analog signals, with

sampling frequency of 5 kHz. The selected ADC is a

AX1309 by Maxim [16]; it has four analog channels and12-bit resolution, so, at least, five ADCs are required.

his structure allows a simultaneous acquisition from 20hannels.

with the driver for a pair of IGBTs.

F.J. Rodrıguez et al. / Electric Power Systems Research 78 (2008) 1597–1609 1601

Table 2System sensors

Grid filter DC-bus Connection VSC2-ac generator

Converter currents: i1a, i1b and i1c CDC2 voltage: uDC2 Generator currents: ima, imb and imc

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apacitor voltages: uCa, uCb and uCc CDC1 vrid currents: i2a, i2a and i2a

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. About designing the computational and peripheralnterface modules

The main objective of this section is to present a generalescription of both computational and peripheral interface mod-le. Firstly, the task distribution between the two processorss analysed. Next, the DSP–FPGA interface is described, andnally, the most interesting aspects about the DSP and FPGArogramming are shown.

.1. Task distribution between the two processing devices

The most important tasks of the controller are listed in the leftolumn of Table 3. These tasks, involved in control loops, presentcritical execution time since their execution has to be finishedefore the next sampling period. The parameter description iss follows:

TS is the sampling period required by each task. The value ofthis period was specified in Section 3.1.Trun means the maximum execution time. When several tasksare included in the same time, it means that the sum of theirexecution times should not be longer than the maximum timeindicated.Operation type describes the nature of the operation (trigono-metric, matrix, arithmetic, etc.).Algorithm type details if it is a control algorithm, suitable for

a sequential execution, or a parallel algorithm.Selected device describes which processor (DSP and FPGA)is selected, according to the characteristics of the function tobe executed.

able 3nalysis of the task executed by the “Computational Module”

asks TS Tr

or the line-side converterCurrent vector controller 200 �s <2Identification of different disturbances 200 �sDSC (Delay Signal Cancellation) [17] 200 �sSPLL [17] 200 �sdc-bus voltage controller 200 �s

or the generator-side converterVector controller. 200 �s <2Turbine controller (tracking of the maximum power point) 200 �s

or the two convertersPWM generation (carrier frequency 2.5 KHz and 24 signals) 200 �sEncoder reading 200 �sAcquisition data 200 �s

e: uDC1

As shown in Fig. 2, the computational module proposed heres composed by a floating-point DSP and an FPGA. The maindvantage of using DSPs lies in their software implementationhat makes the design flexible, scalable, and easy to use andpdate. On the other hand, due to its inherent parallelism, anPGA provides higher performance in some parallel and inten-ive computing tasks and in specific logic implementation (glueogic), compared to a microprocessor or a DSP. The use of thesewo processors allows the parallel implementation of algorithms,ncreasing the processing rate. Nevertheless, it is necessary tochieve an optimal task distribution to improve the control elec-ronic system performance.

For this distribution, some considerations based on the taskype and on the internal structure of the devices have been takennto account:

. Some tasks are constrained or linked by data dependences,so their location should be in the same device to avoid highdata exchange rates between devices.

. Since the selected DSP has scarce integrated periphery, sometasks, like the encoder reading or the PWM generation,should be implemented in the FPGA.

. Tasks with high computational load may not be implementedby the DSP in real-time, so they are processed in the FPGA.For example, a complex Kalman Filter, an accurate FFT,etc.

. A very repetitive task, that rarely changes, may be pro-

grammed in the FPGA, independently of their computationalcomplexity. For example, the Delay Signal Cancellation algo-rithm (DSC [17]), a non-detailed FFT, a FIR filters used forharmonic selective filtering, etc.

un Operation type Algorithm type Selected device

00 �s Trigonometric and matrix Control DSPFPGAFPGA

Arithmetic DSPArithmetic DSP

00 �s Trigonometric and matrix Control DSPArithmetic DSP

Arithmetic Parallel FPGAArithmetic Parallel FPGA– Parallel FPGA

1 Systems Research 78 (2008) 1597–1609

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. Tasks with low or low-medium computational load, whichmay be often modified by the programmer, are executed inthe DSP: mainly, control algorithms.

. Non-critical tasks, like representation, are not constrained, sothey can be placed at the DSP due to its programming ease.

Finally, as it is indicated in Table 3, the DSP executes allhe controllers; it controls the current in converters, the dc-busoltage, the turbine and the SPLL (method of synchronizationith the grid) [17]. The FPGA tasks are related to PWM gen-

ration, encoder reading, acquisition data and more informationanagement whose implementation is explained in Section 4.4.

.2. DSP–FPGA interface

The communication between the DSP and the FPGAecomes a critical point of the system, since the parallel effi-iency depends on it. It is based on the 32-bit External Memorynterface bus (EMIF) from the TI DSP [18]. This externallyccessible bus is mapped into the DSP address space, where theifferent control register of the Computational Module is placed.

.3. DSP programming

The development tool used for the DSP is Code Composertudio v.2.0, using C as programming language and the real-

ime operating system DSPBIOS by TI [19]. Fig. 4 shows theontrol algorithm flowchart of the converter connected to therid (VSC1). The different blocks executed by the DSP areractically the same blocks shown inside the module Controlf VSC connected to the grid in Fig. 1. The function names exe-uted by each block are shown below. Some differences betweenigs. 1 and 4 are

1) Output of controller. The function of this block is to obtainthe output of the control algorithm executed by the DSP,which is the reference of the PWM generators in the FPGA.

2) PI SPLL and DSC are elements of the SPLL block inFig. 1. SPLL is the method used to synchronize the con-trol algorithm with the utility grid, explained in detail in[17]. PI SPLL executes the PI controller of SPLL, whereasDSC is the on-line sequence separation algorithm based ona matrix calculation.

As is shown in Fig. 4, after initializing the DSP, it waits forxternal interruptions no. 4 and 5 generated by the FPGA. Thexternal interruption 4 is activated for a fault in the system.nder these circumstances, the DSP stops the execution of therogram. On the other hand, the external interruption 5 is peri-dically activated every 200 �s (generated by the FPGA everyampling time) and it is associated with the control algorithmxecution.

.4. FPGA programming

Fig. 5 shows the block diagram of the software implementedn the Xilinx Spartan2E FPGA. The algorithms have been spec- r

Fig. 4. VSC1 control algorithm flowchart.

fied in VHDL, and the functions of the implemented blocksre

Configuration and control registers. System registers are man-aged to communicate all the tasks by a right addressing anda finite state machine.DSP interface. The EMIF interface is implemented to com-municate with the DSP.DSP–FPGA synchronization. The PWM carriers and a syn-chronizing signal for events between the DSP and the FPGA,called SYNC, are generated.PWM generator. It provides the excitation signals for theIGBTs in Fig. 1. To apply these signals to the IGBT drivers,it is necessary to achieve a conversion from these electricalsignals to optical ones.ADC’s control. It generates the control signals for the ADCs.Encoders. It processes the tachometer signals from the gen-erator connected to the VSC 2 and the wind turbine.FAULT control. It generates an interruption in the DSP when-ever a FAULT is activated in the drivers of IGBTs.High performance computational unit. It provides a frame-

work for execution of heavy computation tasks.

The FPGA manages several tasks related to control, configu-ation, communication, wind turbine speed measurement and

F.J. Rodrıguez et al. / Electric Power Systems Research 78 (2008) 1597–1609 1603

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SP synchronization. Next, the implementation of the mainlocks designed is described.

.4.1. Synchronization of events DSP–FPGAThis block is excited by the FPGA clock, CLK, and it gener-

tes the output signals SYNC and COUNTER as shown in Fig. 6.he triangular signal COUNTER is implemented by means of n-its up/down counter. The number of bits depends on the FPGAlock and the COUNTER signal frequencies.

The timing of the different events in the DSP and the FPGA

nd how they are synchronized is shown in Fig. 7. Initially, thewo processors are started in an independent way. The FPGAegins to generate the triangular signal COUNTER representedn Fig. 6 with a period of 400 �s, whereas the DSP, after the

tade

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nitialization process, remains in idle state. Besides, this trian-ular signal is used as PWM carriers, therefore the commutationeriod TSW is 400 �s. At every maximum and minimum ofhese signals, SYNC is triggered, and consequently the DSPXT INT5 pin (external interruption no. 5) to start the execu-

ion of the control algorithms, being the sampling period TSqual to 200 �s. After generating SYNC in the instant k, thePGA acquires samples, while the DSP remains idling until thecquired data are available in the FPGA. The FPGA gives theseata to the DSP, and the DSP transmits the new references for

he FPGA PWM generator. These references are obtained by thelgorithms computed at the instant k − 1. With the acquisitionata in instant k and the references applied at k, the new refer-nces to be applied at the instant k + 1 are computed. All data

rriers and the signal SYNC.

1604 F.J. Rodrıguez et al. / Electric Power Systems Research 78 (2008) 1597–1609

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equired by the Control Electronic System are simultaneouslycquired, and the durations of the different events are given inection 5.

.4.2. Generation of PWM signalsTaking into account the signal COUNTER, the PWM signals

f IGBTs are generated according to the modulation techniquesenominated THSPWM and SVPWM, which are explained inetail in Ref. [20].

.4.3. Acquisition of analog signalsThe acquisition system specifications, already analysed in

ection 3.3, are (1) 12-bit precision; (2) sampling frequency fSf 5 kHz; (3) synchronization with the signal SYNC; and (4)imultaneous sampling of all channels. To meet these specifica-ions, as also was indicated in Section 3.3, 5 MAX1309 ADCsave been selected.

The access to the acquisition module is controlled by a finitetate machine, with three states: idle, the system is waiting forhe synchronism signal; waiting, there is a state change when theour channels of every ADC finish the conversion setting theirOLC (End of Last Conversion) pins low; and reading, the fourhannel of the five ADCs are read in this state. The capturedata, which are used to implement the control algorithms, are

tored in a dual port memory implemented in the FPGA, which isirectly accessed by the DSP. The use of this dual-port memoryllows a dedicated port for the connection with the ADCs andhe other one for the connection with the DSP.

ctD

e DSP and the FPGA.

It is interesting to highlight that pass approximately 3.42 �s,rom the arrival of the synchronism pulse SYNC until the systemas captured and stored all data in the memory. A variable partf this time depends on the ADC’s conversion time, whereashe remaining time elapsed is due to the reading process thatystematically concludes in 1.6 �s.

.4.4. High performance computational unitThis unit provides a powerful framework that allows the

mplementation of complex algorithms, such as Kalman Filter,n accurate FFT, a FIR filters used for harmonic selective filter-ng, etc. These algorithms can be specified in VHDL or any otherardware description language. From the DSP point of view, thenterface of the computational unit consists of a configurableumber of input and output registers for every algorithm imple-ented in this unit. When a control algorithm needs to make a

omplex operation, it may leave the input operators in the cor-esponding registers, obtaining the results in the next samplingeriod. Algorithms requiring more than a sampling period ofrocessing are suitable, by specifying the number of samplingntervals needed in the unit configuration register.

. Experimental results

Fig. 8 shows the overall Control Electronic System, whichan be divided into two parts, as has been already mentioned inhe previous sections: (1) the Computational Module formed bySP and FPGA and (2) the peripheral interface with the ADCs,

F.J. Rodrıguez et al. / Electric Power Systems Research 78 (2008) 1597–1609 1605

the co

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elays, optical transmitters and receivers, etc. This digital sys-em has been developed to manage the 150 kVA back-to-backPC VSC prototype presented in Fig. 9, where its most impor-

ant elements are remarked. Every VSC of the converter is builtith 6 FD300R12KE3 and 6 DF300R12KE3 (12 modules) overne heatsink. Also, two SKF 16 A-230-11 fan by SEMIKRONith a maximum air flow radial of 615 m3/h has been added

o the heatsink, so the final thermal resistance is reducedonsiderably. To connect the power converter to the grid an LCL-lter is chosen with the next values: L1 = 0.5 mH/195 Arms,2 = 0.25 mH/195 Arms and C0 = 100 �F/480 V [10].

In order to check the correct functionality of the differ-nt parts of the converter, some results are analysed here: (1)he computational power of the proposed control electronic

latform; (2) the method used to synchronize the converterith the utility grid, as an example of the control algo-

ithms; (3) some waveforms obtained from real-time tests in theonverter.

siic

able 4umber of CPU cycles for the DSP execution

reas Code Size (bytes) Count Max CPU cyc

ain() 184 1 0nit system() 328 1 0

int(5) 472 55 7310cquisition data() 1324 55 2230eference PWM() 780 55 754I SPLL() 720 55 778SC() 1440 55 983

urrentcontroller() 3648 55 2005cbuscontroller() 548 55 256int(4) 220 1 0

ystem protection() 144 1 7005

ntrol electronic system.

.1. Tests about the computational power of the proposedontrol electronic platform

In this section, the execution time of the VSC1 controllers obtained, whose flowchart and timing diagram were shownn Figs. 4 and 7, respectively. The DSP operates at a clockrequency of 225 MHz (the DSP clock cycle is 4.44 ns). Onhe other hand, the FPGA operates at a clock frequency of0 MHz. Table 4 shows the code size of every function, theumber of calls for every function (Count), and the maxi-um number of CPU cycles needed by the DSP to execute

very block (Max CPU cycles). The function names shownn Table 4 are those also shown in Fig. 4 below every block.urthermore, in the column entitled Fig. 7 blocks, the corre-

pondence between the functions and the blocks representedn the timing diagram in Fig. 7 is indicated. In the case ofnterruption no. 5 (when the overall control algorithm is exe-uted), the maximum number of CPU cycle is 7310. If the

les Fig. 7 block

Data adquisition + adquired data transmission from FPGA to DSPReferences calculated at k − 1 are transmitted from DSP to FPGAControlalgo-rithms

1606 F.J. Rodrıguez et al. / Electric Power Systems Research 78 (2008) 1597–1609

Fig. 9. Power electronic system assembly of the converter.

Fig. 10. DSP execution graph.

F.J. Rodrıguez et al. / Electric Power Systems Research 78 (2008) 1597–1609 1607

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Fc

ig. 11. Results of the method used to synchronize the converter with the utilitnd negative sequences.

SP clock cycle is 4.44 ns, then the maximum execution times 31,456 �s, which is much shorter than the sampling time200 �s). It implies that the developed control electronic plat-orm can execute the control algorithms of the two VSCs,

ap

o

ig. 12. Experimental converter waveforms. (a) Phase voltage divided by 10 and phasondition. (c) Phase voltage divided by 10 and phase current for Q* = 8 kVAr. (d) Pha

: (a) grid phase voltages. (b) SPLL output: d and q components of the positive

nd, also, more complex control algorithms without schedulingroblems.

Another method to analyse the DSP performance consistsf displaying the task execution diagram. In Fig. 10 it is pos-

e current for Q* = 0 VAr. (b) Phase current harmonic spectrum for the previousse voltage divided by 10 and phase current for Q* = −8 kVAr.

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ible to observe the control algorithm execution time respecto the sampling time (TS). It is executed inside the hardwarenterruption no. 5, and is divided in two elements: KNL swi andther Threads. The CPU load for control algorithms is approx-

mately 15.773%; during the rest of every sampling time, theSP executes the following tasks: communication task withost; scheduling tasks related to the real-time operating systemDPS/BIOS [19]); and, finally, the idle task.

About the FPGA, the number of BRAMs required is 1 out of4 (7%), the number of SLICEs consumed is 748 out of 235231%) and the maximum delay is 18.7 ns.

.2. Experimental results of the synchronization methodith the utility grid

Fig. 11 describes the behaviour of the system used to syn-hronize VSC1 with the utility grid. The method is the SPLLPLL software) explained in Ref. [17], and the output is obtainedy executing the functions PI SPLL and DSC shown in Table 4.he maximum execution time of these algorithms is 7.82 �s,nder the same circumstances shown in the previous section.ig. 11a shows the grid phase voltages (egan and egbn) directlyeasured. The results from algorithms PI SPLL and DSC can

e observed in Fig. 11b, where the dq-positive (edqpos) and dq-egative (edqneg) voltage components are presented. It can beemarked that only the q-positive component is different from, since the grid voltages are balanced; furthermore, the SPLLs synchronized with the grid virtual flux.

.3. Experimental waveforms

To carry out the experimental tests, the converter has beenonnected to a real grid with nominal voltage of 400 V in aesearching laboratory; and, furthermore, with the next condi-ions: (1) non-null grid impedance; (2) mean THD in the phaseeutral voltages of 19.5%; and, (3) mean percent imbalance of.5% (according to IEEE Std. 1159–1995). Fig. 12 shows therid currents and voltages when the VSC2 is approximately con-uming 12 kW and the reactive power reference of the VSC1s Q* = 0 VAr (see Fig. 12a), Q* = 0 kVAr (see Fig. 12c), and* = −8 kVAr (see Fig. 12d). In Fig. 12 the angle between theoltage and the current is 180◦ because the converter is consum-ng active power from the grid utility. In the contrary case, ifhe converter is delivering active power to the grid utility, theurrent and the voltage will be in phase. Fig. 12b shows the gridurrent harmonics for the test shown in Fig. 12a. The funda-ental harmonic peak value is 12 kW/400

√2/3, and the value

f the other harmonics is negligible, including the harmonicslaced at 2fSW. This verifies the design procedure of the gridlter and, also, the VSC1 current controller algorithms. For the

wo other experiments, the harmonics are very similar: only theundamental harmonic amplitude increases 5A approximately.

. Conclusions

This paper presents the design and implementation of aeal-time controller for a 150 kVA back-to-back Neutral Point

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ms Research 78 (2008) 1597–1609

lamped (NPC) Voltage Source Converter (VSC) used on windower applications. The design follows a modular approachased on a floating-point DSP and on an FPGA, combining theexibility and processing power from both devices. The con-

rol electronic platform assembly has been shown, as well ashe distribution of the tasks between the chosen two proces-ors, a floating-point DSP and a FPGA, and the programmingf these devices. Measurements of execution times, operationf different control algorithms and experimental tests about theower electronic system have verified the correct operation ofhe proposed real-time controller.

cknowledgment

This work has been funded by the Spanish AdministrationMEC: ENE2005-08721-C04-01).

eferences

[1] A. Fratta, G. Griffero, S. Nieddu, Comparative Analysis among DSP andFPGA-based Control Capabilities in PWM Power Converters, in: Proceed-ings of the 30th Annual Conference of the IEEE Industrial Society, Busan,Korea, November 2–8, 2004, pp. 257–262.

[2] G. Iwanski, W. Koczara, Control system of the variable speed autonomousdoubly fed induction generator, in: EPE-PEMC04-11th International PowerElectronics and Motion Control Conference, Riga, Latvia, September 2–4,2004.

[3] G. Gateau, R. Ruelland, M. Aime, A co-simulation environment for thetest and the validation of digital control strategy on a mixed DSP/FPGAarchitecture, in: EPE PEMC04-11th International Power Electronics andMotion Control Conference, Riga, Latvia, September 2–4, 2004.

[4] P. Field, G. Peters 1, S. Round, A control strategy for a soft-switched bidi-rectional motor drive with PWM motor voltage synthesis, in: EPE’03, 10thEuropean Conference on Power Electronics and Applications, Toulouse,France, September 2–4, 2003.

[5] V. Dinavahi, R. Iravani, R. Bonert, Design of a real-time digital simulatorfor D-STATCOM system, IEEE Trans. Ind. Electr. 51 (October (5)) (2004)1001–1008.

[6] Z. Bielewicz, L. Debowski, E. Lowiec, A DSP and FPGA based integratedcontroller development solutions for high performance electric drives, in:Proceedings of the IEEE International Symposium on Industrial Electron-ics, ISIE’96, vol. 2, June 17–20, 1996, pp. 679–684.

[7] S.S. Kim, S. Jung, Hardware implementation of a real time neural networkcontroller with a DSP and an FPGA, in: Proceedings of the IEEE Inter-national Conference on Robotics and Automation, ICRA’04, vol. 5, April26–May 1, 2004, pp. 4639–4644.

[8] Spanish Grid Institution. http://www.ree.es.[9] R. Ottersten, On control of Back-to-Back Converters and Sensorless Induc-

tion Machine Drives, Thesis for the degree of doctor of philosophy,Department of Electric Power Engineering, Chalmers University of Tech-nology, Goteborg, Sweden, 2003.

10] E.J. Bueno, S. Cobreces, F.J. Rodrıguez, A. Hernandez, F. Espinosa, R.Mateos, F. Lopez, Optimizes design of a back-to-back NPC converter tobe used as interface for renewable energies, in: Proceedings of the 31stAnnual Conference of the Industrial Electronics Society, IECON, 2005,pp. 2543–2548.

11] Texas Instruments. http://www.ti.com/.12] Xilinx. http://www.xilinx.com.13] Spectrum Digital. http://www.spectrumdigital.com.

14] Digilent. http://www.digilentinc.com.15] V. Blasko, V. Kaura, W. Niewiadomski, Sampling of discontinuous voltage

and current signals in electrical drives: a system approach, IEEE Trans.Ind. Appl. 34 (September/October (5)) (1998) 1123–1130.

16] Dallas Semiconductor—Maxim. http://www.maxim-ic.com/.

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F.J. Rodrıguez et al. / Electric Power

17] E. Bueno, F.J. Rodrıguez, F. Espinosa, S. Cobreces, SPLL design to flux

oriented of a VSC interface for wind power applications, in: Proceedings ofthe 31st Annual Conference of the Industrial Electronics Society, IECON,2005, pp. 2451–2456.

18] Texas Instruments, TMS320C6000DPS External Memory Interface(EMIF) Reference Guide, Literature Number: SPRU266D, April 2005.

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ms Research 78 (2008) 1597–1609 1609

19] Texas Instruments, TMS320C6000 DSP/BIOS 5.20 Application Program-

ming Interface (API) Reference Guide, 2005.

20] E.J. Bueno, R. Garcıa, M. Marron, J. Urena, F. Espinosa, Modulation tech-niques comparison for three levels VSI converter, in: Proceedings of the28th IEEE Annual Conference of the IECON, vol. 2, November 5–8, 2002,pp. 908–913.