Computer Component Primitives Adder Multiplier Latch Decoder Disks Main Memory Cacheline Line Selection Logic Bit Cell Cache Controller RAM Decoder Processor 2 114 17 100 0 1 2 3 Addresses

Department of Electrical & Computer Engineering

EC 413Computer Organization

Prof. Michel A. Kinsy

Computer Component PrimitivesDigital timing, MUXes, Busses, Tri-states


Computing Systems

§ A system is a set of related components that works as a whole to achieve a goal

§ A system contains: • Inputs • Behavior• Outputs

§ Behavior is a function that translates inputs to outputs

Behaviorinputs outputs: :


Computing Systems§ A system contains:

• Inputs • Behavior• Outputs

§ Our second view of computer organization• Computer

Organization v2


Instruction +

DataResults

Processor

2

114

17

100

0

1

2

3

Addresses Data

MemoryDatatransfer

+/- *

Registers





Organization v2


Instruction +

DataResults

Processor

2

114

17

100

0

1

2

3

Addresses Data

MemoryDatatransfer

inst<19:15>inst<24:20>

inst<11:7>

inst<14:12>

Instrcution

ALUControl

RegWriteclk

rd1

GPRs

rs1rs2

wswd rd2

we

ALU

rd ß(rs) func (rt)funct7 rs2 funct3rs1 rd opcode7 5 5 3 5 7


Computer Organization Overview§ The modern digital computer has three major

functional hardware units: CPU, Main Memory and Input/Output (I/O) Units

Processor Memory

Control Bus

211417

100

ReadAddress

Instruction[31-0]

ADD

PC

4

Write Data

Read Addr 1

Read Addr 2

Write AddrRegister File

Read Data 1

Read Data 2

ALU

Overflow

zero

RegWrite

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend

16 32

MemtoReg

ALUSrc

Shiftleft 2

ADD

PCSrc

RegDst

ALUControl

1

1

1

0

00

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Branch

Device#1

Device#n

I/O Devices

…

Address Bus

Data Bus


The Computer§ Our second view of computer organization

Computer

Memory SystemCPU

ALU Register File

Adder MultiplierComparator Latch Decoder

Disks Main Memory

Cacheline

Line Selection Logic Bit Cell

Cache

Controller RAM Decoder

Processor

2

114

17

100

0

1

2

3

Addresses Data

MemoryDatatransfer

+/- *

Registers


Computing: The Art of Abstraction

Algorithm

Register-Transfer Level (RTL)

Application

Instruction Set Architecture (ISA)Operating System/Virtual Machine

Microarchitecture

Devices

Programming Language

Circuits

Physics


Full Ecosystem View

OperatingSystem

ProgrammingLanguage

Applications&Algorithms

Firmware

Datapath&Control

DigitalDesign

CircuitDesign

Layout

I/OsystemProcessor MemoryorganizationISA

Compiler


Computing: Computer Organization

Computer

Memory SystemCPU

ALU Register File

Adder MultiplierComparator Latch Decoder

Disks Main Memory

Cacheline

Line Selection Logic Bit Cell

Cache

Controller RAM Decoder

§ The DNA of Modern Computing


Transistor§ Uses Silicon§ Developed in 1947 in Bell

Laboratories by William Shockley, John Bardeen and Walter Brattain Won a Nobel prize

§ On-off switch


Transistors§ MOS - Metal-Oxide Semiconductor§ MOS transistors have three terminals: drain, gate,

and source§ A transistor acts as switches:

§ If the voltage on the gate terminal is higher/lower than the source terminal then a conducting path will be established between the drain and source terminals

G

S D

G

S Dn-channel p-channel


Transistors§ CMOS - Complementary MOS§ Transistors are the primary

components of ICs§ An integrated circuit (IC) or a chip is

made up of transistors (these days billions) and other electronic components§ ICs are the building blocks of

computers (CPU, bus interface, memory management unit)

OI

Vss

Vdd


First Integrated Circuit§ Invented at Texas Instruments by Jack Kilby in

1958


Computer & Digital Design § Boolean algebra serves as the basis for computer

logic design§ Transistors are the mean to implement Boolean

algebra in modern computer systems§ Basic Boolean algebra

§ Set of Elements: {0,1}§ Set of Operations: {., + , ¬ }

§ Digital equivalence § Signals: High = 5V = 1; Low = 0V = 0


TransistorsArchitecture Transistor

CountYear Maker Technology

SizeIntel 4004 2,300 1971 Intel 10μm

Intel 8008 3,500 1972 Intel 10μm

Quad-core 2,000,000,000 2010 Intel 65nm

61-core Xeon Phi

5,000,000,000 2012 Intel 22nm

Xbox One 5,000,000,000 2013 Microsoft/AMD

28nm

18-core Xeon Haswell-E5

5,560,000,000 2014 Intel 22nm


Boolean Algebra to Digital Design

x0011

y0101

F0001

x0011

y0101

F0111

x01

F10

xy F

OR

Fxy

AND

0

1

y

x

x

y

F

1

0

Fx

FxNOT

Symbol/Gate

Truth table

Transistorcircuit

0

1

x y

Fy

x


Logic Gates

X = (A + B)’

Name Symbol Function Truth Table

AND 0 0 00 1 01 0 01 1 1

0 0 00 1 11 0 11 1 1

OR

NOT X = A’

NANDX = (AB)’

NOR

XORExclusive OR

X = A Å BOrX = A’B + AB’

X = (A Å B)’orX = A’B’+ AB

XNOR

Exclusive NORor Equivalence

A B X

A B X

0 11 0

A X

0 0 10 1 11 0 11 1 0

A B X

0 0 10 1 01 0 01 1 0

A B X

0 0 00 1 11 0 11 1 0

A B X

0 0 10 1 01 0 01 1 1

A B X

X = A • BorX = AB

A

BX

A

BX X = A + B

A X

A

BX

A

BX

A

BX

A

BX


Boolean Algebra to Digital Design§ Addition

§ Truth Table

1 0 0 1 0 1 0 1

Sum 1 1 1 0Carry 0 0 0 1

A B Cin Sum Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1



§ Truth Table

§ Equations

A B Cin Sum Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

Sum=Cin .A’.B’+ B.Cin’.A’+ A.Cin’.B’+ A.B.Cin

Cout =A’.B.Cin + A.B’.Cin + A.Cin’.B+ B.Cin .A=A.B+ A.Cin + B.Cin



Sum=Cin .A’.B’+ B.Cin’.A’+ A.Cin’.B’+ A.B.Cin

A

B

Cin

Sum


Boolean Algebra to Digital DesignCout =A’.B.Cin + A.B’.Cin + A.Cin’.B+ B.Cin .A

=A.B+ A.Cin + B.Cin

A

B

Cin

Cout


Types of Digital Circuits § Combinatorial logic

§ A combinational circuit consists of logic gates whose outputs, at any time, are determined by combining the values of the inputs

§ Sequential logic§ Output depends not only on the present value of its

input signals but on the sequence of past inputs

CombinationalCircuits

Inputs outputs


Types of Digital Circuits § Sequential logic

§ Output depends not only on the present value of its input signals but on the sequence of past inputs

§ We now have a memory requirement!


Inputs outputs

Memory

next statepresent state


Memory & Digital Design § A sequential circuit combinational circuit with

feedback through memory§ The stored information at any time defines a state

§ Outputs depends on inputs and previous inputs§ Previous inputs are stored as binary information into

memory§ Next state depends on inputs and present state


Inputs outputs

Memory



Types of Digital Circuits § Sequential logic

§ Storage elements observe inputs and can change state only in relation to a timing signal

§ Need for discrete instances of time§ We now have a clock requirement!

CLOCK


inputs x outputs

Memory



Clock § A synchronous system is synchronized according

to a clock§ A clock cycle or cycle time or clock period is the

duration between two consecutive rising or falling edges

Cycle time Rising clock edge

Falling clock edge

4 GHz = clock speed = 1 = 1 cycle time 250 ps





Organization v2

+/- *

I/O

Clock

Mem

oryBehaviorinputs outputs

: :

Instruction +

DataResults

Processor

2

114

17

100

0

1

2

3

Addresses Data

MemoryDatatransfer

inst<19:15>inst<24:20>

inst<11:7>

inst<14:12>

Instrcution

ALUControl

RegWriteclk

rd1

GPRs

rs1rs2

wswd rd2

we

ALU

rd ß(rs) func (rt)funct7 rs2 funct3rs1 rd opcode7 5 5 3 5 7


Storage Elements (Memory)§ A storage element can maintain a binary state

(0,1), until directed by an input signal to switch state

§ Main difference between storage elements:§ Number of inputs they have§ How the inputs affect the binary state


Storage Elements (Memory)§ A storage element can maintain a binary state

(0,1), until directed by an input signal to switch state

§ Two main types:§ Latches (level-sensitive)§ Flip-Flops (edge-sensitive)

§ Latches are useful in asynchronous sequential circuits

§ Flip-Flips are built with latches


Latches & Flip Flops § A latch is binary storage element§ Can store a 0 or 1§ The most basic memory§ Easy to build

§ Built with gates (NORs, NANDs, NOT)

S’R’ LatchSR Latch


Latches & Flip Flops § A latch is binary storage element§ Can store a 0 or 1§ The most basic memory§ Easy to build

§ Built with gates (NORs, NANDs, NOT)

SR Latch with Clock D Latch


Latches & Flip Flops § A flip flop can be built using two latches in a

master-slave configuration§ A master latch receives external inputs§ A slave latch receives inputs from the master latch§ Depending on the clock signal, only one latch is

active at any given time§ If clock=1, the master latch is enabled and the inputs

are latched§ if clock=0, the master is disabled and the slave is

activated to generate the outputs


Computer Hardware Elements§ Combinational circuits

§ Mux, Demux, Decoder, ALU, ...

Sel

O

A0

A1

An-1

Mux...

lg(n)

Sel

O0

O1

On-1

A

De

mu

x

.

.

.

lg(n)

AD

eco

de

r

.

..

O0

O1

On-1

lg(n)

OpSelect- Add, Sub, ...- And, Or, Xor, Not, ...- GT, LT, EQ, Zero, ...

Result

Comp?

A

B

ALU


Computer Hardware Elements

§ Multiplexer (Mux)§ A Mux a digital

building block for selecting and routing signals

§ It has§ Data inputs§ Control inputs§ An output

§ The control inputs select which data inputs to be connected to the output

Sel

OA0

A1

An-1

Mux

.

..

lg(n)

O

Sel

A1

0

1

A0 O

A1

A0

Sel


Computer Hardware Elements§ Demux

§ Used to router a signal to one of multiple outputs

§ Single data input§ Log (n) control inputs§ n outputs

§ Select bits decide which output is connected to the input

Sel

O0

O1

On-1

A

De

mu

x

.

.

.

lg(n)

O0A

Sel

O1



§ Decoder converts an n-bit input code to an m-bit output with n ≤ m ≤ 2n

§ Each valid input needs to produce a unique output

§ For example used for I/O selection

A

De

cod

er

.

..

O0

O1

On-1

lg(n)

O0A0

O1

O3

O4

A1

A1 A0 O3 O2 O1 O0

0 0 0 0 0 10 1 0 0 1 01 0 0 1 0 01 1 1 0 0 0


Computer Hardware Elements§ Encoder performs the inverse

operation of a decoder § It has 2n (or fewer) inputs and

produces n output lines that indicate which single bit of the input is active

8 inputs 3 outputs

O0

O1

O2

01234567

A0

A7

012

En

cod

er

O

.

..

A0

A1

An-1

lg(n)

A2A3A6A7O1

A1A3A5A7O0

A4A5A6A7O3

The an active signal to differentiate between A0 = 0 and A0 = 1.


Computer Hardware Elements§ Buses and Tri-State

Logics§ Our second view of

computer organization§ Computer

Organization v2§ Data Transfer Bus§ An essential part of

the computer’s organization

CPU Memory I/O

Data

Address

Control

+/- *

I/OClock

Mem

ory


Computer Hardware Elements§ Buses and Tri-State

Logics§ Our second view of

computer organization§ Computer

Organization v2§ Since there are multiple

units and devices on the buses, Tri-state logic is needed to prevent a bus conflict

CPU Memory I/O

Data

Address

Control

Enable

Input Output


Three-State Gates§ Tri-State Buffer

§ Tri-State Inverter A Y

C

C A Y0 x Hi-Z1 0 01 1 1

A Y

C



§ Synchronous state elements§ Flipflop, Register, Register file, SRAM, DRAM§ Edge-triggered: Data is sampled at the rising

edge

Clk

D

Q

Enff

Q

D

Clk

En


A Simple Memory Model§ Reads and writes are always completed in one

cycle§ a Read can be done any time (i.e. combinational)§ a Write is performed at the rising clock edge

§ If it is enabled Then the write address and data must be stable at the clock edge

MAGICRAM

ReadDataWriteData

Address

WriteEnableClock


Circuit Complexity Classes§ SSI - Small-Scale Integration

§ Several (less than 10) independent gates

§ MSI - Medium-Scale Integration § 10 to 200 gates

§ LSI - Large-Scale Integration § 200 to few thousand gates

§ VLSI - Very-Large-Scale Integration § Thousands to Billions of gates


Next Class§ Arithmetic Logic Unit (ALU) and Register File

Documents

Computer Component Primitives Adder Multiplier Latch Decoder Disks Main Memory Cacheline Line Selection Logic Bit Cell Cache Controller RAM Decoder Processor 2 114 17 100 0 1 2 3 Addresses