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6-2 • Comprehensive VHDL: Types Copyright © 2000 Doulos
Types
Aim To understand the use and synthesis of enumeration
types, STD_LOGIC and STD_LOGIC_VECTOR
Topics covered Enumeration types Type STD_LOGIC and bus resolution Initial values Slices and concatenation Overloading and conversion Standard packages
6-3 • Comprehensive VHDL: Types Copyright © 2000 Doulos
Enumeration Types
type Opcode is (Add, Neg, Load, Store, Jmp, Halt);
signal S: Opcode;
type Opcode is (Add, Neg, Load, Store, Jmp, Halt);
signal S: Opcode;
S <= Add;S <= Add;
process (S)
begin
case S is
when Add
=>
...
process (S)
begin
case S is
when Add
=>
...
Defining a new data type for a control bus
6-4 • Comprehensive VHDL: Types Copyright © 2000 Doulos
Synthesis of Enumeration Types
000001101Halt
000010100Jmp
000100011Store
001000010Load
010000001Neg
100000000Add
One HotBinary
Synthesis
ASIC ToolsASIC Tools FPGA ToolsFPGA Tools
6-5 • Comprehensive VHDL: Types Copyright © 2000 Doulos
Multi-Valued Logic Types
type BOOLEAN is (FALSE, TRUE);
type BIT is ('0', '1');
type BOOLEAN is (FALSE, TRUE);
type BIT is ('0', '1');
type STD_ULOGIC is ( 'U', -- Uninitialized (the default) 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance 'W', -- Weak Unknown 'L', -- Weak 0 'H', -- Weak 1 '-'); -- Don't care (for synthesis)
subtype STD_LOGIC is RESOLVED STD_ULOGIC;
type STD_ULOGIC is ( 'U', -- Uninitialized (the default) 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance 'W', -- Weak Unknown 'L', -- Weak 0 'H', -- Weak 1 '-'); -- Don't care (for synthesis)
subtype STD_LOGIC is RESOLVED STD_ULOGIC;
In package STD.STANDARDIn package STD.STANDARD
In package IEEE.STD_LOGIC_1164In package IEEE.STD_LOGIC_1164
For resolving bus conflictsFor resolving bus conflicts
6-6 • Comprehensive VHDL: Types Copyright © 2000 Doulos
Logical Operators
Logical operators
and
nand
or
nor
xor
not
and
nand
or
nor
xor
not
Defined on types
BOOLEAN
BIT
BIT_VECTOR
STD_LOGIC
STD_LOGIC_VECTOR
BOOLEAN
BIT
BIT_VECTOR
STD_LOGIC
STD_LOGIC_VECTOR
xnorxnor
VHDL 93VHDL 93
6-7 • Comprehensive VHDL: Types Copyright © 2000 Doulos
Tristate Drivers
signal BUSS, ENB1, ENB2, D1, D2: STD_LOGIC;... TRISTATE1: process (ENB1, D1)begin if ENB1 = '1' then BUSS <= D1; else BUSS <= 'Z'; end if;end process;
TRISTATE2: process (ENB2, D2)begin if ENB2 = '1' then BUSS <= D2; else BUSS <= 'Z'; end if;end process;
ResolutionFunction
BUSS
DriverTristate1,
BUSS
DriverTristate2,
BUSS
subtype STD_LOGIC is RESOLVED STD_ULOGIC;subtype STD_LOGIC is RESOLVED STD_ULOGIC;
6-8 • Comprehensive VHDL: Types Copyright © 2000 Doulos
STD_LOGIC Bus Resolution
'W'
'1''0'
'X'
'L' 'H'
‘ - ’
'Z'
'U' Strength of STD_LOGIC values is
defined in package STD_LOGIC_1164
Values higher in the lattice are stronger
6-9 • Comprehensive VHDL: Types Copyright © 2000 Doulos
Initial Values
type Opcode is (Add, Neg, Load, Store, Jmp, Halt);
signal S: Opcode;
signal CLOCK, RESET: STD_LOGIC;
variable V1: STD_LOGIC_VECTOR(0 to 1);
variable V2: STD_LOGIC_VECTOR(0 to 1) := "01";
signal N: Opcode := Halt;
constant SIZE: INTEGER := 16;
constant ZERO: STD_LOGIC_VECTOR := "0000";
type Opcode is (Add, Neg, Load, Store, Jmp, Halt);
signal S: Opcode;
signal CLOCK, RESET: STD_LOGIC;
variable V1: STD_LOGIC_VECTOR(0 to 1);
variable V2: STD_LOGIC_VECTOR(0 to 1) := "01";
signal N: Opcode := Halt;
constant SIZE: INTEGER := 16;
constant ZERO: STD_LOGIC_VECTOR := "0000";
Signals and variables are initialized at the start of simulation
Default value is the leftmost value of the type
Synthesis ignores initial values
Initial value AddInitial value Add
Initial value 'U'Initial value 'U'
Initial value "UU"Initial value "UU"
6-10 • Comprehensive VHDL: Types Copyright © 2000 Doulos
Slice Names
V(2 to 5)
variable V: STD_LOGIC_VECTOR(0 to 7);
variable F: STD_LOGIC_VECTOR(3 downto 0);
variable V: STD_LOGIC_VECTOR(0 to 7);
variable F: STD_LOGIC_VECTOR(3 downto 0);
F := V(2 to 5)F := V(2 to 5)
F(1 downto 0) := "11";F(1 downto 0) := "11";
V(0 to 1) := F(3 downto 2);V(0 to 1) := F(3 downto 2);
6-11 • Comprehensive VHDL: Types Copyright © 2000 Doulos
Concatenation
signal A, B: STD_LOGIC_VECTOR(7 downto 0);
signal F : STD_LOGIC_VECTOR(15 downto 0);
signal A, B: STD_LOGIC_VECTOR(7 downto 0);
signal F : STD_LOGIC_VECTOR(15 downto 0);
123 0
A
567 4 123 0
& B
567 4
91011 8
F
131415 12 123 0567 4
F <= A & B;F <= A & B;
Concatenation operator “&”
6-12 • Comprehensive VHDL: Types Copyright © 2000 Doulos
Shifting
Logical shift left:
signal REG: STD_LOGIC_VECTOR(N-1 downto 0);
REG <= REG(N-2 downto 0) & '0';
signal REG: STD_LOGIC_VECTOR(N-1 downto 0);
REG <= REG(N-2 downto 0) & '0';
REG before
REG after
123 0N-1 N-2
0
123 0N-1 N-2
6-13 • Comprehensive VHDL: Types Copyright © 2000 Doulos
Operator Overloading
library IEEE;use IEEE.STD_LOGIC_1164.all;
entity ADDER is port (A, B: in STD_LOGIC_VECTOR(7 downto 0); SUM : out STD_LOGIC_VECTOR(7 downto 0));end;
architecture A1 of ADDER isbegin SUM <= A + B; end;
Error: "+" is not defined for type STD_LOGIC_VECTOR
Error: "+" is not defined for type STD_LOGIC_VECTOR
6-14 • Comprehensive VHDL: Types Copyright © 2000 Doulos
Standard Packages
BOOLEAN
BIT
BIT_VECTOR
INTEGER
REAL
TIME
STRING
CHARACTER
BOOLEAN
BIT
BIT_VECTOR
INTEGER
REAL
TIME
STRING
CHARACTER
Package IEEEE.STD_LOGIC_1164Package STD.STANDARD
=
/=
>
>=
<
<=
=
/=
>
>=
<
<=
STD_LOGIC
STD_LOGIC_VECTOR
STD_LOGIC
STD_LOGIC_VECTOR
and
nand
or
nor
xor
not
and
nand
or
nor
xor
not
Types
OperatorsImplicit operators
Types
6-15 • Comprehensive VHDL: Types Copyright © 2000 Doulos
Implicit Relational Operators
'U' < 'X' < '0' < '1' < 'Z' < 'W' < 'L' < 'H' < '-''U' < 'X' < '0' < '1' < 'Z' < 'W' < 'L' < 'H' < '-'
"0" < "00" < "000" < "001" < "100" < "111" < "1111" "0" < "00" < "000" < "001" < "100" < "111" < "1111"
Beware: for type STD_LOGIC_VECTOR
Beware: for type STD_LOGIC
6-16 • Comprehensive VHDL: Types Copyright © 2000 Doulos
Using NUMERIC_STD
library IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.NUMERIC_STD.all;
entity ADDER is port (A, B: in UNSIGNED(7 downto 0); SUM : out UNSIGNED(7 downto 0));end;
architecture A1 of ADDER isbegin SUM <= A + B; end;
IEEE Std 1076.3IEEE Std 1076.3
6-17 • Comprehensive VHDL: Types Copyright © 2000 Doulos
Conversion Functions
N <= TO_INTEGER(U);
N <= TO_INTEGER(S);
U <= TO_UNSIGNED(N, 8);
S <= TO_SIGNED(N, 8);
N <= TO_INTEGER(U);
N <= TO_INTEGER(S);
U <= TO_UNSIGNED(N, 8);
S <= TO_SIGNED(N, 8);
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
signal U: UNSIGNED(7 downto 0);
signal S: SIGNED(7 downto 0);
signal N: INTEGER;
signal U: UNSIGNED(7 downto 0);
signal S: SIGNED(7 downto 0);
signal N: INTEGER;
6-18 • Comprehensive VHDL: Types Copyright © 2000 Doulos
Array Type Conversion
signal U: UNSIGNED(7 downto 0);
signal S: SIGNED(7 downto 0);
signal V: STD_LOGIC_VECTOR(7 downto 0);
signal U: UNSIGNED(7 downto 0);
signal S: SIGNED(7 downto 0);
signal V: STD_LOGIC_VECTOR(7 downto 0);
U <= UNSIGNED(S);
S <= SIGNED(U);
U <= UNSIGNED(V);
S <= SIGNED(V);
V <= STD_LOGIC_VECTOR(U);
V <= STD_LOGIC_VECTOR(S);
U <= UNSIGNED(S);
S <= SIGNED(U);
U <= UNSIGNED(V);
S <= SIGNED(V);
V <= STD_LOGIC_VECTOR(U);
V <= STD_LOGIC_VECTOR(S);
Closely related typesClosely related types
Type name used for type conversionType name used for type conversion
Type Conversions between closely related types
6-19 • Comprehensive VHDL: Types Copyright © 2000 Doulos
Numeric_std and Std_logic_vector
signal V: STD_LOGIC_VECTOR(7 downto 0);
signal N: INTEGER;
signal V: STD_LOGIC_VECTOR(7 downto 0);
signal N: INTEGER;
N <= TO_INTEGER(UNSIGNED(V));
V <= STD_LOGIC_VECTOR(TO_UNSIGNED(N, 8));
N <= TO_INTEGER(UNSIGNED(V));
V <= STD_LOGIC_VECTOR(TO_UNSIGNED(N, 8));
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
Type conversionType conversion Conversion functionConversion function
V <= STD_LOGIC_VECTOR(SIGNED(V) + 1);V <= STD_LOGIC_VECTOR(SIGNED(V) + 1);
Type conversionType conversionConversion functionConversion function
6-20 • Comprehensive VHDL: Types Copyright © 2000 Doulos
Summary of NUMERIC_STD
+ - * / rem mod
< <= > >= = /=
UNSIGNED x UNSIGNED
UNSIGNED x NATURAL
NATURAL x UNSIGNED
SIGNED x SIGNED
SIGNED x INTEGER
INTEGER x SIGNED
+ - * / rem mod
< <= > >= = /=
UNSIGNED x UNSIGNED
UNSIGNED x NATURAL
NATURAL x UNSIGNED
SIGNED x SIGNED
SIGNED x INTEGER
INTEGER x SIGNED
TO_INTEGER [UNSIGNED ] return INTEGER
TO_INTEGER [SIGNED ] return INTEGER
TO_UNSIGNED [NATURAL, NATURAL] return UNSIGNED
TO_SIGNED [INTEGER, NATURAL] return SIGNED
RESIZE [UNSIGNED, NATURAL] return UNSIGNED
RESIZE [SIGNED, NATURAL] return SIGNED
TO_INTEGER [UNSIGNED ] return INTEGER
TO_INTEGER [SIGNED ] return INTEGER
TO_UNSIGNED [NATURAL, NATURAL] return UNSIGNED
TO_SIGNED [INTEGER, NATURAL] return SIGNED
RESIZE [UNSIGNED, NATURAL] return UNSIGNED
RESIZE [SIGNED, NATURAL] return SIGNED
sll srl rol ror
UNSIGNED x INTEGER
SIGNED x INTEGER
sll srl rol ror
UNSIGNED x INTEGER
SIGNED x INTEGER
not and or nand nor
xor xnor
UNSIGNED x UNSIGNED
SIGNED x SIGNED
not and or nand nor
xor xnor
UNSIGNED x UNSIGNED
SIGNED x SIGNED
Signatures (VHDL 93)Signatures (VHDL 93)
6-21 • Comprehensive VHDL: Types Copyright © 2000 Doulos
Shift and Rotate Operators
sll
srl
sla
sra
rol
ror
sll
srl
sla
sra
rol
ror
BIT_VECTORBIT_VECTOR VHDL 93VHDL 93
sll
srl
rol
ror
sll
srl
rol
ror
SIGNED
UNSIGNED
SIGNED
UNSIGNED
signal S: SIGNED;
S <= S srl 1;
signal S: SIGNED;
S <= S srl 1;
Shift right one place and sign extendShift right one place and sign extend
6-22 • Comprehensive VHDL: Types Copyright © 2000 Doulos
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Adder is
port (A : in STD_LOGIC_VECTOR(7 downto 0);
B : in INTEGER;
C : in SIGNED(7 downto 0);
SUM: out SIGNED(7 downto 0));
end;
architecture Arch of Adder is
begin
SUM <=
;
end;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Adder is
port (A : in STD_LOGIC_VECTOR(7 downto 0);
B : in INTEGER;
C : in SIGNED(7 downto 0);
SUM: out SIGNED(7 downto 0));
end;
architecture Arch of Adder is
begin
SUM <=
;
end;
Quiz 1Fill in the box
6-23 • Comprehensive VHDL: Types Copyright © 2000 Doulos
Quiz 1 Solution
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Adder is
port (A : in STD_LOGIC_VECTOR(7 downto 0);
B : in INTEGER;
C : in SIGNED(7 downto 0);
SUM: out SIGNED(7 downto 0));
end;
architecture Arch of Adder is
begin
SUM <=
;
end;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Adder is
port (A : in STD_LOGIC_VECTOR(7 downto 0);
B : in INTEGER;
C : in SIGNED(7 downto 0);
SUM: out SIGNED(7 downto 0));
end;
architecture Arch of Adder is
begin
SUM <=
;
end;
SIGNED(A) + B + C;
6-24 • Comprehensive VHDL: Types Copyright © 2000 Doulos
Quiz 2
Fill in the box
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Mux8to1 is
port (Address: in Std_logic_vector(2 downto 0);
IP: in Std_logic_vector(7 downto 0);
OP: out Std_logic);
end;
architecture Arch of Mux8to1 is
begin
OP <= IP( (Address) );
end;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Mux8to1 is
port (Address: in Std_logic_vector(2 downto 0);
IP: in Std_logic_vector(7 downto 0);
OP: out Std_logic);
end;
architecture Arch of Mux8to1 is
begin
OP <= IP( (Address) );
end;
6-25 • Comprehensive VHDL: Types Copyright © 2000 Doulos
Quiz 2 Solution
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Mux8to1 is
port (Address: in Std_logic_vector(2 downto 0);
IP: in Std_logic_vector(7 downto 0);
OP: out Std_logic);
end;
architecture Arch of Mux8to1 is
begin
OP <= IP( (Address) );
end;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Mux8to1 is
port (Address: in Std_logic_vector(2 downto 0);
IP: in Std_logic_vector(7 downto 0);
OP: out Std_logic);
end;
architecture Arch of Mux8to1 is
begin
OP <= IP( (Address) );
end;TO_INTEGER(UNSIGNED )));
6-26 • Comprehensive VHDL: Types Copyright © 2000 Doulos
Package STD_LOGIC_UNSIGNED/SIGNED
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- use IEEE.STD_LOGIC_SIGNED.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- use IEEE.STD_LOGIC_SIGNED.all;Don't use bothDon't use both
+ -
STD_LOGIC_VECTOR
STD_ULOGIC
INTEGER
+ -
STD_LOGIC_VECTOR
STD_ULOGIC
INTEGER
CONV_INTEGER[STD_LOGIC_VECTOR] return INTEGERCONV_INTEGER[STD_LOGIC_VECTOR] return INTEGER
< <= > >= = /=
STD_LOGIC_VECTOR
INTEGER
< <= > >= = /=
STD_LOGIC_VECTOR
INTEGER
*
STD_LOGIC_VECTOR
*
STD_LOGIC_VECTOR
6-27 • Comprehensive VHDL: Types Copyright © 2000 Doulos
Package STD_LOGIC_ARITH
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
+ -
UNSIGNED
SIGNED
STD_ULOGIC
INTEGER
+ -
UNSIGNED
SIGNED
STD_ULOGIC
INTEGER
CONV_INTEGER [INTEGER/UNSIGNED/SIGNED/STD_ULOGIC] return INTEGER
CONV_UNSIGNED[INTEGER/UNSIGNED/SIGNED/STD_ULOGIC , INTEGER] return UNSIGNED
CONV_SIGNED [INTEGER/UNSIGNED/SIGNED/STD_ULOGIC , INTEGER] return SIGNED
CONV_STD_LOGIC_VECTOR[INTEGER/UNSIGNED/SIGNED/STD_ULOGIC , INTEGER]
return STD_LOGIC_VECTOR
EXT[STD_LOGIC_VECTOR , INTEGER] return STD_LOGIC_VECTOR
SXT[STD_LOGIC_VECTOR , INTEGER] return STD_LOGIC_VECTOR
CONV_INTEGER [INTEGER/UNSIGNED/SIGNED/STD_ULOGIC] return INTEGER
CONV_UNSIGNED[INTEGER/UNSIGNED/SIGNED/STD_ULOGIC , INTEGER] return UNSIGNED
CONV_SIGNED [INTEGER/UNSIGNED/SIGNED/STD_ULOGIC , INTEGER] return SIGNED
CONV_STD_LOGIC_VECTOR[INTEGER/UNSIGNED/SIGNED/STD_ULOGIC , INTEGER]
return STD_LOGIC_VECTOR
EXT[STD_LOGIC_VECTOR , INTEGER] return STD_LOGIC_VECTOR
SXT[STD_LOGIC_VECTOR , INTEGER] return STD_LOGIC_VECTOR
< <= > >= = /=
UNSIGNED
SIGNED
INTEGER
< <= > >= = /=
UNSIGNED
SIGNED
INTEGER
*
UNSIGNED
SIGNED
*
UNSIGNED
SIGNED