Compound semiconductors on silicon

Compound Semiconductors on Si|icon

Dr Alan Mills PO Box 4098, Mountain View,

CA 94o4o, USA Tel/fax: +~-65o-968-~383/84~6

E-mail. [email protected]

30

For more than 2o years many millions of dol- lars have been spent for the growth of gallium arsenide and other hetero-materials on silicon for all the obvious reasons, larger, cheaper and higher quality substrates available in quantity (mostly elemental Groups IIl-V and II-Vl). Unfortunately most of it was spent producing either little success or a cost in excess of the competing compound

semiconductor substrate. And, for some time the only compound semiconductor that showed promise was silicon-germanium, which does not quite present the same technology challenge, since both elements are in the same Group IV of the Periodic Table and therefore the silicon-germanium material system may be classed as an alloy rather than a compound.

Compound Semiconductors on Silicon

2000/~ of a gallium arsenide seed layer are deposited to

form a pseudo substrate

The results of combin ing these dissimilar materi-

als are n o w in f rom several research groups and

they are close to changing the out look for these

in ter group, or hetero-epi taxial processes f rom

dim to very promis ing or even to a lmost com-

mercial, (based on the latest gallium arsenide and

gallium ni t r ide on silicon process advances). As

r epo r t ed in III-Vs Review earlier this year,

Motorola and IQE have b e e n coopera t ing to

develop the depos i t ion of MBE-grown gall ium

arsenide on silicon wafers for about one year.

This coopera t ion b e t w e e n Motorola and IQE

already includes a Cus tom Evaluation Agreement

o p e n to IQE and Motorola cus tomers , a Service

and Coopera t ion Agreement in w h i c h Motorola

Gallium arsenide I /

Amorphous SiO2 i ~

Silicon substrate I

Template layer required to prepare the surface of STO to accept GaAs

Single crystal STO provides the surface for growing GaAs

Amorphous SiO2 layer formed during growth of STO on silicon. decouples the Si from the overlying GaAs - absorbs strain associated with lattice and temperature mismatch

will pu rchase deve lopmen t services f rom IQE, a

$10 million equity inves tmen t by Motorola in

IQE, a $14 mill ion three year equity draw d o w n

facility for IQE and an addit ional $10 million pur-

chase of war ran t op t ions in IQE, ex tend ing over

five years.

Gallium Arsenide The Motorola process involves the use of h igh

die lectr ic-constant oxide-interlayers, such as

s t ron t ium t i tanate (STO), w h i c h inhibi t react ion

b e t w e e n the silicon and the epitaxially g rown

gallium arsenide layers. If electrical conduct iv i ty

to the substrates is required, the STO layer can

be doped w i th concen t ra t ions of up to lOE19

atoms pe r cm3 of a lumin ium.The crystall ine qual-

ity of this STO on silicon is r epor t ed to be be t t e r

than any single crystal STO current ly available.

Originally, Motorola 's in teres t in this t echno logy

was the creat ion of a compl ian t substrate for the

deposi t ion of epitaxial, h igh dielectr ic cons tan t

oxide films on silicon for r andom access m e m o r y

devices, a c o n c e p t previously p roposed in 1991

by Cornell Professor, Y.H. Lo.

One of the keys to this type of hetero-epi taxy

and one of the processes deve loped by Motorola,

is the format ion dur ing g rowth of a th in sil icon

dioxide interlayer b e t w e e n the surface layer of

III-Vs REVIEW THE ADVANCED SEMICONDUCTOR MAGAZINE VOL~5 - NO 4" MAY 2oo2


silicon and the mechanica l suppor t silicon wafer

however, the 20A silicon dioxide layer originally

p r o d u c e d in the process was unsui table for

CMOS appl icat ions and has b e e n replaced by an

STO layer.This th in oxide can be e i the r amor-

p h o u s or crystalline, bu t it serves to take the

stress out of the surface silicon layer and allows

the g rowth of a low stress hetero-epitaxial layer

on the surface. In the case of s t ron t ium t i tanate

interlayers, the opt imised STO layers are

about 120 A thick, w i th the silicon dioxide inter-

layer th ickness r educed to 7 angstroms.

Following the depos i t ion of the STO layer, at

least 2000A of a gallium arsenide seed layer are

depos i ted to form the pseudo substrate, suitable

for gall ium arsenide device layer g rowth and pos-

sibly o the r III-V materials on silicon. Rather fortu-

itously, a th in silicon dioxide layer, w h i c h is com-

pl iant and forms b e t w e e n the silicon and the

STO layer.The STO has a stable cubic s t ruc ture

above 70 ° Kelvin and it allows the stresses, the

the rmal interlayer mismatches and the associated

cracking to be eliminated. It also creates the pos-

sibility for lattice engineer ing, w h i c h could be

the enab le r for n e w device structures. Currently,

only solid sources are used in this MBE deposi-

t ion process , requir ing h igh t empera tu re

Knudsen Cells to p roduce the vapour ised metals

and good cont ro l of the gas injection, creat ing a

chal lenge for solid source MBE technology.

For p rocess deve lopmen t , IQE used a Gen-2000

MBE reac to r w i t h a 7 x 6" wafer capaci ty and

separa te III-V and oxide depos i t ion c h a m b e r s

w h e r e the ox ide inter-layer and the seed galli-

u m arsen ide layer are g r o w n separately.Various

si l icon subs t ra te resist ivit ies have b e e n used

and 1 to lO ohm-cm mater ia l can make good

RF devices. However , t he h ighe r resist ivity

(1000 to 5000 ohm-cm) float zone si l icon sub-

strates may be pre fe rab le for h igh f r equency

devices, bu t they have no t yet b e e n evaluated.

Process uni formi t ies are good w i th the deposi t -

ed STO layer th icknesses and GaAs MESFET

across the wafer resist ivit ies exh ib i t ing b e t t e r

t han 1% uniformit ies .

To realize its low cost potential , a h igh volume

process and p roduc t is n e e d e d that could pro-

vide addit ional cus tomer feed back .The key fac-

tors to suppor t a manufac turab le process are

s tated to be minimal opera tor involvement , full

p rocess computer iza t ion , accurate cont ro l of

material beams and process pa ramete r s and a

need to keep device re-engineer ing for exist ing

>,

"0 #-

Blurring the boundaries for next generation "system on a chip"

• Optical • Large wafer capabilities sizes

• High speed • Low cost • High • Volume

frequency manufacturing

• High voltage

f Integrate the superior electrical and optical performance of III-V

semiconductors with the mature Silicon-based technology to create a

new industry of integrated

semiconductor circuits

i • Mature integration

capability • Memories • Microprocessors

Integration at the digital/electromagnetic (computation/communications) interface

O >

02

I

produc t s to a min imum.Accord ing to Thomas

Hierl, the CTO of IQE plc, the p rocess is produc-

t ion capable, bu t deve lopmen t volumes are need-

ed to cor robora te the initial data for repro-

ducibility, yields and costs .With suitable demand,

scale up to p roduc t ion volumes would be possi-

ble by Q1 2003.

With depos i t ion uniformit ies already similar to

those a t ta ined f rom gallium arsenide on gallium

arsenide processes (homo-epi taxy) , a ramp up to

commerc ia l volumes could be accompl i shed

wi th in one year.The target pr ice for the 6" galli-

u m arsenide on sil icon wafers is $200 for 6"

d iameter pseudo substrates versus a repor ted

pr ice of $300 for 6" gallium arsenide wafers

a l though pseudo-wafer costs in the deve lopmen t

phase are bel ieved to be in the $400 to $600

The best of both worlds

RF power Transistors

Today's Power Amplifier Transistors (made in silicon)

+ Limited RF Power

-- In~ufficiem Coverage A ~ a

NITRONEX GaN on Silicon

........... 6X to 15X Power

+ Heat+driven Operating (.'o,ts

• Ten, of Millions $US spent annual b

To Cool B a ~ $laliorls

. . . . . . . . . . . 2 X

Efficiency

+ St~lchcd Beyon+l Capahility

• Highest Fa i lu~ Rm¢ ol Any El~'trical

COl]iponel~t hi B['S

* Marginal Signal Qual i ly

Limited N~mix.t of U,crs

in Coventge Area

. . . . . 4X Robustness (up to 50V)

......... 3X Linearity

( w o u l d n o t n e e d s i d e b a n d s )

C O M P A R A T I V E P E R F O R M A N C E nitride power transistors and amplifiers can easily outperform silicon

III-Vs REVIEW THE ADVANCED SEM ICONDUCTOR MAGAZINE VOL 15 - NO 4" MAY 2002


32

-7.30 -7.25 -7.20 -7.15 qx (l/rim)

i i i 10°] tG°.,0002, 'q /

:~ I,r "1,'~_ SL+I

--E 10o~ SL'2 ~ , ~ d ~ l l t &

10.~ r ~ ~ simula, ti°n 30 32 34 36 38

20 (degree)

Reciprocal-space map around the GaN (20ff 4) reflection (left) and ( 9 - 2 0 scan (righO showing measurement and simulation. As can be clearly seen in the reciprocal space map the

superlattice (5L) peaks are slightly shifted in qx with respect to the main GaN reflection indicating a different a-lattice constant (vertical dashed line) but no relaxation (partial relaxation:

diagonal dashed line). The (9-2(9 scan shows, in addition to the superlattice peaks, Pendell~sungs fringes from the SL and the cap layer, indicating the high quality o f the

InGaN/GaN interfaces.

range. FETs have already b e e n demons t r a t ed

based on this process and it is n o w be ing

ex t ended to heterobipolar-devices .To p romo te

h igh interes t levels and par t ic ipa t ion in the i r

gallium arsenide o n silicon t echno logy and to

reduce deve l opm en t costs for in te res ted

parties, Motorola has agreed to allow in teres ted

compan ies to p r o c e e d w i th process develop-

men t work w i t hou t a l icense by using

non-disclosure agreements .

To speed up the progress of the gal l ium

arsen ide o n si l icon t e c h n o l o g y internally,

Motorola has fo rmed a whol ly o w n e d sub-

sidiary, T h o u g h t b e a m Inc., h e a d e d by Padmasree

Warr ior as Genera l Manager .Al though

T h o u g h t b e a m is an R&D opera t ion w i t h o u t a

fab, its goal is to c o m b i n e the bes t of the III-V

and the si l icon worlds. Using the MBE g r o w n

p s e u d o subs t ra tes and depos i t ing the active

device layers by MOCVD, Motorola has already

c o m p a r e d the p e r f o r m a n c e of the i r gal l ium

arsen ide on si l icon FETs w i th similar gal l ium

arsen ide based devices and s h o w n t h e m to have

similar charac ter i s t ics including, mobil i t ies, satu-

ra ted velocit ies, ga te /d ra in b r e a k d o w n voltages,

t r a n s c o n d u c t a n c e s and RF pe r fo rmance . MES-

FET p o w e r amplif iers based on this t e c h n o l o g y

w i t h equ iva len t p o w e r eff iciencies have already

b e e n evaluated in c e l l p h o n e handse t s in the

Chicago area and were found to be indistin-

guishable f rom those on gal l ium arsen ide

wafers. Future plans inc lude the tes t ing of HBTs

and lasers.

Gallium Nitride The potent ia l for gallium ni t r ide devices covers a

wide range of appl icat ion areas and includes

those listed below.

• Power condi t ion ing

• Wireless b roadband

• Pressure sensing

• Whi te solid-state l ighting

Weak-beam TEM images using (0001) and (1TO0)

reflection to view screw type (top left) and edge type (bottom left) dislocations, respec-

tively. In the TEM image the reduction of dislocation den-

sity due to the LT-AIN interlayers (C) and the 5i N in-situ

mask (B) can be clea~y seen. A denotes the

AIGaN:Mg/Sx(In GaN/GaN:Si) active region and D the AIN

seed layer CL linescans taken at 5 K for the same cross sec-

tion are plotted on the right side on the same scale. On

the top-right, a spectrum linescan is plotted depicting

the vertical evolution through the layer sandwich. On the bottom-right, intensity pro-

files are plotted for the n- GaN, p-GaN and InGaN

luminescence, respectively

360 380 400 420 440 460 480 5gO W a v e l m ~ (nm)

0.0 ..... "-~-L ....... ' . . . . . ' " " "

} . . . . . . . . . . . . . .

Ji

1# 1~ 1# CL ~ . n ~ t y (ar~ .~ts)

III-Vs REVIEW THE ADVANCED SEMICONDUCTOR MAGAZINE VOL t5 - NO 4" MAY 2002


• DVD storage

• Coloured signs & l ighting

• Automot ive l ighting

• Automotive e lec t ronics

• Power t ransmiss ion

• Heat sensing

• Flame sensing

• Te lecomm base stat ions

• Satellite e lec t ronics

LED lighting p roduc t s are well es tabl ished and

are a h igh grow rate appl icat ions category, w i th

blue and violet lasers be ing aggressively devel-

oped for h igh capaci ty DVDs, bu t the potent ia l

for e lec t ronic devices is yet to be realized.Two

key factors have con t r ibu ted to the slow intro-

duc t ion of n i t r ide devices and they are the h igh

defect levels i nhe ren t in mos t epitaxial ni t r ide

layers and the lack of bulk substra tes for h o m o

epi taxy.These necess i ta te the use of hetero-sub-

strates, such as sapphi re and sil icon carbide.

In many instances, mili tary need and perform-

ance have dr iven the d e v e l o p m e n t of n e w com-

p o u n d semiconduc to r materials, p rocesses and

devices bu t cost has dr iven process deve l opm en t

for the h igher volume p roduc t s (as in silicon

devices). However, a c o m p a n y called Ni t ronex

plans to s imultaneously com bi ne the advanced

hetero-subst ra te g rowth technologies and the

ant ic ipa ted lower cost features i nhe ren t in galli-

u m ni t r ide on silicon in the i r SIGANTIC process ,

to create a ' revolut ionary potent ia l ' for the i r

n i t r ide on silicon technology, w i th an initial goal

of $60 for a 60W chip.

Ni t ronex has l icensed Nor th Carolina State

Universi ty pa ten t s cover ing the depos i t ion of gag

l ium ni t r ide on silicon, a p rocess they are devel-

op ing for the commerc ia l p roduc t ion of b o t h

e lec t ronic and op toe lec t ron ic gallium ni t r ide

devices. Originally, the focus was r epo r t ed to be

the use of a pendeo-ep i taxy processes , bu t after

rev iewing the key patents , the adopt ion of a sili-

con carbide interlayer p rocess ( b e t w e e n the sili-

con and the gallium ni t r ide layer) seems to be

more appropr ia te than the incorpora t ion of pen-

deo technology.

In the Ni t ronex processes , an u p p e r sil icon layer

(wi th a prefer red 111 or ientat ion) , [selected

from e i ther a bulk silicon, a sil icon on insula tor

(SOI) or a silicon over implan ted oxygen

(SIMOX) wafer substrate] is conve r t ed at a h igh

t empera tu re into a 3C-silicon carbide layer by

t rea tment w i th a ca rbon conta in ing p recurso r

gas such as e thylene.As an alternative, silicon

1.2 . . . . . . . . . i . . . . . . . . . , . . . . . . . . . i . . . . . . . . . l . . . . . . . . n-GaN l u m i n e s c e n c e

1 . 0

~ 0.8

,{ 0,6

~c 0.4

~i 0.2

0.0 0 . 0 0.5 1.0 1.5 2.0

D e p t h ( l~m)

A

~ 1 0 5

~ 10 '

d

. . . . . . . . . i . . . . . . . . . i . . . . . . . . . i . . . .

1 0 3 ,i . . . . . . . . + . . . . . . . . . i . . . . . . . . . , . . . .

0.0 0.4 0,8 1.2

Depth (vm)

carbide can also be directly depos i ted on the sift-

con wafers. If not, the carbide seed layer may

then be th i ckened by the fu r ther chemical

vapour deposi t ion g rowth of addit ional silicon

carbide+After a pol ishing step to smoo th out the

depos i ted silicon carbide, a thin, low tempera-

ture buffer layer (in the range of 50 totOOnm

thick) of e i ther a luminium or gallium ni t r ide is

usually grown. It is on this buffer layer that the

device layers of 2H-gallium ni t r ide and its alloys

are usually depos i t ed wi th the bes t defect levels

achieved be ing in the 10E6 pe r cm 2 range .The

use of substrates wi th the oxide interlayers

may also provide the added benef i t of a compli-

ant substrate, w h e r e stress relief is ob ta ined by

slippage b e t w e e n the sil icon and its adjacent

oxide layer.

Masking layers or t r enches can be added pr io r to

the last g rowth step in w h i c h case, device quality

lateral epitaxial over g rowth (LEO) or pendeo-

epitaxial layers of 2H-gallium ni t r ide can be pro-

duced. Such layers may have lower defect levels

over the masked areas than those ob ta ined by

direct g rowth on the seed layers.Additionally, it is

envisaged that sect ions of the sil icon wafer may

be capped off so that they are no t conve r t ed to

carbide or gallium ni t r ide layers.After removal of

the cap, they could t h e n be used to grow silicon

devices (or even expose silicon devices already

CL linescans from the top of the diode structure to the substrate of the two LED samples, with and without a 5i N interlayer, showing the

x y

n-GaN (left) and lnGaN luminescence (right). A strong enhancement in CL intensity is observed for the n-GaN luminescence after each LT- AIN interlayer, which are located at the two minima around 1 and 1.7 pm. A strong enhancement of the InGaN luminescence by the 5i N interlayer is also

x y

observed. This is due to a better InGaN quafity and a better carrier diffusion clearly indicated by the prolonged tail o f the InGaN luminescence for the sample with 5ixNy mask,

300 • , , i , , , [ , , , i , • , i , , , i

J ~ ~ . . . . . . . . . . . '

}.1 / / o =~

0 10 20 30 40 ,50 Current (mA)

I-V characteristics o f a verti- cally contacted light emitting diode grown on Si substrate (inset) and power vs. current o f an LED (360 pm diameter) mounted on an - 1 mm 2 die in an epoxy LED dome. At 35 mA Ohmic heat- ing starts to significantly reduce device performance. The peak wavelength is around 455 nm.

III-Vs REVIEW THE ADVANCED SEMICONDUCTOR MAGAZINE VOL 15 - NO 4 " MAY 2002

I e~ D i i S t R Y F O ( I I i 5 Compound Semiconductors on Sil icon

34

FET performances, with ft of 11GHz and fmax of 17GHz

were not as good as expected

prepared) , creat ing the potent ia l for b o t h sil icon

and gallium nitr ide devices on the same chip.

According to J o h n Brewer, Jr. Vice President,

Marketing at Nitronex, the i r first gallium ni t r ide

p roduc t target is the t e l ecommunica t ions base

station, w h e r e ni t r ide p o w e r transistors and

amplifiers (wi th the capabili t ies for h igher

p o w e r levels, h ighe r efficiencies [40 to 60%],

h igher opera t ing voltages and the ability to oper-

ate at h igher junc t ion t empera tu res ) can easily

out pe r fo rm the sil icon LDMOS present ly in use.

This is qui te a large market w h e r e the n u m b e r of

t ransmi t / rece ive circuit boards are expec t ed to

increase f rom about 7 mill ion last year to over 15

million in 2004 and the i r co r r e spond ing value to

increase f rom almost $600 million to $1.25 bil-

l ion in the same per iod.This value represents

over 25 mill ion p o w e r amplifiers. Only the lack

of reliability data and pe r haps design accep tance

should s tand in the i r way.To mee t these goals,

the Ni t ronex strategy is for cross-industry part-

ne rsh ips ra ther than a cont ro l of the market, and

therefore the Company has coopera t ive process

deve l opm en t agreements available for pa r tne r s

in te res ted in these and o the r nitride-on-silicon

based applications.

There are several reasons for this oppor tuni ty ,

first the si l icon circuits are no t very p o w e r effi-

c ient (more t han 80% of the p o w e r is d iss ipated

as heat) , second, a h igh air cond i t ion ing cost in

the region of $10 mil l ion pe r system for remov-

ing this hea t and third, a relatively shor t operat-

ing lifetime (6 to 9 m o n t h s ) for the sil icon

p o w e r amplif iers due to the i r h igh junc t ion

opera t ing t e m p e r a t u r e s . A n o t h e r incent ive for

the adop t ion of gallium ni t r ide amplif iers is

the i r super ior linearity, w h i c h would al low clos-

er spacing of user channels , less side b a n d allo-

ca t ion and more users p e r exist ing base station.

The system d e m a n d s f rom th i rd genera t ion

! 120

100

80

60

40

0

UGs=1.5V

z~U~=-O.~

U~=-3V

2 4 6 8 10 12 U~[V]

GaN/AIGaN FET on Si, Uni-UIm, Otto-von-Guedcke Universi~t Magdeburg

mobi le handse t s could drive the inser t ion of gal-

l ium ni t r ide devices in the 2003 /2004 t ime

frame for reasons of efficiency, l inearity and

h igher opera t ing voltages.

As repor ted in the previous issue of III-Vs

Review, (Vol. 15 page 40), a University of

Magdeburg research group a round Alois Krost is

also developing gallium ni t r ide o n silicon device

processes and p resen ted its results on the devel-

o p m e n t of the i r III-nitride-on-silicon process at

the recen t Materials Research Society Meet ing in

Boston.The Magdeburg processes use e i ther

masking or superlat t ice inter-layers to p repa re

the sil icon for acceptable ni t r ide growth. Process

deve lopmen t has evolved to w h e r e gallium

ni t r ide blue LEDs have already b e e n demonstra t -

ed on ni t r ide layers depos i ted on silicon wafers

g rown by the NCSU and the Magdeburg devel-

oped processes.

Additional progress has b e e n made and in a pri-

vate communica t ion ,Armin Dadgar f rom the

Universi ty of Magdeburg repor ted on a coopera-

tive effort w i t h Global Light Indistries (GLI) in

Germany, w h e r e Markus Kamp et al manufac-

tered blue and green LEDs employing buffer

s t ruc tures p repa red in Magdeburg .The active

LED s t ruc ture has b e e n g rown by Andreas

Kaluza's MOCVD group using p lane tary reactors.

Processing and packing used s tandard GLI

processes. See the p h o t o g r a p h of these packaged

ni t r ide on sil icon LEDs opera t ing at a 20mA drive

current.I-V character is t ics of the f ront con tac ted

diodes were as good as those GaN/sapphi re

LEDs, giving opera t ion voltages a round 3.1V at

20mA current .

Even t h o u g h the I-V character is t ics for front-con-

tac ted LEDs on sil icon and sapphi re were identi-

cal, the ou tpu t p o w e r of the planetary-grown

LEDs on sil icon was lower (approximate ly

0 .2mW at 4 9 0 n m and 0 .4mW at 498nm) than for

those g rown on sapphire. However, ne i the r epi-

taxial g rowth no r process ing has b e e n adjusted

to the different substrate. Fur ther improvemen t s

in ou tpu t p o w e r are expec t ed f rom the removal

of the absorb ing Si substrate. It is wor thy of no te

that the in situ inser t ion of a silicon ni t r ide mask

(wh ich has b e e n used to lower the defect densi-

ties on sapphi re and silicon) significantly

increased the optical ou tpu t p o w e r and that all

the LEDs g r o w n on silicon are red-shifted by 20

to 40nm, w h e n compared w i th LEDs g rown on

sapphire .This factor makes a direct compar i son

of the diodes difficult .The shift is p r e sumed to

III-Vs REVIEW THE ADVANCED SEMICONDUCTOR MAGAZINE VOLt5 - NO4- MAY 2oo2

C o m p o u n d S e m i c o n d u c t o r s on Si l icon I I ~ i D t i S i t t~ i O ( i O S

Global Light Industries LEDs

be due to the p re sence of tensi le stress on sill-

con versus compress ive stress on sapphire.

Transmission e lec t ron mic roscopy analyses on

cross sect ions of these LED s t ruc tures have n o w

b e e n pe r fo rmed by O. Contreras and F.A. Ponce

f rom Arizona State University.The dual ahmlini-

u m ni t r ide in ter layers and o the r s tructural layers

in this gallium ni t r ide o n sil icon system are clear-

ly visible, t oge the r w i th the differing levels of

defects c rea ted as the s t ruc ture was be ing

grown. Note also the ca thode luminescence line

scan intensi ty data and a layer m ap for the same

structural cross sec t ions .These were de t e rmined

by T. Riemann and J. Chr is ten f rom Magdeburg.

An increase in luminescence intensi ty is

ob ta ined after each ah imin ium ni t r ide layer is

inserted.

In coopera t ive research w i th the Universi ty of

Ulm and ex tend ing the process to e lec t ronic

devices, the first gallium ni t r ide FETs on sil icon

have n o w b e e n made .The undopedA1GaN/GaN

FET devices exhib i ted good two-dimensional

e lec t ron gas results w i th mobil i t ies of 1590

cmz/Vs at reasonably h igh carr ier concen t ra t ions

(6.7E12 p e r cm2).The FET per formances , w i th ft

of l l G H z and fmax of 17GHz were not as good

as expec t ed and were a t t r ibuted to sub-layer par-

asitic currents . Future modif icat ions of the

g rowth process are p l anned and should improve

the pe r fo rmance of these FETs.

The g r o w t h of c o m p o u n d s e m i c o n d u c t o r s on

si l icon is n o w a revis i ted topic of in te res t and

in some ins tances be l ieved to be in the a lmost

c o m m e r c i a l category.At the r e c e n t G o r h a m

confe rence , C o m p o u n d S e m i c o n d u c t o r Out look

2002, the g r o w t h of c o m p o u n d mater ia ls o n sil-

i con was offered as a one-day tutor ia l session.

For those in te res t ed in e i the r gal l ium arsen ide

or gal l ium ni t r ide o n si l icon p r oce s s technolo-

gy, the tutor ia l was a w o r t h w h i l e feature and a

relatively painless way to ca tch up w i t h the

w a v e . T h e po ten t i a l marke t for these p rocesses

was wel l d o c u m e n t e d and m a n y o p p o r t u n i t i e s

we re explored , bu t little in fo rmat ion was

offered a b o u t the c u r r e n t p roces s costs,

e x c e p t for the 3x es t imate for gal l ium arsen ide

p s e u d o wafers r e p o r t e d by Thomas Hierl f rom

IQE (at the i r p r e sen t state of deve lopmen t ) .

Volume p r o d u c t i o n is e x p e c t e d to b r ing these

p s e u d o subs t ra tes in to c o m p e t i t i o n w i t h those

available today. W h e n successful, g r o w t h on

silicon could offer an agility to swi tch f rom one

materials business mode l to another.Additionally,

the re may be an incent ive for the te lecommuni-

cat ions providors to suppor t these and o the r

c o m p o u n d solutions for b a n d w i d t h expansion,

s ince voice provides mos t of the i r income, bu t

data is n o w the largest c o n s u m e r of the available

b a n d w i d t h capacity.

Custom Epitaxial Solutions QinetiQ offers custom

epitaxial growth and characterisation solutions for

today's fast-changing environment. We can

supply epitaxial layers to stringent specifications, and

offer layer design and device fabrication if required.

• Custom wafer growth with no minimum order

• High quality, with 20 years of expertise behind us

• Full in-house characterisation (SIMS, X-ray, CV, Hall, PL)

• GaAs/AIGaAs, InP-based, InSb/InAISb, GaN/AIGaN, CdTe/HgCdTe, SiGe, dilute nitrides

• MBE, CBE and MOCVD

• Custom device fabrication and assessment

• Layer design and modelling

Tel. +44 1684 895365 Fax. +44 1684 896938 [email protected] www.electro-optics.co.uk

QinetiQ was formerly DERA, the UK's

Defence Evaluation and Research Agency

QinetiQ St. Andrews Road, Malvem, UK

RES No.115 - USE THE FAST NEW ENQUIRY SERVICE @ www.three-fives.com

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Compound semiconductors on silicon