Combinational Gate Design

8/12/2019 Combinational Gate Design

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CMOS Combinational Gate Design

(Chapter 9)

Bharadwaj AmruturECE Dept !!S" Bangalore #$


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2

Compound gates


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3

Compound %ersus Simple Gates

Using Simple Gates:G =P =


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4

Compound %ersus Simple Gates

Using Simple Gates:

G = 5/3 * 4/3 * 5/3 = 100/27 = 3.7P = 2 + 1 + 2 + 1 + 2 = 8Delay = 3.7 * + 8

!"# $"mp"%n& Gate

Delay = 2.7 + 5.4


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5

!nput Order

Cal"ulate parasiti" dela& 'or 'alling

!' A arri*es last+ !' B arri*es last+

6C

2C22

22

BA x

Y


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'

!nput Order

Cal"ulate parasiti" dela& 'or 'alling

!' A arri*es last+, B-#-.node / is alread& at 01 So dis"harge

time"onstant o' - (2 3 2) 4 5C - 5C

!' B arri*es last+, A-#-. node / is %dd6%t1 Both / and & ha*e to be

dis"harged -. time"onstant - 2 ($C35C) 3 2 (5C) -7C1

6C

2C2

2

22

B

A

x

Y


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!nner 8 Outer !nputs

!' input arri*al time is nown, Conne"t latest input to inner terminal

2

2

22

B

A

Y


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S&mmetri" Gates

!nputs "an be made per'e"tl& s&mmetri"

A

B

Y

2

1

1

2

1

1

6C

2C2

2

22

B

A

x

Y


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As&mmetri" Gates

As&mmetri" gates 'a*or one

input o*er another E/: suppose input A o' a ;A;D

gate is most "riti"al 9

gB- $

As&mmetri" gate approa"hes g- # on "riti"al in ut when other


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?igh Speed Digital Cir"uit Design

@otal e''ort - G B ?

?igh speed -. lower

? and B are ultimatel& determined b& mi"ro6ar"hite"ture

G is determined b& logi" and "ir"uit design

, Choose low G gates

, Change "ir"uit topolog& to redu"e G 'or a gi*engate1 ?ow+

d G


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Sewed Gates

Sewed gates 'a*or one edge o*er another

E/: suppose rising output o' in*erter is most "riti"al Downsi=e non"riti"al nMOS transistor

Cal"ulate logi"al e''ort b& "omparing to unsewed in*erter withsame e''e"ti*e resistan"e on that edge1 gu-

gd-

1/2

2A Y

1

2A Y

1/2

1A Y

HI-skew

inverter

unskewed inverter

(equal rise resistance)

unskewed inverter

(equal fall resistance)


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12

Sewed Gates

Sewed gates 'a*or one edge o*er another

E/: suppose rising output o' in*erter is most "riti"al Downsi=e non"riti"al nMOS transistor

Cal"ulate logi"al e''ort b& "omparing to unsewed in*erter withsame e''e"ti*e resistan"e on that edge1 gu- $1> - >5

gd- $1>#1 - >

1/2

2A Y

1

2A Y

1/2

1A Y

HI-skew

inverter

unskewed inverter

(equal rise resistance)

unskewed inverter

(equal fall resistance)


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13

?!6 and O6Sew

De': ogi"al e''ort o' a sewed gate 'or a parti"ular

transition is: the ratio o' the input "apa"itan"e o' that gate to

the input "apa"itan"e o' an unsewed in*erter

deli*ering the same output "urrent 'or the same

transition1

Sewed gates redu"e si=e o' non"riti"al transistors

?!6sew gates 'a*or rising output (small nMOS)

O6sew gates 'a*or 'alling output (small pMOS)

ogi"al e''ort is smaller 'or 'a*ored dire"tion

But larger 'or the other dire"tion

l '


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14

Catalog o' Sewed Gates

1/2

2A Y

Inverter

1

1

22

B

AY B

A

A!2 "#2

1/21/2

$

$

HI-skew

%"-skew1

1A Y

2

2

11

B

A Y

B

A

11

2

2

&u ' /6

&d ' /

&av&

' /$

&u ' $/

&d ' 2/

&av&

' 1

&u ' 1

&d ' 2

&av&

' /2

&u ' 2

&d ' 1

&av&

' /2

&u ' /2

&d '

&av&

' */$

&u ' 2

&d ' 1

&av&

' /2

Y

Y

1

2A Y

2

2

22

B

AY

B

A

11

$

$

unskewed&u ' 1

&d ' 1

&av&

' 1

&u ' $/

&d ' $/

&av&

' $/

&u ' /

&d ' /

&av&

' /

Y


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15

As&mmetri" Sew

Combine as&mmetri" and sewed gates

, Downsi=e non"riti"al transistor on unimportant input, edu"es parasiti" dela& 'or "riti"al input

A

reset

Y

$

$/

21

reset

A

Y


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seudo6nMOS !n the old da&s nMOS pro"esses had no pMOS

!nstead use pull6up transistor that is alwa&s O;

!n CMOS use a pMOS that is alwa&s O; Eatioissue

Mae pMOS about H e''e"ti*e strength o' pulldownnetwor

+,ut

+in

16/2

/2

Ids

l,ad

. . .6 .* 12 1 10

.

.

.6

.*

12

1

10

' 2$

' $

' 1$

+in

+,ut


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seudo6nMOS ower

seudo6nMOS draws power whene*er - 0

Called stati" power - !%DD A 'ew mA > gate 4 #M gates would be a problem

@his is wh& nMOS went e/tin"tI

But re6e/amine in "onte/t o' high subthreshold leaage1


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D&nami" ogi"

D&nami"gates uses a "lo"ed pMOS pullup

@wo modes: pre"hargeand e*aluate

1

2A Y

$/)

2/)

A

Y

1

1

A

Y

tatic seud,-n3" !4na5ic

recar&e 7valuate

Y

recar&e

@h t


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@he ooter Jhat i' pulldown networ is O; during pre"harge+


22/25

ogi"al E''ort

Inverter A!2 "#2

1

1

AY

2

2

1

B

AY

A B 11

1

&d ' 1/)

d ' 2/)

&d ' 2/)

d ' )/)

&d ' 1/)

d ' )/)

Y

2

1

AY

)

)

1

B

AY

A B 22

1

&d ' 2/)

d ' )/)

&d ' )/)

d ' $/)

&d ' 2/)

d ' (/)

Y

f,,ted

unf,,ted

)2 2

M t i it


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Monotoni"it& D&nami" gates reKuire monotoni"all& risinginputs during

e*aluation

0 6. 0 0 6. #

# 6. #

But not # 6. 0

recar&e 7valuate

Y

recar&e

A

"utut s,uld rise 8ut d,es n,t

vi,lates 5,n,t,nicit4

durin& evaluati,n

A


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Monotoni"it& !ssues

But d&nami" gates produ"e monotoni"all& 'alling

outputs during e*aluation !llegal 'or one d&nami" gate to dri*e anotherI

A9

Y

recar&e 7valuate

9

recar&e

A ' 1

Y s,uld rise 8ut cann,t

Y

9 5,n,t,nicall4 falls durin& evaluati,n


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Documents

Combinational Gate Design