Lecture05-2005 Combinational Design

8/19/2019 Lecture05-2005 Combinational Design

1/78

Lecture 5 Combination Logic

Design

Pradondet Nilagupta

[email protected]

Department of Computer Engineering

Kasetsart University


2/78

#

Acknowledgement

'his lecture note has (een summari)ed fromlecture note on *ntroduction to +,-* Design"

+,-* Circuit Design all over the orld. * can/t

remem(er here those slide come from.0oever" */d like to thank all professors ho

create such a good ork on those lecture

notes. 1ithout those lectures" this slide can/t

(e finished.


3/78

2

Topics

Com(inational logic functions.-tatic complementary logic gate structures.


4/78

%

Combinational logic expressions

Com(inational logic3 function value is acom(ination of function arguments.

& logic gate implements a particular logic

function.4oth specification 5logic e6uations7 and

implementation 5logic gate netorks7 are

ritten in 4oolean logic.


5/78

8

Gate design

1hy designing gates for logic functions is non9trivial3may not have logic gates in the li(ray for all logic

e:pressions;a logic e:pression may map into gates that

consume a lot of area" delay" or poer.


6/78

!

Boolean algebra terminology

a(/

a is a varia(le; a and a/ are literals.

a(/ is a term. & function is irredundant if no literal can (e

removed ithout changing its truth value.


7/78?

Irredundancy

& logical e:pression is irredundant if no literalcan (e removed from the e:pression ithout

changings its value

edundant e:pressions3a*b + a

a*b + a*b'

*rredundant e:pressions3

a*b' + a'*b

a + c*d'


8/78A

Completeness

& set of logical functions is complete iif ecan generate every possi(le 4oolean function

using that set

'he set B &ND" " N' is complete'he set B N&ND is complete

'he set B &ND" is not complete

'ransmission gates are not complete.

*f your set of logic gates is not complete" you

can/t design ar(itrary logic.


9/78

Minimality

& logic e:pression is minimal if no e6uivalentform has a higher cost 5i.e." literal count7

Minimality F *rredundancy

C&D tools are availa(le to find the minimal5or near9minimal7 form for3'o level logic 5&NDG -um of Products7

Multilevel ,ogic 5&r(itrary netork of gates7


10/78$

Static complementary gates

Complementary3 have complementary pullup5p9type7 and pulldon 5n9type7 netorks.

-tatic3 do not rely on stored charge.

-imple" effective" relia(le; hence u(i6uitous.


11/78

Static complementary gatestructure

VDD

Out

Gnd

VDD

Out

Gnd

PullupNetwork

(p-transistors)

PulldownNetwork

(n-transistors)

InInputs

Inverter

Pullup Netork 9 drives output to +DD Pulldon Netork 9 drives output to HND


12/78#

Inverter layout

(tubs not

shown)a out

+

transistors

GND

VDD

a out

tub ties


13/782

Complementary CMOS otes

Pullup" pulldon netorksshould NE+E conduct at

same timeI

Pullup" pulldon netorks are

duals

Parallel in pulldon impliesserial in pullup

-erial in pulldon implies

parallel in pullup

Hate 'ypes3

-imple3 N&ND" N"inverter

&nd9r9*nvert 5&*7

r9&nd9*nvert 5&*7

A

A

B

C

B C

OUT = (A*(B+C))’


14/78%

!ayout Considerations

Metal lines re6uired for +ddI" HndI ndiff" pdiff must (e separated (y $ lam(da

'ransistor options3hori)ontal or vertical diffusion lines-tart ith minimum9si)e transistors

*ncreased idth implies increased driving capa(ilitiy"

(ut

Do the analysis first to see if it/s necessary


15/788

!ayout Considerations "cont#d$

*nterconnect layers 5use vias hennecessary73Metal

Metal #Poly

Diffusion

-pecify a ell depending on process typeUse su(strate contacts to prevent latchup


16/78!

A% gate

+

ba

out


17/78?

A% layout

+

ba

out

b

a

out

VDD

GND

tub

ties


18/78A

!ayout &xample ' A%

Compare to


19/78

O( gate

+

b

a

out


20/78#$

O( layout

b

a

out

a

b

out

VDD

GND

tub ties


21/78#

!ayout &xample ' O(

Compare to


22/78##

!ayout ' Creating )ideTransistors

Divide into multiple transistors 'ie together sources" drains

Compare to


23/78#2

AOI*OAI gates

&* = andGorGinvert; &* = orGandGinvert. *mplement larger functions.

Pullup and pulldon netorks are compact3

smaller area" higher speed than N&NDGNnetork e6uivalents.

&*2#3 and 2 inputs" and input 5dummy7"

and # inputs; or together these terms; theninvert.


24/78#%

AOI example

out = Ja(>c/3

symbol circuit

and

or

invert


25/78

#8

+ullup*pulldown network design

Pullup and pulldon netorks are duals. 'o design one gate" first design one netork"

then compute dual to get other netork.

E:ample3 design netork hich pulls donhen output should (e $" then find dual to get

pullup netork.


26/78

#!

%ual network construction

d u m m y

a

b c

dummy

a

b c


27/78

#?

Inverter ' %C Analysis

in out

Vout

Vin1 2 3 4 5

1

2

3

4

5

NMOS linPMOS off

NMOS sat

PMOS sat

NMOS off

PMOS lin

NMOS satPMOS lin

NMOS lin

PMOS sat

A

B

C

D

E


28/78

#A

Inverter %C Analysis ' Continued

A Vout = VDD

Vout = Vin − Vtn )− Vin − Vtn )2−

βp

βn

Vin − VDD − vtp)2D

E Vout = 0

B Vout = Vin − Vtp)− Vin − Vtp)2− 2 Vin −

VDD

2− Vtp

VDD −βn

βp

Vin − v tn 2

C Vout =VDD

2

Source: N. Weste & . !shra"hian# Principles of CMOS VLSI Design $ddison Wesley# %'

Note dependence on n/βpRecall: βn = k n

' Wn

Ln

βp = k p' Wp

Lp


29/78

#

!ogic !evels, Output

,ogic values are represented (y a range ofvoltages,ogic 3 (eteen +C0 and +DD 58+7

,ogic $3 (eteen +C, and +-- 5$+7-tatic CM- utput levels +C0 = +DD 58+7

+C, = +-- = Hnd 5$+7


30/78

2$

!ogic !evels, Input

E:amine DC *nputGutput Curve 5


31/78

2

!ogic !evels ' Summary

"1"

"0"

VOH

VH

V!

VO!

Undefined Region

V()

V(y)

V

*

V

V,*

V,

Slo-e /%

Slo-e /%


32/78

2#

oise Margin

& measure of noise immunity,ogic 3 NM0 = +C0 9 +*0

,ogic $3 NM, = +C, 9 +*,

*mportant hen noise is presentDefinition3 small random variations in voltage

Don/t ant noise to affect circuit output


33/78

22

Vin

Vout

βnβp

= 1

βnβp

= 10

βnβp

= 0.1

Transistor Si-ing and oiseMargin

Changing (eta 5si)e7ratio changes +*0" +*,

'o (alance noise

margin3 Make βn=βp = 1p=2.81n &ctually" 1p=#1n is often

good enoughO


34/78

2%

Gate %elay

Consider an inverter ith step function inputDelay related to time to discharge G charge

C,

RL

CL

in

t


35/78

28

Simpli.ying Assumptions

&ssume transistors turn onGoffinstantaneously

Model transistor as a sitch" resistor in series

esistor appro:imates +dsG*d at different values of+ds

5-ee


36/78

2!

%elay Calculation ' /inding (n

Rn= V sat

I sat

+ V lin I

lin

/ 2 EQ 3 − 1

I sat = 1

2′k W L

V DD − V SS − V t ( )

2

V sa t

= V DD

− V SS

V lin

= V DD

− V SS

− V t ( ) / 2

I lin = ′kW

L12

V DD − V SS −V t ( )2 − 12

V DD −

V SS −

V t

2

2

=3

8′kW

LV

DD− V

SS − V

t ( )2


37/78

2?


Rn= V

sa t

I sa t

+ V

lin

I lin

/ 2

= V

DD −V

SS

1

2′kW

LV DD

− V SS − V

t ( )2

+ V

DD − V

SS − V

t

( ) / 238

′kW

LV DD

− V SS

−V t

( )2

/ 2

Rn = L

W

5

3V DD

− 5

3V

SS −

2

3V

t

k ' V DD

− V SS

− V t ( )

2

Table 3-1, p. 125 (0.5µm process, VDD=5V)

Rn = 3.9kΩRp = 14kΩ


38/78


39/78

2

/all Time Approximation

Capacitor initially charged at +DD 'ransistor appro:. n


40/78

%$

(ise Time Approximation

Capacitor initially discharged 5at +ss7 'ransistor appro:. p


41/78

%

Gate %elay Accuracy

Comparison to -pice simulation3


42/78

%#

Gate %elay o. A% Gate

Pulldon3 series n9transistorstf = #.# R 5# R n7 R C,

Pullup3 parallel p9transistors

5orst case hen one on7tr = #.# R p R C,

Rn CL

VOUT

Rn


43/78


44/78


45/78

%8

Gate %elay ' %e.initions

Vin

Vout

tpH!

50

50

tp!H

50

50

t#

$0

10

tf

Delay: time to reach 50% of final value tpHL (book calls this td)

tpLHTransition Time: time between 10% and 90%: tf - fall time

tr - rise time


46/78

%!

Simpli.ying Assumptions

&ssume -tep


47/78

%?


Rn = VsatIsat

+ VlinIlin

/2 EQ 3−1

Isat = 12k n' W

LVDD − VSS − Vt( )2

Vsat = VDD − VSS

Vlin = VDD −VSS −Vt( ) /2

Ilin = ′knW

L

1

2 VDD −VSS −Vt( )

2

−1

2

VDD −VSS −Vt2

2

= 38

′knW

LVDD −VSS −Vt( )

2


48/78

%A


Rn = VsatIsat

+ VlinIlin

/2

=

VDD − VSS1

2′kn

W

LVDD − VSS − Vt( )

2 +

VDD − VSS − Vt( ) /23

8′kn

W

LVDD − VSS − Vt( )

2

/2

Rn =L

W

5

3

VDD −5

3

VSS −2

3

Vt

′kn VDD −VSS −Vt( )2


49/78

%

%elay Calculation ' /inding (p

Rp = VsatIsat

+ VlinIlin

/2 EQ 3−1

Isat = − 12 ′kp WL VSS − VDD − Vt( )2

Vsat = VSS − VDD

Vlin = VSS −VDD −Vt( ) /2

Ilin = − ′kpW

L

1

2 VSS −VDD −Vt( )

2

−1

2

VSS

−VDD

−Vt

2

2

= − 38

′kpW

LVSS −VDD −Vt( )

2


50/78

8$

%elay Calculation ' /inding (p

Rp = Vsat

Isat+ Vlin

Ilin

/2

= VSS − VDD− 1

2′k W

LVSS − VDD − Vt( )

2+ VSS − VDD − Vt( ) /2− 3

8′k W

LVSS − VDD − Vt( )

2

/2

Rp = LW

5

3VSS −

5

3 VDD −

2

3Vt

−k' VSS −VDD −Vt( )2


51/78

8

Summary, Calculating (n and (p

Rp

= L

W

− 53

VDD −2

3Vt

− ′kp −VDD −Vt( )2

Rn =L

W

5

3VDD −

2

3Vt

′kn VDD −Vt( )2

&ssume +--=$ to simplify3


52/78

8#

&xample, Calculating (n

Rn = LW

5

3V

DD

− 2

3V

t

′kn VDD − Vt( )2

= 23

5

3(5V)− 2

3(0.7V)

′kn 5V− 0.7V( )2

=14KΩ

Use values from (ook3VDD = 5V

Vt = 0.7V

′kn = 73µA/V2

L = 2λ

W = 3λ


53/78

82

&xample, Calculating (p

Rp = LW

− 5

3

VDD −2

3

Vt

− ′kp −VDD −Vt( )2

= 23

− 5

3

(5V)− 2

3

(−0.8V)

−(21µA/V2 ) −5V− (−0.8V)( )2

=14KΩ

Use values from (ook3VDD = 5V

Vt = −0.8V

′kp = 21µA/V2

L = 2λ

W = 3λ

Summary, ( and ( .or


54/78

8%

Summary, (n and (p .orMinimum'Si-ed Transistors

type VDD=5V VDD=3.3V

Rn

3.9KΩ 6.8KΩ

Rp 14KΩ 25KΩ

Table 3-1, p. 130


55/78

88

Inverter %elay wit0 t0e τ model

Rising Input / Falling Output

Vout(t)= VDDe−t

(Rn+RL )CL EQ 3− 6

CL

Rp

Rn

RL0.5VDD = VDDe−tpHL

(Rn+RL )CL EQ 3− 7*

tpHL = −(Rn +RL )CL ln(0.5)= 0.69(Rn +RL )CL EQ 3− 8

tf = t10% − t90% = (Rn +RL )ln0.1

0.9

= 2.2(Rn +RL )CL EQ 3− 9

VDD

tt10%t90%


56/78

A% Gate %elay wit0 t0e


57/78

8?

A% Gate %elay wit0 t0e τ Model

CL

Rp

Rn

RL

Rp

Rn

,7C,

ise time3 p9transistor on5for orst case7

tf = #R#.#5n>,7C,


58/78

8A

O( Gate %elay wit0 t0e τ Model

,7C,

ise time3 p9transistor in series

tf = #R#.#5n>,7C,

Rp

Rp

Rn Rn


59/78

8

AOI Gate %elay wit0 t0e τ Model

,7C,

ise time3 2 p9transistors in series5orst case7

tf = 2R#.#5n>,7C, CL

RL

A

B

C

D

A

B

D

C

%elay &stimation ' Ot0er


60/78

!$

%elay &stimation ' Ot0erApproac0es

Current source model 9 treat transistor as current sourcein saturation


61/78

!

Accuracy o. met0ods

Comparison to -pice simulation3


62/78

!#

&xample ' Inverter %elay

Estimate tr and tf for a minimum9si)e inverter driving theinputs of four minimum9si)e inverters

5assume loading only from transistor gates7

IN OUT

CL

CINV

CINV

CINV

CINV

Cgp

Cgn


63/78

!2

0"-

0"n

0,NV

0

&xample ' Inverter %elay "1*2$

Estimate loading from a single inverter3

CINV

Cgp

Cgn

2λ ×0.25µm/ λ( )× 3λ ×0.25µm/ λ( )×0.9fF/ µm2

= 0.3375fF

2λ ×0.25µm/ λ( )× 3λ ×0.25µm/ λ( )×0.9fF/ µm2

= 0.3375fF

Cgn +Cgp = 0.3375fF+0.3375fF

= 0.675fF

4×Cinv = 4×0.675fF = 2.7fF


64/78

!%

tr

t1

&xample ' Inverter %elay "2*2$

No use n" p" C, to calculate tr " tf

2.2×Rn ×CL

= 2.2× 3.9KΩ×2.7×10−15 F

= 23. 1ps

2.2×Rp ×CL

= 2.2×14KΩ×2.7×10−15 F

= 83. 1ps

&xample ' Gate %elay o. an AOI


65/78

!8

&xample Gate %elay o. an AOIGate

Use values in (ook for +DD=8+ise time tr 31orst case3 # transistors in series


66/78

!!

&..ect o. Increased Transistor)idt0

*ncrease idth of transistor to3 *ncrease current

educe effective resistance 5n or p7

-ide9effect3 increased input capacitance

5more a(out this later7

Rn(WNEW) = L

WNEW

5

3VDD −

2

3Vt

′kn VDD − Vt( )

2

= 3λWNEW

Rn(W=3λ)

Rp(WNEW) = 3λ

WNEWRp(W=3λ)

&xample, Gate %elay o. a O(


67/78

!?

t f =

t f =

&xample, Gate %elay o. a O("3%%453$

A

B

BA

W=31L=2

W=8L=2

OUT

CL=20fF

Rn(W=8λ) =

Rp(W=31λ) =

Rn(W=3λ) ×3λ8λ

= 3.9k Ω×3λ8λ

=1.46k Ω

Rn(W=3λ) × 3λ31λ

= 14k Ω×3λ31λ

= 1.35k Ω

2.2 × (2×Rp(W=31λ) )×CL

= 2.2 × 2 ×1.35k Ω× 20fF = 0.12ns

2.2 × Rn(W=8λ) ×CL

= 2.2 ×1.46k Ω× 20fF = 0.064ns


68/78

!A

Transistor Si-ing &xample

-i)e the transistors in an inverter so that tr =tf p G n = 2KW G 2.KW = 2.%?

Make 1p appro:imately 2.8R1n

VOUTVIN

%&3!&2

%&10

!&2


69/78

!

Transistor Si-ing &xample

-i)e the transistors in an &* gateso that tr =tf

p G n = 2KW G 2.KW = 2.%?

5round donO to 27

-i)e each orst case path for e6ual delay &ssume ,=# in all transistors

3

A

B

C

D

A

B

D

C

'

''

1(

1(

3'

3'

(esult o. Body &..ect, Increased


70/78

?$

(esult o. Body &..ect, Increased%elay

Consider n9transistors in series3 ' has higher +t hile C charged

' turns on more sloly

C, discharges more sloly

Delay 5fall time7 increasesI

1hat to doT

&ttempt to reduce parasitic

C9Ointernal node capacitanceO

Place earliest9arrivingO gate inputs

near Hnd 5+DD" for p9transistors7 Place latest9arrivingO gate inputs

near output

CL

C1

T1

T2 +

-VC1=Vsb1

Vsb2=0V

To Pullup Network

OUT


71/78

?

Body &..ect

1e/ve used fi:ed values for +tp" +tn" 4U' 'his is true only if sourceGsu(strate voltage +s(=$

Not alays the case hen transistors are in series

*ncreasing +s(

increases idth of depletion layer

raises the threshold voltage +t

E:ample 5p. 8!73 if +s(=8+" X+t=$.!+ 5#%Q of +t7

∆V t = γ n Φs + Vsb − Φs( )


72/78

?#

+ower Consumption

-tatic poer consumption 9 due to leakage current DiodeO leakage 9 reverse9(iased diode Yunction

-u(threshold current 9 in deep su(micron devices

'otal static consumption3

Dynamic poer consumption

Poer consumed as outputs sitch toCharge load capacitances

Discharge load capacitance

Pstatic = Ileakage ×VDD

io = is(eqV/kT

− 1)

Isub=

ID0 (WL

)e−

Vgs

−

Vt / nV

th

−

1


73/78

?2

%ynamic +ower Consumption

Charging Capacitor Current" voltage3 E6. 29A" 29 5p. 2$7

Energy3 E6. 29$

Discharging Capacitor Current" voltage3 E6. 29" 29# 5p. 27

Energy3 E6. 292


74/78

?%

+ower Consumption "cont#d$

Poer3 Energy per unit timeP = fRC,R5+DD9+--7# = fRC,R+DD#

1here

f = rate of change of gate output1orst case3 f=f clock 5more likely f L f clock (ut f α f clock

7

P depends only on f" C," and +DDI


75/78

?8

+ower Consumption and 3%%

educing +DD creates large reduction in P *f e reduce +DD to +DD/"

P

P' =V

DD

( )

2

VDD'( )

2

EXAMPLE: if VDD= 5V,V

DD' = 3.3V

P

P'=

5V( )2

3.3V( )2= 2.29

EXAMPLE: if VDD= 5V,V

DD' = 1.8V P

P'= 5V( )

2

1.8V( )2= 7.72

% l d 3


76/78

?!

%elay and 3%%

'radeoff3 reducing +DD increases delay *f e reduce +DD to +DD/"

'radeoff3 reducing +DD decreases noise immunity5more careful design necessaryI7

Rp

Rp'

∝

VDD

VDD'

sotr'

tr

∝ VDD

VDD'

EXAMPLE : if VDD = 5V,VDD'= 3.3Vtr'

tr∝

5V

3.3V= 1.52

EXAMPLE : if VDD = 5V,VDD '= 1.8Vtr'

tr

∝

5V

1.8V

= 2.77

%esign Strategies .or +ower


77/78

??

g g(eduction

Use loer +DD to reduce poer Compensate for higher delays (y

Using neer" smaller" faster *C technology

'rading off more sloer logicO for less faster logicO 9

this is called voltage scaling

E:amples 5from 'om 4urd/s Heneral Processor *nformationO7

*ntel P8 Pentium3 +DD=8.$+ G f clk=!!M0) G P=!1

*ntel P8%C3 +DD=2.2+ G f clk=$$M0) G P=8.$1

*ntel P88+'3 +DD=2.2 G f clk=#$$Mh) G P=2.%1 *ntel P!3 +DD=2.2+G f clk=!!M0) G P=#2.%1

Compa6 &lpha ##!%3 +DD=#.$+ G f clk=!!?M0) G P=?#1


78/78

Speed'+ower +roduct

& ay of characteri)ing the 6uality of a logicfamily

Documents

Lecture05-2005 Combinational Design