Chapter 3 – Combinational Logic Design

Chapter 3 – Combinational Logic DesignChapters 1-2 covered the basic tools for working with combinational logic circuits, including:• number systems• Boolean expressions• Minimization techniques• Logic gates

Chapter 3 introduces topics related to the design of combinational logic circuits, including:• design procedure• hierarchical design• common combinational logic circuits/functions, including:• encoders, decoders, priority encoders• multiplexers, de-multiplexers• magnitude comparators• BCD to 7-segment decoders

1Chapter 3A EGR 270 – Fundamentals of Computer EngineeringReading Assignment: Chapter 3 in Logic and Computer Design Fundamentals 4th Edition by Mano

Types of logic circuitsThere are two broad types of logic circuits:

1) Combinational logic circuits– Circuits whose outputs are determined by logic operations on the input

values– Chapters 1-5 deal with combinational logic circuits

Combinational Logic Inputs Outputs = f(Inputs)

Combinational Logic Circuit

2Chapter 3A EGR 270 – Fundamentals of Computer Engineering

2) Sequential logic circuits– Circuits that include memory devices (such as flip-flops) as well as

combinational logic so that the outputs are based on both present and past inputs

– Sequential logic circuits are introduced in Chapters 6

Combinational

Logic

Inputs Outputs = f(present + past inputs)

Memory

Sequential Logic Circuit


4

Design Hierarchy• A complex logic system might contain the equivalent of millions of gates.• It would be almost impossible to design a complex system by connecting one

logic gate at a time.• A “divide and conquer” approach is used to break the circuit into blocks.• Interconnected blocks form the entire complex circuit.• Large blocks can be broken into smaller blocks.• Each block must have carefully defined functions and interfaces.


Key Point: Many logic circuits will be designed with expansion in mind. For example, a 4-bit adder might be designed so that two of them can be combined to form an 8-bit adder.

Figure 3-2: Design Hierarchy and Reusable Blocks

This design approach is referred to as a hierarchical design.


Figure 3-3: Hierarchy for Figure 3-2• The figure below shows the structure of the hierarchy without the interconnections.• Figure 3-3a shows each block and we see that 32 NAND gates are required.• Figure 3-2b is more compact and only shows one copy of each distinct block.• The NAND gates below are pre-defined circuits and are referred to as primitive blocks.• Functional blocks will later be introduced that are predefined reusable blocks providing

many basic functions used in digital design. Tool libraries often contain widely used functional blocks.


Design Procedure for Combinational Logic Circuits• In Chapters 1-2 we concentrated on analyzing or minimizing given truth

tables or logic diagrams.• In Chapter 3 we will concentrate more on designing logic circuits to

accomplish a given task.• Chapter 3 introduces a general design procedure that can be used to design

combinational logic circuits. • We will also look at commercially-available logic circuits.


Design Procedure (for combinational logic circuits)1. Specification: Write a specification for the circuit if one is not provided.2. Formulation: Derive the truth table or initial Boolean equations that define the

required relationships between inputs and outputs.3. Optimization: Apply two-level and multiple-level optimization. Use Boolean

algebra, Karnaugh maps, or other techniques to optimize the circuit. 4. Technology Mapping: Select the technology to be used to implement the design.

Options might include:• Implement with AND-OR-NOT gates• Implement with Exclusive-OR gates and other basic logic gates• Implement with only NAND gates or only NOR gates• Implement using decoders• Implement using multiplexers• Implement using PLDs or FPGAs (programmable devices)

5. Verification: Verify the correctness of the circuit using methods such as:• Hand analysis• PSPICE simulation• VHDL simulation• Build in lab and test the circuit


Example: Design a 4-bit prime number indicator where the output P = 1 when the binary value of the input ABCD represents a prime number.


Example: Design a 4-bit magnitude comparator, where the output M = 1 when the inputs A3A2A1A0 and B3B2B1B0 are equal.


Example: Design a code converter to convert a BCD code to an Excess-3 code. Treat all invalid inputs as don’t cares.


Group Exercise: Design a circuit where the output is 3 times the input.Assume that the input has 3 bits.A) How many bits will be needed for the output? (Hint: First determine the

largest possible input)B) Draw the truth table.


Group Exercise: (continued)C) Use K maps to determine a minimal POS expression for each output.


x yz

00 01 11 10

0

1

D) Draw the logic diagram (if time allows). How many total gates are needed?

x yz

00 01 11 10

0

1

x yz

00 01 11 10

0

1

x yz

00 01 11 10

0

1

x yz

00 01 11 10

0

1

x yz

00 01 11 10

0

1


7-segment displays

Class Objectives: After this class the student should:• Describe applications of 7-segment displays• Describe how segments are lettered• Describe the difference between common-anode and common-cathode 7-

segment displays• Describe the function of a decoder/driver for 7-segment displays• Develop truth tables for 7-segment displays• Design a minimal logic circuit to implement a 7-segment display driver

15Chapter 3A EGR 270 – Fundamentals of Computer Engineering7-segment displays7-segment displays are arrangements of 7 LED’s that can be used to display the digits 0-9. 7-segment displays are commonly seen in everyday applications, including consumer electronics, watches, electronic toys, test equipment, and much more.

Demonstration: A few sample displays will be passed around during class.

16Chapter 3A EGR 270 – Fundamentals of Computer EngineeringSegment designationThe 7 segments are lettered a-g in the pattern shown below. The digit 3, for example, can be displayed by turning on segments a, b, c, d, and g. Segments e and f would be turned off.

Types of 7-segment displaysThere are two types of 7-segment displays:1) common anode (all anodes at +5V) – LOW inputs used to light segments2) common cathode (all cathodes at ground) – HIGH inputs used to light

segmentsanode cathode

V+ _

A (MSB)

B

C

D

BCD-to-7-segment decoder/driverIn order to light the appropriate segment for each possible digit, a decoder is needed. Sometimes the decoder is also called a driver because it can provide the higher current levels needed by LEDs. This device will have:• 4 inputs for the input BCD code• 7 outputs for the 7-segmentsAn example BCD-to-7-segment decoder is shown below:


BCDinput

Outputs for7-segment

display

BCD-to-7-segment decoder(with active-HIGH outputs)

Common cathode7-segment display

TypicalSegment

DCBA (LSB)

BCD-to-7-segment decoder/driverThere are two types of commercially available BCD-to-7-segment displays drivers:1) common cathode display driver – This driver must be used with a

common-cathode 7-segment display. For each BCD input, it provides HIGH outputs for each segment to be lit (active-HIGH outputs).

2) common anode display driver – This driver must be used with a common-anode 7-segment display. For each BCD input, it provides LOW outputs for each segment to be lit (active-LOW outputs).


The 7448 is a commercially available BCD-to-7-segment decoder/driver that is intended to drive a common-cathode display. Note that “current-limiting resistors” are required for each segment. Also note that input A is the LSB.

Similarly, the 7447 is a commercially available BCD-to-7-segment decoder/driver that is intended to drive a common-anode display. Note that “current-limiting resistors” are required for each segment. Also note that input A is the LSB.


BCD-to-7-segment decoder(with active-LOW outputs)

Common anode7-segment display

TypicalSegment

DCBA (LSB)

bubbles indicate that the outputs are active-LOW


Common-cathode displays - internal connections • Add the internal connections for 7-segment display if it is a common-

cathode display.• Illustrate the inputs and outputs if the input is 7 (BCD)• What connects to CC (common cathode)?

abcdefg

DCBA (LSB)

7448

a

b

c

d

e

f

g

CC

anode cathodeV+ _


Common-anode displays - internal connections • Add the internal connections for 7-segment display if it is a common-

anode display.• Illustrate the inputs and outputs if the input is 7 (BCD)• What connects to CA (common anode)?

abcdefg

DCBA (LSB)

7447

a

b

c

d

e

f

g

CA

anode cathodeV+ _


PSPICE: The parts used in PSPICE for 7-segment displays do not look like typical 7-segment displays, but instead look like 7 diodes. However, their connections make it clear if they are common cathode or common anode.


Illustration: If the BCD digit 3 is to be displayed in each case below:• Add binary values to the inputs A, B, C, D• Add binary values to the outputs a, b, c, d, e, f, g• Color the lit segments

D

C

B

A (LSB)

Case 2: Common-anode display

D

C

B

A (LSB)

Case 1: Common-cathode display

Unused inputsSince the BCD-to-7-segment display driver is intended for BCD inputs (0-9), not that inputs some inputs are unused (10-15). These unused inputs could be handled in a variety of ways:1) Blank display2) Treat as “don’t cares” for simplest circuit. 3) Let the unused input represent A, b, C, d, E, F so that they can also be used

with hexadecimal inputs. (Why are b and d in lower case?)4) Display unique patterns not equal to any of the decimal digits. The 7447 and

7448 use this approach. The unique patterns used are shown below.


Example: Design a BCD-to-7-segment decoder to drive a common anode display with a blank display for all illegal inputs. (K-maps on following slide.)


BCD Digit A B C D a b c d e f g0123456789------

Let A be the MSB.


ABCD 00 01 11 10

00

01

11

10

ABCD 00 01 11 10

00

01

11

10

ABCD 00 01 11 10

00

01

11

10

ABCD 00 01 11 10

00

01

11

10

ABCD 00 01 11 10

00

01

11

10

ABCD 00 01 11 10

00

01

11

10

ABCD 00 01 11 10

00

01

11

10

How many total gates are required?Compare this to the circuit provided on the data sheet for the 7447 (next slide)


7447 Schematic(from the data sheet)

Group Exercise: Design a BCD-to-7-segment decoder to drive a common cathode display that displays A,b,C,d,E,F for inputs (10-15). Let D be the MSB.


BCD Digit D C B A a b c d e f g0123456789

101112131415


DCBA 00 01 11 10

00

01

11

10

DCBA 00 01 11 10

00

01

11

10

DCBA 00 01 11 10

00

01

11

10

DCBA 00 01 11 10

00

01

11

10

DCBA 00 01 11 10

00

01

11

10

DCBA 00 01 11 10

00

01

11

10

DCBA 00 01 11 10

00

01

11

10

How many total gates are required? ______

Technology Mapping (Note: The instructor may choose to omit this section)If an initial design is specified using AND, OR, and NOT gates, the design may

then be converted (or mapped) into a new technology. Examples in the text include:

1) Mapping a design to NAND logic2) Mapping a design to NOR logic

Note that NAND and NOR gates are “universal gates”, meaning that they can be used to form any other type of basic logic gates. Figure 3-14 on the following page illustrates the mapping of other gates into NAND and NOR gates.

Show how to form other logic gates using NANDs:


Figure 3-6: Mapping of AND gates, OR gates, and Inverters to NAND gates, NOR gates, and Inverters.


Procedure for converting (mapping) a circuit into NAND or NOR circuits:1. Replace each AND and OR gate with the NAND (NOR) gate and inverter

equivalent circuits.2. Cancel all inverter pairs (back-to-back inverters).3. Without changing the logic function, “push” all inverters through branches

to represent them as multiple inverters.

Example: Implement the following optimized function with NAND gates and inverters.

F = AB + (AB)’C + (AB)’D’ + E


Example: Repeat the last example using NOR gates and inverters.F = AB + (AB)’C + (AB)’D’ + E


Documents

Chapter 3 – Combinational Logic Design