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ColonialELECTRONIC MANUFACTURERS, INCORPORATED

Design

For

Manufacturability

GUIDELINES

DFM-1 REV-C

One Chestnut Street Nashua, New Hampshire 03060Telephone: (603) 881-8244 FAX: (603) 881-8186

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DFM-1 Rev -CMay 16, 2001

Design for Manufacturing Specification for Thru-Hole / Surface Mount Technology(All Dimensions in inches unless otherwise specified).

Table of Contents-------------------------------------

1.0 Introduction1.1 Scope1.2 Applicable Documents1.3 Assembly Types1.4 Surface Mount Packages

2.0 Basic PCB Design Requirements2.1 Board outline2.2 Board Thickness2.3 Bow and Twist2.4 Shape2.5 Placeable Area2.6 Tooling Hole Locations2.7 Fiducial Marks2.8 Irregular Shaped Boards2.9 Panelization of PWB’s2.10 Grids2.11 Artwork (Gerber Pho Files) Generation2.12 Silkscreen considerations2.13 Drill drawing information2.14 Assembly drawing information2.15 Design rule check2.16 Cad outputs

3.0 PWB Design Considerations3.1 Component Holes, Pads and Via Sizes3.2 Circuit Layout3.3 Component Layout (General)3.4 Component Alignment3.5 Component Orientation3.6 Clearance Requirements3.7 Solder Mask3.8 Surface Mount Land Pattern Design

4.0 Design for Testability4.1 General4.2 Test Pads4.3 Test Pads Masking and Location4.4 Test Pads and Component Clearances4.5 Test Pad / VIA Combinations4.6 Power and Ground Test Requirements

5.0 Deliverable CAD / Fabrication / and Assembly Supplier5.1 Deliverables from PCB design Cad supplier5.2 Deliverables to fabrication supplier5.3 Deliverables to assembly supplier

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DFM-1 Rev -CMay 16, 2001

Design For Manufacturing SpecificationFor Thru-Hole/Surface Mount Technology

1.0 Introduction

1.1 Scope - This DFM Guideline establishes minimum criteria for the design andlayout of single, double-sided, and multi-layer designs using through-hole,surface mount, or mixed technologies. For PWB’s or also known as PCB’s

1.2 Applicable DocumentsIPC-T-50-Terms and DefinitionsIPC-SM-782-Surface Mount Land PatternsIPC-S-100-Standards ManualIPC-D-330-Design Guide ManualIPC-G-400-Guidelines ManualIPC-D-275-Design Standard for Rigid Printed Boards and AssembliesCurrent supplier standards as applicable for fabrication and assembly.

1.3 - Assembly Types

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Figure 1.3 Assembly Types

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1.4 – Surface Mount Packages

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2.0 Basic PCB Design Requirements

2.1 Board Outline – The maximum board size is 18.00 long x 14.00 wide. Theminimum panel size is 4.00 long x 2.50 wide.

2.2 Board Thickness – For standard PWB materials (Fr-4, G-10, Etc.)Theminimum PWB thickness is .031 while the maximum is .125. The typical multi-layer PWB is .062 thick while the typical back-plane is 0.093 to 0.125 thick. Othermaterials are available to make PWB’s of thinner materials such as metal orceramic substrates, to go below the 0.031 minimum restrictions.

2.3 Bow and Twist – The maximum bow and twist after fabrication should be.010 in/in. All copper planes will be balanced. Outer layers to be cross – hatchedfor wave solder thermal characteristics to minimize warping.

2.4 Shape – The PWB or panel is required to have two parallel sides in thedirection of process flow. See Figure 2.4. The leading edge of the board, whichdetermines the process flow, should be the shortest edge of the board. The longestparallel edges of the board, should be the conveyor edges. The leading edge of theboard should have a square edge. If the edge is not square it will exhibit a problemin the assembly process due to the board needing to contact a mechanical stop inthe placement equipment, or for wave soldering consideration.

Figure 2.4: PWB Shape Board or Pallet

Process Flow

Breakaway MaterialParallel Sides added to Square Board edge

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2.5 Placeable area (Through-Hole) – Tooling hole Clearances andplaceable area requirements for through-hole DIPS and Axials

Figure 2.5:Tooling Hole and Edge Clearances for Through-Hole DIPS and Axials

2.6 Tooling Hole Locations – Four non-plated tooling holes 0.125” are requiredon each PWB in order to provide accuracy for automatic assembly and testprocesses. This requirement is the same for panelized PWB’s but the holes mayexist on the breakaway material. The location and clearances are as in Figure2.6. For SMT Assembly machine there is a location pin restriction of .400 areafrom front edge of Board or Pallet. See figure 2.6.A

Figure 2.6: Tooling Hole Clearances and Placeable Area for SMT

.200 min

Process flow Leading edge of PCB

.200 min

.200 min Fiducial (4 Places)

.354 min

.200 min

.394 min

.200 min

"0"

Component keep out area

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Figure 2.6A Mountable area for SMT assembly machine

2.7 Fiducial Marks – For each side of the PWB that has SMT componentslocated on it, the PWB must have three global fiducials and one bad sense markfiducial on it. No solder mask is allowed to cover these locations. The Fiducialsshould be placed as far apart from one another as possible on grid with respect todatum. For panelized boards, four fiducials on both sides are required on thebreakaway material as well as each individual circuit in the array. See Figure 2.7for locations and clearances.

Figure 2.7: Fiducial Mark Locations

Fiducial ( 4 places minimum

Process Flow 8 places if double sided SMT)

.216 min (all edges)

.216 min

(all edges)

Component keep out area

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Figure 2.7.1: PWB Fiducial Marks

2.7.1 Global Fiducials–The preferred global fiducials are a .040” diameter witha .080” diameter window clear of silkscreen, solder mask, holes, or circuitry onoutside layers. Fiducial marks may be required on stencil artwork for gluing onbottom side components. These are the same as bad sense marks.

2.7.2 Local Fiducials – All fine pitch patterns (.031 lead pitch orsmaller) must have two local fiducials. (See Figure 2.7.2). These fiducials will belocated on opposite diagonal corners of the land pattern so as not to allow the bodyof the device to infringe on the fiducial keep out area. The fiducial pads size is thesame as global fiducials. Do not put fiducial openings in the solder paste stencilA/W.

Figure 2.7.2: Component or Local Fiducial Marks

2.7.3 Bad Sense Mark – Smt layers will carry a .100 fiducial with a .100minimum soldermask relief for machine requirements, quantity one per board, oneach side top and bottom. Locate at edge of board outside component placementarea.

.040 dia fiducial pad

.080 clearance (void areas)

.040 dia

.080 SolderMask Clearance (Void Area)

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2.8 Irregular Shaped Boards – PWB’s with irregular edges should either havebreakaway material added to the leading edge or be panelized to make the edgesquare (i.e. uniform and continuous). The leading edge of the board must becontinuous as this edge needs to hit board stops in the SMT auto-placementmachines and as it rides in on the finger conveyor system on the wave soldermachines. See Figure 2.8.

Figure 2.8: Irregular Shaped Boards

2.9 Panelization of PWB’s – The following are guidelines for the panelizationof PWB’s. Boards with a minimum dimension smaller than 4.00 are candidates forpanelization. The design engineer should consult with Colonial ElectronicManufacturers’ Technical Director for inputs in order to meet the guidelines forassembly equipment.

2.9.1 Board Outline – Where possible, the shape of a panelized PWBshould be square or rectangular in nature. This allows, for moreeconomical material use than boards with complex shapes and projections.

2.9.2 Panel Size – Standard panel sizes are 12 x 16, 14 x 16, 16 x 18, 16 x 21, and18 x 24. Preference is to use a standard 18 x 24 panel size to keep board yield highand cost low. Plateable area around panel requires .50 inches for Two sidedmaterial, and .75 inches for multi layer material.

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2.9.3 Routing Tabs/Locations – The width of the route tab should be.100 max. One tab should be provided for every 3.0 of board edge length. Tabsshould be placed from .5 to 1.0 from corners of the board in both directions. Thereshould be at least 2 tabs for each side of the board that is 2.0 or greater in length.Route tabs are not allowed to be placed directly on corners. Tabs should not belocated directly beneath overhanging components (connectors, etc.). All routelocations should be defined on the fabrication drawing. See Figure 2.9.3.

Figure 2.9.3: Panel Routing Specifications

.100TYP.

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2.9.4 V-Score Breakaway – The preferred V-scoring of a pallet willspecify remaining material after cutting. Scoring locations and depth mayvary depending on component weights, width going thru solder machine.Standard is .015 +/- .003 dimension. On board designs no outer or innerCopper layer will have copper present at V-score due to blade cutting intoboard edges. Never will exposed copper be allowed after individual Board isbroken from pallet. Allow .020in from edge of board to any copper.

V – Score dimension consideration Figure 2.9.4

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2.9.5 Micro-Drilling Breakaway Tabs – The preferred method of employingbreakaway tabs is the use of micro-drilled breakaway tabs conforming to Figure2.9.5. These tabs should occur approximately every three inches of breakawayMaterial. Use of this method will result in a burr free edge.

Figure 2.9.5: Micro-Drilled Breakaway Tab

2.9.6 Minimum Panel Margins – The minimum width of panel margins froman outer panel edge to the nearest breakaway slot is .500.

2.9.7 Step and Repeat Dimensions – For automatic test purposes, locate thesame features on adjacent boards in even increments of .100 from each other sothat the test points/vias can fall on an even grid.

2.9.8 Wave Solder Support Slot – For each panelized board exceeding 12inches in width design consult with Colonial Electronic Manufacturers’ TechnicalDirector to determine if there should be provisions for a support fixture. Thisfeature is important for panelized boards due to the sagging possibility during thewave solder process.

2.9.9 Edge Connector Fingers – For PWB’s requiring gold plating of edgefingers the panelization process may not be able to be utilized. Thepanelization technique is able to be utilized for tin/lead plated fingers. If aboard with gold fingers is to be panelized the fingers must be on an outer edgefor plating. Consult manufacturing engineering from your PWB supplier for goldplating process requirements.

2.9.10 Impeadance Control – On multi up panels for impeadance controlboards, allow a .75 x 6.00 inch coupon in center of panel. Reference

.035 dia

PCB Side.100 max

Scrap Side .100

.050

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registration coupons per IPC-D-275 designs standards for rigid boards.

2.9.11 Breakaways with overhang Components - Show breakaways cross-hatched to distinguish breakaway material versus usable board material.Show one board on pallet with component outlines that extend into thebreakaway area. This makes it easier to visualize what can and can’t be donefor changes that can possibly reduce costs at the fabrication and assemblysuppliers. This will represent the total overhang in relationship to the edge of thepallets for wave solder finger conveyor considerations.

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2.10 Grids

2.10.1 Through-Hole Mounted Components – The preferred componentmounting grids will be .100 for through hole components with respect to the x,ydatum lines specified on the fabrication drawing. An .050 grid is acceptable butnot preferred. Hole patterns that cannot be fit on grid should have at least one oftheir holes located on grid. It is preferred to have via holes fall on grid, especially ifthey might be used as converted test vias.

2.11 Artwork (Gerber .pho files) Generation

2.11.1 Silkscreen Artwork – A pattern showing coverage of referencedesignators and component body outlines that will be placed over the soldermaskfor identifying component body outlines and reference designators.

2.11.2Gerber Artwork – 1/1 scale photo plots of all PWB copper layers, soldermasks, Solder paste stencils, and silkscreen.

2.11.3 Solder Mask Artwork – A pattern showing coverage of all copperconductors to be free from soldering.

2.11.4 Solder Paste Stencil Artwork – A pattern of openings in the solderstencil through which solder paste is deposited to the component pads.

2.12Silkscreen Considerations

2.12.1 – Silkscreen “Made in USA” flag symbol – If your product iscompletely assembled in the U.S.A. then the addition of a Made in U.S.A. and Flagsymbol is a desirable option. This could Be added to the silk screen at noadditional cost (provided that the board is still in the design stages). Or a label canbe added after assembly is complete. The later would require a cost of labor andlabels.

2.12.2 Silkscreen outline for Serial Number / Bar Code Label – If serialnumbers or bar codes are required the area to receive the label should be markedon the silk screen layer, and represent the actual size of the label.

2.12.3 - Silkscreen component pin 1 and Polarity identifiers - Allcomponents having a pin number 1 or polarity identifier will be shown on thesilkscreen and will be visible after component attachment.

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2.12.4 - Identification – Artwork should contain the PCB part number. ThePCB part number should be on the top side of the PCB with the current revision.

2.12.5- Silkscreen CE mark – CE and UL markings can be added to thesilkscreen layers to reduce cost of labor and labels. Care must be taken to assureproper specifications are followed to meet requirements.

Minimum Height = .20Width = .28Line Width = .03

2.12.6- Silkscreen Component Body outlines 0603,0805,1206There are many ways to mark and identify components. The following are theminimum requirements for component identification. All 0603, 0805, and 1206surface mount components will have the outlined identified as a .015 solid dotcentered between the pads. All Tantalum Capacitors with case sizes of A,B,C andD will adhere to specification provided. The positive side will be identified with adouble line width of .020. The body outline will be .010 line width. The silkscreenwidth of all bodies will adhere to the actual width of the component.

For 0603,0805,1206 Tantalum caps cases A,B,C,DCase A width = .070Case B width = .118Case C width = .137Case D width = .181

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2.13 – Drill Drawing Information

2.13.1 Drill Chart Hole Sizes - Drill chart will combine any hole sizes thatoverlay within specified tolerance range. Smallest size to be .013. Smaller hole sizewill go to next higher hole size as long as min +.007 over max MFG lead is obtained.

Examples; if Qty 33 with size .037 +/- .003and Qty 10 with size .040 +/- .003combine to Qty 43 with size .038 +/- .003

Fig 2.13.1 Drill Chart

2.13.2 Slots – Slots will be identified with a letter symbol and will have a detail “A”called out. This gives the PC fab supplier a clear orientation of slots. All slotswill have an associated drill chart symbol referenced in the detail view.

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2.13.3 Reference X-Y hole to edges – Drill drawing will identify one hole to twoedges of board to accommodate PCB fabricator to locate corner of board for stepand repeat associated with palletization, and routing of board edges.

2.13.4 Standard drill drawing notes – All drill / fabrication drawings will carrythese notes.

1) Any exceptions to specifications will be listed as a note on drawings.Example: Gold plate Fingers

2.13.5 Chamfers – Chamfers on insertion type PCB’s will be .02 x 45 degree bothsides.

2.13.6 Standard routing bits – Standard routing bits are .100, .125, .093, and.062. Less than .062 will increase cost (10 to 20%). Specify a standard .100 routingbit.

.250

0

0.300

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2.13.7 Multi – layer stack up, tolerances – The drill / fab drawing willindicate the layer stack up and tolerances as shown;

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2.14 Assembly drawing information – Any notes, details or specialinstructions to make the assembly clear will be noted on the drawing. Any jumperplugs for jumper pin headers will be noted as such

2.14.1 Find Numbers – Use of a find number (balloon item number) on drawingwill be used whenever necessary such as hardware.

2.14.2 LED’s – Any LED’s having a colored mark on body to identify cathodeend will be noted as such.

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2.14.3 Component locations – All components will be identified by thesilkscreen reference designators outline.

2.14.4 Standard Note: Colonial Electronic Manufacturers Inc., as a default, willassemble to the guidelines of IPC-610-C, unless requested by the customer toassemble to the specifications of some other guideline.

2.15 Design Rule Check – All PCB designs should have a DRC performed forMinimum copper width.Minimum spacing requirements.Silkscreen on component pads.Minimum annular rings on drill pads (components, vias, and mounting

holes).Solder Mask clearances and coverage.Solder Paste openings.

2.16 Cad OutputsFor a current sample of cad format needed for programming please request

a sample from Colonial Electronic Manufacturers Inc. Technical Director.Aperture lists should include dcode, shape, quantity. No unused apertures

will be included.X-Y programming of surface mount components should be in a column

format preferably in an excel spreadsheet, clearly readable forprogramming input to machine. See example at the end of this handbook.

Paper plots should be right reading for bottom copper layer and silkscreenlayer for ease of checking design.

3.0 PWB Design Considerations

3.1 Component Holes, Pads and Via Sizes

3.1 .1 Calculating Sizes (Holes and Pads) – Minimize the quantity of differenthole sizes. Avoid sizes overlapping in tolerance. See Table 1 for the method ofcalculating hole and pad sizes. Note: Check manufacturers part specificationfor recommended hole sizes.

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Non-Plated Thru-Holes Plated Thru-HolesFinished Hole Size:Hand Inserted Part N/A L + 0.007 minAuto Inserted Part N/A L + 0.012 minPad sizes External and Internal:External Layer Pad Size H + .050 Min H + .020 MinInternal Layer Pad/Size Clearance H+ .020 Min H + .031 MinFinished Via Sizes:.062 Thick PWB Minimum Size = .013 + .000/-.008 with .030 ext pad size

Preferred Size = .020+/-.003 with .040 ext pad size.093 Thick PWB Minimum Size = .020+/-.003 with .040 ext pad size

Preferred Size = .030+/-.003 with .058 ext pad size.125 Thick PWB Minimum Size = .025+/-.003 with .053 ext pad size

Preferred Size = .039+/-.003 with .068 ext pad size

L = Part Maximum Lead diameter, H = Maximum hole SizeMaximum takes into consideration Manufacturers Tolerances

3.1.2 PTH Diameter Tolerance – For PTH’s the specified tolerance should be asfollows

Hole Size Tolerance

Equal to or Less than .061 .003

Equal to or Greater than .062 .005

3.1.3 Pads - The minimum via hole size is limited by PCB fabrication capabilities.It is preferred that no unused pads without traces be located on inner layer

3.1.4 External Pad Sizes for PTH’s – See Table 1 for pad sizes and shapes oncomponent and solder sides. For unlisted PTH pad sizes, pad diameter shouldbe at least .020 larger than the associated nominal hole size.

3.1.5 Internal Layer Pad Size for PTH’s – The internal layer pad diametersshould be at least .031 larger than the associated nominal hole size.

3.1.6 Internal Layer Pad Sizes for NPTH’s – A clearance should surroundnon-plated holes on all inner layers. The clearance should be of a size and shape toprovide clearance of at least .020 larger than the nominal hole size where a noconnect is desired.

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3.1.7 External Layer Pad Sizes for NPTH’s – A void should surround non-plated holes on all external layers. The void should be a size and shape to provideclearance of a least .050 larger than the nominal hole size where a no connect isdesired.

3.1.8 Thermal Relief Pads – On Multi-Layer Boards, thermal relief pads shouldbe used around all holes in voltage and ground planes where planes are connectingto IC’s, resistor networks, and discrete components rated at one watt or less.The thermal pad is circular in nature split up into four sections with .010 to .020between ends of the sections. The inside diameter for the thermal is .060 whilethe outside diameter is .080 for .038 plated through holes. The thermals shouldbe at a 45or 90.

3.1.9 Converted Thermal Relief Pads –Internal voltage and groundconnections from a cad output thermal shape can be converted to a direct hit to theinternal plane by modifying the aperture list and noting the shape as “DH”.

3.2 Circuit Layout

3.2.1 Preliminary Engineering Layout – Engineering study will determineinitially the critical components on a given design from the standpoint ofcomponent density, heat dissipation, vibration factors, electrical compatibility,assembly, maintainability, and other functional requirements such as circuitfrequency and speed.

3.2.2 Conductors

3.2.3 Distribution – Copper distribution on each layer should be as even aspossible for proper copper etching, copper plating Balancing , and PWBLamination warpage control. Outer layer conductors, side to side, should also bebalanced. Open areas on internal layers should be filled with either additionalpower planes, ground planes or non-functional copper to assist in plating densityfabrication concerns.

3.2.4 Minimum Line Width/Spaces – Utilize standard technology whereverpossible to provide the highest yield and quality manufacturable PCB. However,use of fine line technology may be used if layer reduction can be achieved or spaceis at a premium

TechnologyLine/SpaceTolerancesPreferred Technology.008/.008.0015Standard Technology.006/.006.0015Fine Line Technology.005/.005.0015

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3.2.5 Copper Thickness – All copper weights will be specified on the Drill /Fabrication drawing .1/2oz = .0007 1oz= .0014 1 1/2oz = .0021 2oz= .0028

3.2.6 Signal Routing – On boards using through hole mounted dips, it ispreferred that the signal runs on the solder side shall run perpendicular to themajor axis of the dip. This allows signal runs between the lead mounting holes andpermits an outward or inward crimp on the lead without danger of solder bridgingto adjacent runs (if solder mask is not used). Where possible, signal conductorsshould be uniform in width along the entire conductor run using 45cornering forFCC emissions.

3.2.7 Conductor Width – The minimum conductor width on the finished boardshould be determined on the basis of the current carrying capacity required, andthe maximum permissible conductor temperature rise. For general use thepermissible temperature rise is defined as the difference between the maximumsafe operating temperature of the laminate and the maximum ambient temperaturein the location where the board will be used. Charts for this purpose are availablein IPC-D-275.

3.2.8 Conductor Length – Minimizing the length of conductor runs should bestandard practice. This will result in the minimization of capacitance important inhigh frequency applications and minimizing ohmic resistance for critical voltageregulation requirements.

3.2.9 Conductor Bends – To minimize entrapment of processing chemical andFCC emission control, bends should be as indicated below.

Figure 3.2.9: Conductor Bends

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3.2.10 Conductors Routes Into SMT Pads – Conductors can be routed into a SMTland pad from any direction and from any angle, however circuitsconnecting to a pad may not lay beside the pad, which will effectively widenthe pad. See Figure 3.2.10

Figure 3.2.10: Conductor Routes Into SMT Pads

3.2.11 Spacing of Conductors to SMT Land Pads – Conductor should bespaced a minimum of .006 from a SMT land pad to allow for complete coverage ofthe conductor with solder mask. See Figure 3.2.11

Figure 3.2.11: Conductor Spacing to SMT Land Pads

3.2.12 Edge Clearance – Unless the CAD outline drawing dictates otherwise, thefollowing nominal dimensions (prior to fabrication and assembly tolerances) shallbe the closest that components, mechanical parts, conductors, pads, and etchedmarkings can be to PWB edges (exceptions are critically located parts such asconnectors, LED’s, switches, etc.).

EdgeItem ClearanceConductors, pads, and etched markings on cardExternal Layers - .150 inchesguide edges. Internal Layers - .025 inchesConductors, pads, and etched markings. Internal/External Layers - .025 inchesEdges of components and mechanical parts.125 inches minimumconveyor edges.Test Pads to Edge of Board .125 inches minimum

.006 min

.008 preferred

Land Pad

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3.2.13 Layer quantity and Voltage/Ground Plane Locations – To ensureboard flatness, Multi Layer Boards will contain an even number of layers. Voltageand ground layers should be located at the center of the MLB lamination. Toincrease to an even number of layers if the design would have an odd number, theground layer may be duplicated, with the duplicates located adjacent to each other.If the design contains a voltage layer, the two duplicate ground layers shouldsandwich the voltage layer. There should be no large bare board or largeunbroken copper areas (greater than approx. 1 sq. in.) on internal or externalsignal layers. Cross hatching is recommended to fill in these areas and to break uplarge copper areas.

3.2.14 Repetitious Circuitry – When practical, component arrangement incircuits repeated on a particular PWB should be identical. If possible, functionalcircuits of mostly discrete components within a PWB should be physicallyseparated for visual identification. See Figure 3.2.14

Figure 3.2.14: Repetitious Circuitry Sample

3.2.15 Reduction of Radio Frequency Interference/EMI – To produce EMIquiet design the rules layout below should be observed. In today’s fine pitch andpower “thirsty” LSI devices coupled with high speed clocks and SMT components(increased density per sq. inch) correctly placed devices and proper routing willresult in better design.

3.2.16 Power and Ground Carrying Conductors and Vias – The via shouldbe placed at the minimum distance as outlined in Figure 3.6.5. No thermal relief isrequired for the via. Only one power pin (VCC or ground) is allowed to beconnected to the single via). The via can be shared by the bypass capacitor placednext to the power pin. The maximum width conductor should be used for powerconnection. The preferred vias for power and ground should follow preferred holeand pads listed in Table 2.4.

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3.2.17 Decoupling Capacitors – The decoupling capacitor should be uniformlydistributed throughout the board. At least 1 (one) bypass capacitor per power pinshould be placed on the board in the proximity of VCC power. Any additionalfiltering or bypassing in an excess of standard by-pass should follow manufacturerecommendation.

3.2.18 Chassis Ground – The chassis ground etch should not overlap any ofpower or signal ground on any of the layers. When the edge of the PWB containsconnectors that utilize shielding for EMI reduction, there should be chassis ground“plane” on at least 2 (two) layers, connected at least 1” apart and providingconnection to attached panel, the chassis ground etch shall be exposed allowingattachment of other EMI gaskets, connecting springs, etc. to the back panel. Thewidth of the chassis ground should be at least .375 thick. If the layout allows, awider etch is preferred.

3.2.19 Power – On power boards, where high voltage potential exists, conductorspacing should follow UL 1950, IEC 950 spacing requirements. The conductorsand spacing should be identified by the cognizant engineer prior to starting PCBlayout.

3.2.20 Telecommunication Circuits – The circuits intended for attachment tothe wide area telecommunication network like (ISDN, TI, PSTN) shall provide3mm clearance between primary and secondary circuits. The area under primarytelecommunication circuit shall be clear of any planes (ground, power, chassis) andno other signals, shall be laid out in that area.

3.2.21 Clock Lines – The clock lines should be identified by cognizant engineerprior to layout. The clock lines should be routed away from PCB side that containsany connectors interfacing with outside world. The component placement shouldminimize length of the clock. The clock should be routed in the daisy chain fashion,the “stubbing” should be avoided. There might be other constraints related toclocks those should be identified by the design engineer prior to routing. Thepreferred placement of clock lines is next to the ground plane layer.

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3.3 Component Layout, General

3.3.1 Component Placement – All components should be laid out to utilizeautomatic placement and insertion equipment.

Figure 3.3.1 – Component Placement

3.3.2 Component Orientation for Wave Solder – The preferred orientationis used in order to optimize the resulting solder joint quality as the assemblyexits the solder wave.

All passive components shall be parallel to each other. All SOIC’s shall be perpendicular to the long axis of passive components. The longer axis of SOIC’s and of passive components shall be perpendicular to

each other

3.3.3 Heat Dissipating Parts – Parts dissipating more than one watt or havingan operating temperature of more than 240F (115C) should be mounted so thatthe body of the device is not in direct contact with the PWB surface unlessappropriate heat sinking is used to lower the operating temperature withinacceptable limits.

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3.3.4 Component Contact and Obstruction – Components should not toucheach other or mechanical parts, nor be stacked. No component should inhibit theability to rework an adjacent part. This means be careful in the positioning oftaller parts next to Through-Hole or SMD devices so as to allow adequate space forrework tools. This space should be .100 or larger.

3.3.5 Parts Sensitive to Shock and Vibration – Components susceptible tofailure from shock or vibration should be located as near to the edge of the boardmounting points as possible.

3.3.6 Components Within Board Area – No portion of a component shouldextend beyond the edge of the PWB, except designated parts on the CAD drawing(i.e. connectors, etc.)

3.3.7 BGA Components – Components must not be allowed within .200 aroundperimeter of device to allow for rework station nozzle clearance to keep rework ofsurrounding components to a minimum.

3.4 Component Alignment

3.4.1 Discrete Components – Unless design requirements dictate otherwise,discrete components mounted parallel to each other in a line should be lined up ontheir centers. It is preferred that all components be mounted in one-axisorientation, but two axis orientation is acceptable when required.

3.4.2 Component Polarization – All polarized components (or components withkeying features, such as transistors) should be mounted with their indicatedpolarity ends or keying features facing the same direction throughout the entiredesign, or within circuit groups where possible.

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3.5 Component Orientation

3.5.1 Top Side Component Orientation – Figure 3.5.1 shows the properorientation for dual in line top side components.

Figure 3.5.1: One Axis Layout Through-Hole

3.5.2 Bottom Side SMT Component Orientation – Figure 3.5.2 shows the properorientation for bottom side components.

Figure 3.5.2: Bottom Side SMT Component Orientation

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3.6 Clearance Requirements

3.6.1 Component Clearance for Socketed Dips and Axials – Figures 3.6.1and 3.6.1A show the appropriate clearances to allow for automatic insertionof through-hole components.

Fig 3.6.1 Component clearance for thru hole devices

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Figure 3.6.1A: Component Clearance for Axials and Radials

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3.6.2 Axial and Radial Lead Hole Spacing for Automatic Insertion –Axial leaded hole spacing is equal to the maximum body length of thecomponent plus .126 plus one nominal lead diameter for bend radiusclearance. Maximum insertable lead to lead length is .600 and maximumbody diameter is .200. Radial component lead spacing is .200 preferred.Transistor packages should be .100 lead to lead spacing with the leads beingin line. Maximum transistor body diameter is .312 and maximum bodyheight is .400.

3.6.3 Component Clearance Top Side SMT and T.H. – Pad to Pad– Figure 3.6.3 shows the appropriate top side SMT to SMT and SMT toT.H., pad to pad clearances.

Description Spacing TopSideChip to Chip .040 typ, .025 min

Chip to SOICChip to Tantalum Cap (cases A,B,C,D)

.040 typ, .025 min

.040 typChip to PLCC .040 typ, .025 min

PLCC/SOJ to PLCC/SOJ .100 typ, .050 min

SOIC to SOIC .050 typ, .025 min

SOT23 to SOT23 .040 typ, .025 min

Chip to axial component body .075 typ, .050 min

PLCC/SOJ to dip pad .060 typ

PLCC SMT socket body to PLCC SMT socket body .050 typ, .040 min

PLCC Socket body to other body if height is higher than socket .100 typ, .075 min

Fine pitch to fine pitch .100 typ, .075 min

Fine pitch to non-fine pitch (.020 pitch) .250 typ, .100 min

Figure 3.6.3: Component Clearance Top Side SMT and Through-Hole –Pad to Pad

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3.6.4 Component Clearance Top side leaded and Bottom SideThru hole – Pad to lead Figure 3.6.4 shows the appropriate TopsideThrough hole to bottom side SMT clearances.

Description Spacing Bottom side

Chip to Chip .040 Typ, .030 MinChip to Tantalum Capacitors (Cases A,B,C,D) .050 Typ, .040 MinChip to SOIC .050 Typ, .040 MinSOIC to Tantalum Capacitors (Cases A,B,C,D) .050 Typ, .040 MinSOIC to SOIC .050 Typ, .040 MinTantalum Cap to Tantalum Cap .050 Typ, .040 Min

Fig 3.6.4 Component Clearance

3.6.5 BGA component spacing requirements – Fig 3.6.5 shows theappropriate clearances between component body and adjacent component.No components are allowed within .200 in around perimeter of BGA device.This area is reserved for rework equipment nozzle space requirements.

Fig 3.6.5 BGA Spacing

BGA Nozzle clearance perimeter of BGA tobe free of components

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3.7 Solder Mask – Solder masks should be designed for both primary andsecondary sides of the PWB. See below for clearances/coverage’s. For finepitch component pads a pocket soldermask is preferred. If pads cannotaccommodate a minimum coverage of .004 then a gang soldermask isacceptable. All vias will be covered unless specified.

Pocket Solder Mask

Gang Solder Mask

Clearances/Coverage’s

Area Clearance/CoverageUn-plated Holes, Slots and Cutouts .050 Min. clearance around each hole.Component Pads, Test Pads .003 nominal/.0025 min clearance around

each padEdge Fingers The mask should stop at the ends of the fingers.Traces adjacent to pads Extend min. of .003 beyond edges of traces.Between fine pitch pads .004 min. coverage between pads.Via Holes 100% coverage.

3.8 Surface Mount Land Pattern Design

3.8.1 Land Pattern Design Standards – Use the current IPC-SM-782Surface Mount Land Patterns specification for all land patterns.

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3.8.2 Bottom Side Actives and Chip Arrays – If necessary, bottom sidechip arrays and SOIC’s (50 mil pitch) can be designed onto the bottomside of the board and wave soldered, provided the maximum processtemperatures are within the parts specifications. Leading and trailing padwidth should be increased 100% for solder thieving.

3.8.3 SQFP and QFP (Square) land patterns – The total length andwidth of pad will be calculated using IPC-SM-782 subsection 11.2. When aQFP does not fit any component identifier listed the following table will beused to determine the width and length of pads.The solder paste for pads will be equal to the land size.The Soldermask relief between pads must be preferred .008, acceptable.006, minimum acceptable .004

Zmax = T + Jh Max + Jt MaxXmax = W + 2 Js Min

Component Toe Heel SidePitch Jt Max Jh Max Jh Min0.031 0.017 0.030 0.0010.025 0.017 0.030 0.0010.019 0.020 0.026 0.0010.015 0.020 0.026 0.0010.012 0.020 0.026 0.001

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Figure 3.8.3 SQFP and QFP Land Patterns

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4.0 Design for Testability

4.1 General

A) There must be at least one testable point per every electrical net exceptwhere that added track or capacitance from the via will degrade theelectrical performance.B) It is required that every node be accessible, and the primary means ofaccessibility should be a test pad. However, any net within a through-holemounted device satisfies this requirement, since a through-hole mountingpad may serve as a test point.C) There should be one test pad at each unused IC pin to facilitate librarytesting excluding mechanical alignment pins.D) Every effort should be made to ensure that from spin to spin of theartwork, the pad locations will not change unless the designer specificallycalls out for that to happen. There may be significant production delays andcosts associated with moving test points.E) All test pads must be placed on the bottom of the board. Drop in test padsoutside of through-hole component outlines on all optionally loadedcomponents.

F) Test-Pads should be as evenly distributed across the PCB as much aspossible. Excessive pin densities in any one area will cause excessive boardflex during test which can cause component damage. A maximum pindensity of 50 pins per square inch is recommended.G) Test Points should be placed as close to the OUTPUT of a device aspossible with the shortest possible path. It is recommended that CriticalTest-Pads be positioned and connected before routing begins.

4.2 Test Pads (General)

A) Test Pads grid is variable. The spacing, center to center, between the testpoints are preferred to be on .100 centers, .075 optional, .050 minimum, .025optional, and must be solder coated.B) Test points are preferred to have center to center spacing of .100. Testpads on .025 grids are possible but require the use of .025 probes which aremore fragile and will increase the overall cost of processing.

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4.3 Test Pad Masking and Location

A) Test points are to be free of solder mask and located on the bottom sideof the PWB only.B) Edge fingers, circuit traces or SMT lands are not to be considered testpads as they provide poor contact reliability and/or may provide a “falsepositive” test result.C) All used and unused connector pins should be designated as a Test Pointto facility 100% shorts testing of connectors.D) Edge fingers that are not connected to an electrical net on the board(unused) need not have a Test Pad placed on the net if the ends of the fingersare to be solder masked during the wave solder process thereby eliminatingthe possibility of shorts between two adjacent traces.E) Care should be taken not to place Test Pads near through holecomponent lands that may be bent over (clinched leads) in themanufacturing process.F) Test Point/Pads should be placed at the end of a run of track on I/O’s andoptional RAM sockets, i.e. the last socket on the I/O bus or outputconnector, the last SIMM socket in a bank of RAMs.

4.4 Test Pads and Component Clearances

A) Test Pads should not be located too close to solder side components. Theactual distance from the body edge of a solder side component to the edge ofa test pad depends on the component’s height. Follow the below guide fortest point spacing from solder side components.

Clearance Height of Component.050 min..075.100 min..075 but .250.200 min..250

B) Test Pads will be preferred .040 minimum in size, and acceptable .035

C) Test Pads may be placed on traces as explained below. Please note thatthe minimum requirement for this method is the Test Pad must encapsulate100% of the signal trace.

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4.5 Test Pad/Via Combination – Vias may be used as Test Padsprovided they meet the following criteria:

A) The converted via pad must be .040 diameter minimum with a preferred.013 max. plated hole.B) Via’s are preferred to be on .100 center to center spacing, if necessary.075, .050 and .025 with consideration of costsC) No solder mask material on the Test Pad via.D) Location to components must meet all the criteria outlined in Test Padsand Component Clearance section.

4.6 Power and Ground Test Requirements

A) At least four test points per ground and power planes evenly distributedacross the PCB are required for proper power and ground distribution.B) Power and Ground test points should be allocated such that no morethan 300 mA of current is conducted through any one test point.C) On dense SMT boards where power test pads are required, a larger padis preferred (i.e. .060 diameter). This will allow for larger multi-point pinsfor better power transfer.

5.0 Deliverable checklists

5.1 Deliverables from PCB Design Cad Supplier:

PRODUCT NAME_____________ REV LEVEL TO BE ASSIGNED____

1) Photoplotting files to be submitted in Gerber Command Format.2) Photoplot files to include Job Name and Revision.3) Photplot files to have preferred composite Aperture report.4) Assembly and Drill Drawing files to be in .DXF format for Autocad.5) SMT Design land patterns and design rules per IPC-SM-782A Standard.6) Silkscreen symbols such as: part number, CE mark and flag “Made in USA”

logo should be included at this step.7) All SMT parts on the bottom side of board are preferred to be placed parallel

to the wave solder.8) Any SMT parts on the bottom due to height will be placed to eliminating

shadowing. Ref SM-782A courtyard outlines.9) PLOT SCALING RATIO TO BE 1:1 UNLESS SPECIFIED10) Naming of JOB FOLDER: product number and Revision.

Example: YYYYYYR1

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FILE DESCRIPTION FILE NAME

COMPLETE APERTURE REPORT FILE YYYYYYAF.REPASSEMBLY DRAWING TOP YYYYYYAT.DXFASSEMBLY DRAWING BOTTOM YYYYYYAB.DXFDRILL DRAWING WITH BOARD DIMENSIONS YYYYYYDD.DXFDRILL FILE NC (EXCELLON-COMPATIBLE FORMAT) YYYYYYDR.DRLDRILL TOOL FILE REPORT YYYYYYDR.REP

SILKSCREEN TOP YYYYYYST.PHOSILKSCREEN BOTTOM YYYYYYSB.PHO

LAYER 1 ARTWORK TOP SIDE OF BOARD YYYYYYL1.PHOLAYER 2 ARTWORK (MULTILAYER OR FOR TWO SIDED, BOTTOM SIDE OF BOARD)YYYYYYL2.PHOLAYER 3 ARTWORK (MULTILAYER) YYYYYYL3.PHOLAYER 4 ARTWORK (MULTILAYER, BOTTOM SIDE OF BOARD) YYYYYYL4.PHOLAYER_ _ _ _ ARTWORK (MULTILAYER) YYYYYYL_.PHO

SOLDERMASK TOP SIDE YYYYYYMT.PHOSOLDERMASK BOTTOM SIDE YYYYYYMB.PHO

PASTE MASK SURFACE MOUNT DEVICES TOP SIDE YYYYYYPT.PHOPASTE MASK SURFACE MOUNT DEVICES BOTTOM SIDE YYYYYYPB.PHO

X-Y LOCATIONS FOR SMD PARTS ASCII FORMAT YYYYYYXY.LSTStatistics on Layout, Connections, DRC, Padstacks, and Symbols SUMMARY REPORTJOB FILE ASCII FORMAT YYYYYYJB.JOB

The Deliverable package will consist of Gerber files for all layers, NC drill file and report, Aperture report, Drilland Assembly Drawings in DXF format, 1:1 paperplots if requested by designer, Floppy disk with ZIPPED fileand JOB file.

5.2 Deliverables to Fabrication Supplier. See checklist:

FILE DESCRIPTION FILE NAME

APERTURE REPORT FILE YYYYYYAF.REP/RPT/LSTSILKSCREEN TOP YYYYYYST.PHOSILKSCREEN BOTTOM YYYYYYSB.PHODRILL FILE NC (EXCELLON-COMPATIBLE FORMAT) YYYYYYDR.DRLDRILL TOOL FILE REPORT YYYYYYDR.REP/RPT/LSTLAYER 1 ARTWORK TOP SIDE OF BOARD YYYYYYL1.PHOLAYER 2 ARTWORK (MULTILAYER OR FOR TWO-SIDED,BOTTOM SIDE OF BOARD)YYYYYYL2.PHOLAYER 3 ARTWORK (MULTILAYER) YYYYYYL3.PHOLAYER 4 ARTWORK (MULTILAYER, BOTTOM SIDE OF BOARD) YYYYYYL4.PHOSOLDERMASK TOP SIDE YYYYYYMT.PHOSOLDERMASK BOTTOM SIDE YYYYYYMB.PHOSTENCIL PASTE MASK SURFACE MOUNT DEVICES TOP SIDE YYYYYYPT.PHOSTENCIL PASTE MASK SURFACE MOUNT DEVICES BOTTOM SIDE YYYYYYPB.PHODRILL DRAWING XXXXXX-XXXRX.dwgPALLET DRAWING XXXXXX-XXXRX.dwgREADME TXT FILE (if applicable) XXXXXX-XXXRX.txt

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5.3 Deliverable to Assembly Supplier. See checklist:

FILE DESCRIPTION FILE NAME

X-Y LOCATIONS FOR SMD PARTS ASCII DOS FORMAT YYYYYYXY.LSTASSEMBLY DRAWING TOP SIDE XXXXXX-P1RX.dwgASSEMBLY DRAWING BOTTOM SIDE XXXXXX-P2RX.dwgBILL OF MATERIALS XXXXXX-XXXRXAPERATURE (LIST) FILE REPORT YYYYYYAF.REP/RPT/LSTAPERTURE REPORT FILE YYYYYYAF.REP/RPT/LSTSILKSCREEN TOP YYYYYYST.PHOSILKSCREEN BOTTOM YYYYYYSB.PHOSTENCIL PASTE MASK SURFACE MOUNT DEVICES TOP SIDE YYYYYYPT.PHOSTENCIL PASTE MASK SURFACE MOUNT DEVICES BOTTOM SIDE YYYYYYPB.PHOPALLET DRAWING XXXXXX-XXXRX.dwgREADME TXT FILE (if applicable) XXXXXX-XXXRX.txt

EXAMPLE OF CAD DATA FORMAT FOR MACHINE PROGRAMMING.

Ref. Des. Part # Part Type X Coord. Y Coord. Rotation Top/BotC1 123-456 0603 1.250 3.125 0.0 TOP

R21 234-567 1206 2.250 5.500 90.0 TOPQ2 859-712 0603 1.175 8.750 270.0 BOT

C22 758-821 0603 1.250 1.125 90.0 BOTL1 357-956 1812 2.500 1.250 180.0 TOP

X-Y Data should include Fiducials and Bad Sense marks. Also step & repeatinfo if not already recorded on a pallet drawing.

Revision HistoryRev Reason for change Changed by DateA Initial release B. LeBlanc 3/7/00B 1. Restructure CAD Data Format 2. Change global fids to

PCB Bad Sense Marks. 3. Single local fid not acceptableB. LeBlanc 5/4/00

C Add Hole size to tooling hole requirements B. LeBlanc 5/16/01