COEN6511 LECTURE 3users.encs.concordia.ca/~asim/COEN 451/Lectures/W_12/L12... · Web viewN S Area Delay, ps 1 N=7 2.73 500 um2 189 2 N=3 10 100 um2 300 3 N=1 1000 1 um2 10,000 Criteria

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Driving high loads

On the chip, there are many situations that we have to drive large loads. Some of these loads require special attention such as the clock distribution network, or the output pad drivers. The figure below shows the arrangement of the PADs and the VDD and Gnd lines. In here there is only one VDD and One Ground, usually there are many more and they are well distributed all around the chip.

For example if we take the output pad driver which is a large load and see how can we design it.

Example:

Consider a pad and driver circuit, pay particular attention to the size of the pad and the driver.

Page 1 of 13 Lecture#12 Overview

If we take the cross section of the pad, we get:

1. A two metal layers circuit.

2. A two metal layers circuit with space for pad.


The area of the pad is 10,000um2

The pad is made up of level-2 metal with capacitance of 18aF/ um2

Total capacitance of pad = 0.18pFThis is not considering the wire and the solder.

Consider the clock distribution tree network,

The length covered by the clock distribution is a significant amount. How do we drive this network? For the clock we have a special design due to special requirements but generally for large loads we design a tapered buffer:Assume the small buffer driving a large load then the delay is calculated as:

fan out

If fan out is 10,000 then This delay is un acceptable for most applications

The solution to the problem of driving large loads from a small driver is solved by using Tapered Buffers.


Tapered buffers or drivers

1. Assume that the scaling factor S is uniform2. Assume for the time being that load capacitance of each stage can be represented

by its input capacitances ( gate capacitance) of each inverter

We then have:

That is, we neglect the Cdrains (diffusion capacitance and routing capacitances. This is over-simplification but easier to show the design, real designs particularly in sub micron domain, the drain capacitances can not be ignored and this will be treated later).

, CL is the load capacitance, Cin is the input capacitance of the smallest inverter

in the circuit, Y=fan-outThen, , N is the number of inverters and S is the scaling factor.

Total delay T = N * S *


What is the scaling factor that gives minimum delay and what is that delay?

for minimum delay: dT/dS= 0, hence ,

Optimum scaling factor for minimum delay is Sopt=e

T = N * Sopt *

Example

Design a buffer driver to drive a 3pF load, with an initial Cg for small inverter of 3fF and =10ps.

Optimum delay S=e

Assume Cox=3.5fF/um2,

Assume Wp=2Wn,


or

Assume a 0.5um process, L=0.5um.

WN of N = 210umWP of P = 420um

N PN 210 420

N-1 77 154N-2 28 56N-3 10.6 21.2N-4 4 8N-5 1.5 2N-6 0.5 1

Delay=

Initially, T= =

Area of last stage = 3 x Ln Wn= 3 x 210 x 0.5= 315um

Similarly, area for previous stages is calculated and the total area is found to be about 500um2.


Design techniques

**Please note, as a first approximation, now that we have the initial sizes. Now we can calculate the drain capacitances and take it into account in our intermediate loads, probably 2 or 3 iterations are required to come to convergence**

Example

Use 3 stages for the previous buffer and comment on the delay and area.

N=3, Y=1000, S=10

or

Wn3=58um Wp3=116umWn2=5.8um Wp2=11.6umWn1=0.6um Wp1=1.2um

Delay = N * S * 3 * 10 * 10ps 300ps

Area = (29+2.9+3) x 3 = 100 um2

N S Area Delay, ps1 N=7 2.73 500 um2 1892 N=3 10 100 um2 3003 N=1 1000 1 um2 10,000

Criteria to consider when choosing right driver are Power(P), Delay(D) and Area(A) or PD (power delay), AT or AT2. In this case if we choose AT, the 3 stage driver gives a better performance.


The layout for a driver is done in such a way so as to reduce the area. An example of a large transistor design showing only diffusion and poly layers is shown below.

Another transistor design including the VDD and GND is shown below.


A PAD and its driver is shown below, to indicate all the interconnection and the relative sizes of the PAD and the Driver.


Input protection circuitsThe gate of a cMOS device appears like a small capacitance in order of few fF with a small leakage voltage less than pA. Without protection the cMOS transistors can be damaged with electrostatic discharges ( sometimes permanently). The protection circuitry lowers the input resistance from 1014

to1016. To 1010 ohm. The decrease in resistance is of little consequence in digital circuitry.The principla in designing the protection circuitry is to ensure that the voltage applied to the gate is limited by the protection device.

Electric-field at which oxide breaks down is about 5 x 106 V/CmFor our technology, ( CMOSIS process technology TOX=9.6 10-9 nm)

Voltage at break down point = , for a power supply of 3.3V.

For this reason, a protection circuitry is essential.

Most protection circuitry is based around two principles.1. Punch through ( Source to drain)2. Avalanche ( drain diffusion to substrate)

In punch through due to high voltage the depletion region is extended until it reaches the source where current can flow freely, only limited by the external resistor.In Avalanche, due to the large electric field applied to the drain the electric field built up will accelerate the electrons sufficiently to ionize neutral silicon atoms. This process continues, current flows freely from drain to diffusion, only limited by external circuitry.

1 Punch Through 2. Avalanche

Protection circuitry using input resistor and reverse diode


RD is the dynamic resistance of the transistor.

Example,

Assume Vg=3.3V, Vin=5.0V, RP=500

Or

Approximation: At this stage, the transistor works like a large diode. The area of the drain has to be large to handle the large current due to the avalanche.So let 1/RD = βp (Vgsp-Vthp)or 1.7/ 1550 = 48.74 10-6 (0+0.92) W/L giving W= 12.2 um

We have used , = K’ W/L,

Vgs= 0 , Vthp = - 0.92, L=0.5, K’P = 48.74 10-6 A/V2

to determine W. CMOSIS 5B was used for this calculation .


X is the depletion layer thickness and is calculated in such a way that at a certain voltage, current goes to ground.

X = (( ) (NA + ND)/NA ND)1/2 (Φo – V )1/2

Φo, NA , ND Can be obtained from Process Technology parameters and is a constant. V is the gate input voltage.

Generally we have to protect the circuit against both negative or positive voltage surges.The circuit below is a good protection circuit that can be easily implemented in CMOS technology.


Design techniques.Use P+ and N+ guardrings around nMOS and pMOS transistors and connect them to Vdd and Gnd to reduce latch upPlace substrate and well connections close to the source of the device.

Use minimum area of either p-well or nwell depending on technology.


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COEN6511 LECTURE 3users.encs.concordia.ca/~asim/COEN 451/Lectures/W_12/L12... · Web viewN S Area Delay, ps 1 N=7 2.73 500 um2 189 2 N=3 10 100 um2 300 3 N=1 1000 1 um2 10,000 Criteria