Cmos Basic

7/31/2019 Cmos Basic

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IA E

CMOS Basics


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MOS Transistor Behavior

Saturation Region: an imperfect switch

IDS(sat) =( n/2)(VGS-Vtn)2

n-Channel saturation current

IDS(sat) =-( p/2)(VGS-Vtp)2

p-Channel saturation current

n andp = n and p channel transistor gain

VGS = gate-to-source voltageVtn and Vtp = n- and p-channel transistor threshold

n-channel transistor turns on with positive gate voltagep-channel transistor turns on with negative gate voltage

n-channel transistor passes strong 0 but weak 1

p-channel transistor passes strong 1 but weak 0


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Basic CMOS Inverter

VSS = 0V

Let:

VDD = logic 10V = logic 0

A F

1 0

10

VDD

AF = A

Mp

Mn

SwitchModel

VDDVDD

F = 1

VSS

A=0 A=1 F = 0

VSS


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CMOS Inverter Layout

F=A

VSS

N well

p+

Gate

MetalA F

n+

VDD

VSS

Metal

Metal

Gate

Polysilicon

IA E

Institute of Advanced Microelectronics

University of New Mexico

VDD

A

Contacts


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Static CMOS NAND Gate

A

B

AB

F=(A and B)

VDD

Output is 0 only when both

N-transistors are on,i.e., when A=B=1

FA

B

FA B

0 10

10 111 0

1 1 0


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NAND Gate: Symbolic Layout

VSS

A

B

A

B

AB

F

VDD

F

ContactMetal

VDD

p-diffusion

poly-Si

F

n-diffusion

A

MetalB


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Static CMOS 2-input NOR Gate

A B F

0 0

0

0

0

1

1

0

01

1 1

Output is 0 when either of the

N-transistors is on.

VDD

A

BF=(A or B)

BA

A FB


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NOR Gate: Symbolic Layout

A

B

B

F

VDD

A

VDD

VSS

A

B

F

A

BF


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Characteristics of Static CMOS Logic

Restoring logic: can cascade gates indefinitely without lossof signal level.Facilitates composition; construct complex systems from simple

components

Key to logic synthesis and silicon compilation

Static power dissipation essentially zero.Power consumed only when switching.

As a load, looks like a capacitor.High fan-out.

Fan-in limited by series transistors in NAND and NOR tree.

A safe logic family, but not the fastest or most dense.


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MOS Transistor Scalable CMOS

L = channel lengthW = channel width

p+ or n+ diffusion

Poly-Si Gate

Metal

Metal

W

VDDSaturation drain current:

VSS

L ( )22'

THGSD VVLWkI

=

ID=drain current

VGS=drain-to-source voltageVTH=threshold voltage

k=process dependent parameter

WandL are key performance parameters

Scalable design rules

= 2 x minimum feature size (critical dimension)

Layout features scale proportionally1970: = 100 m 1990: = 1 m 2000: = 0.18 m


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Layout Design RulesMinimum widths & spacing for layout elements.

Ensures device can be fabricated and will work as intended.

Specific to process. Obtain from process vendor.

2

2 2 2

2

2

Poly

N+ or P+2

2

23

Units =

1


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Why do we need Layout Design Rules?

1. Ensure adequate separation and electrical isolation between

structures on the chip.

2. Ensure adequate overlap to achieve correct alignment.

Lithographic fabrication processes have limits:

Optical limits of resolution

Limits of alignment precision

Diffusion profiles, continued diffusion

Errors in coverage, edge failure, e.g. metal plugs in vias

Design rules act as a contractbetween designer andfabrication house:

If the design rules are obeyed, the fab guarantees the chip will

function correctly on the test signals provided.


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Some Factors Affecting Inverter Performance

VDD

Contact resistanceChannelR & C

Gate

Resistance

InLoad

Capacitance

Gate Capacitance

Contact resistanceChannelR & C

VSS


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Inverter Switching Characteristics

In

VDD VDD

Intime0

Out

Temporal:Channel resistance

and parasitic

capacitance produceRC delay

VDD

0Out

Propagation

Delay

VDD

VDD/2

Input/Output characteristic:Balance n- and p-channel gains to

switch states at VDD/2

Vin

VoutVDD


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Cell Layout Performance Issues

Resistance of a conductor (metal, poly) is proportional toaspect ratio (L/W: ohms/square).

Capacitance of a conductor is proportional to area.

To increase speed and drive power of a transistor, increasethe channel width. Also increases power consumption.

Use plenty of contacts to VDD and VSS to reduce power

supply and ground bounce (noise).

Transistor sizing

p-channel resistance > n-channel resistance

Hole mobility < electron mobility For symmetric switching, make p-channel wider than n-channel.


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Circuit Performance Estimation

Actual performance measures must consider layout.

Pre-Layout, Post-SynthesisSimple circuit models, ignore interconnects

e.g. use fan-in and fan-out to estimate delays

Post-Layout

Use SPICE to accurately model performance

Use Spice Parameter Extraction to get parasitic parameters from:

1. Layout files

2. Process description


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Simple Memory Circuit: D Latch

0

1

S

Clock

QD

Critical Parameters

to Guarantee Valid

Data is Latched

tSU = Setup Time

Time before clockwhen input must be

stable

tH = Hold Time

Time after clock when

input must be stable

Clock

tSU tH

D

Q


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Positive Edge Triggered D Flop-Flop

Input and output separated in time.

0

1

S

Clock

D0

1

S

Clock

Slave

QMQ

D Q

Master

Clock

QM

Q


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Synchronous Sequential Logic

State

Register

Next

State

Logic

Output

Logic

Inputs

State

OutputsControl

Signals

Clock Next state = f(current state, inputs)

Controls signals stabilize on low clock periodNew state latched in falling clock edge

D Q

Clock

State n+1 State n+2State n State n+3State Vector

Next-State

Logic


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Standard Logic CellsHand layout of a complex chip is tedious and expensive.

Optimal performance requires careful consideration of topology, fan in and fan out.

Transistors must be sized for each case.

Instead, divide design into standard set of logic cells.

Custom design, layout and optimize each cell.Design cells so they can be tiled to produce complex designs.

May be parameterized by drive strength (fanout)

Physically designed to same height, so they can be abutted.

Some typical standard logic cells

0

1

S

D Q

AND-OR-Invert BufferMux

Flip-Flop


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CMOS Summary

Silicon CMOS is the preferred logic family today.

Complementary property gives balanced switching, low power.

Excellent noise immunity. Restoring logic allows gates to be cascaded indefinitely.

Increasingly, digital CMOS is available as standard cells.

CMOS Standard cells enable automatic circuit synthesis and

semi-custom design.

Full custom designers optimize the cells at layout level.

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Cmos Basic