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CHAPTER 7
MATRIX CONVERTER AS A MULTILEVEL INVERTER
FOR DSTATCOM APPLICATION
7.1 INTRODUCTION
The traditional way of maintaining power quality in a power system
is to use banks of inductors and capacitors. Due to the development of
technology, fast acting voltage source and current source converters based
compensating devices have replaced the inductor and capacitor banks. The
converter-based devices operate very fast but have high switching losses due
to a number of power electronic switches in them. One such converter-based
compensator in the transmission level is the STATCOM and in the
distribution level is the DSTATCOM. In general, a DSTATCOM uses a
two-level VSCs. The literature reports that the Total Harmonic Distortion
(THD) of the two-level inverter’s output current is more than that of three-
level inverter or the multilevel inverter (Rodriguez et al 2002, Yu et al 2004,
Munoz et al 2010 and Zaveri et al 2012). For reducing the THD, some
researchers have proposed multilevel inverters like diode-clamped multilevel
inverters and cascaded multilevel inverters for the DSTATCOM application
(Wen et al 2007, Sirisukprasert 2004 and Munoz et al 2012). Although the
multilevel inverter reduces the THD as compared to the two level inverters, it
requires complicated switching algorithms and has capacitor voltage
balancing problems and increased switching losses. In this thesis, the Matrix
Converter (MC) is used as a multilevel inverter for the DSTATCOM
133
application. The MC is an AC-to-AC converter, which has low-complexity
switching scheme. This chapter investigates the matrix converter based
DSTATCOM for reactive power compensation in the MATLAB /
SIMULINK environment.
7.2 PROBLEM FORMULATION
A DSTATCOM is a fast acting shunt connected custom power
device used in the distribution system. The VSC or current source converter is
the important element in it. For high-voltage distribution system, the
DSTATCOMs are designed using a two-level VSC and the transformer at the
output side to meet the desired voltage profile. For high power application,
the VSCs are connected in parallel to the DC bus. This type of connection
requires a transformer with multiple secondary windings, which increases the
complexity of the power system. Further, the transformer increases the overall
cost and losses in the system and may saturate when the load draws any DC
current. The efficiency of the system is also low due to the increased
switching losses. Generally, the use of a two-level inverter requires a filter
circuit for reducing the THD at the output.
The use of multilevel inverters like the diode-clamped, the
cascaded and the flying capacitor types reduces the THD at the output without
the use of bulk filters. The flexibility of the multilevel inverter is improved by
increasing the number of possible operating states; consequently, all the
devices are controlled individually. Use of a multilevel inverter reduces the
transformer voltage ratio and it may be possible to connect the DSTATCOM
directly to a higher voltage system. When the diode-clamped multilevel
inverter is used for the DSTATCOM application, it gives rise to capacitor
unbalancing problem. In addition, it requires a clamping diode to clamp the
voltage across the switches (Sirisukprasert 2004, Xu et al 2008). When a
cascaded multilevel inverter is used with a single DC-link capacitor for the
134
DSTATCOM application, a transformer is required for connecting the
cascaded inverter structure to the distribution systems. Alternatively, a
separate cascaded multilevel inverter module with separate DC-link
capacitors for each phase can be used without the transformer. However, this
arrangement requires a complex DC-link voltage regulation loop whose
complexity increases with the increase in the number of H-bridge modules.
Further, connecting separate DC sources between the two converters in a
back-to-back arrangement such as in the UPFC and the UPQC is not possible
as a short-circuit occurs when the two back-to-back converters are not
switched ON. In addition to the reactive power exchange, the power pulsation
takes place at twice the output frequency for each H-bridge inverter. This
necessitates the over-sizing of the DC-link capacitors (Peng et al 1998 &
Shukla et al 2007). On the other hand, the use of a flying capacitor multilevel
inverter requires the simplest DC-link voltage regulation loop as compared to
other multilevel inverters. Further, it does not require a number of isolated
power supplies as required in the case of the cascaded H-bridge multilevel
inverters. Its DC-link capacitor control loop is as simple as the conventional
two-level inverter and is independent of the number of output voltage levels.
The main limitation of the flying capacitor multilevel inverter is that it
requires a large number of capacitors and the control is inefficient. To make
voltage control more efficient a simple DC-link is used (Shukla et al 2005,
Shukla et al 2007). However, multilevel inverter topologies for the
DSTATCOM applications require more number of switches, which increases
the switching losses and complexity of the switching algorithm.
To overcome these drawbacks in the multilevel inverter, a matrix
converter based DSTATCOM is proposed. The performance of this
DSTATCOM is studied for a simple switching algorithm. The HCC switching
algorithm is used in which the number of switches conducting at any time is
135
three and is less than the number of switches conducting at any time in a
multilevel inverter.
7.3 SYSTEM CONFIGURATION USING MATRIX
CONVERTER TOPOLOGY
Figure 7.1 shows the single line diagram of a DSTATCOM using
the matrix converter as a multilevel inverter.
Figure 7.1 Single line diagram of the DSTATCOM using the matrix converter as the multilevel inverter
The matrix converter topology for the three-level operation uses 18
switches whereas the diode clamped and the cascaded multilevel inverters for
the same level require 12 switches. However, the number of switches
conducting at any point of time in the matrix converter is less than the number
of switches conducting in the multilevel inverter. Thus, the matrix converter
as a multilevel inverter has reduced switching losses. It is also to be noted that
two capacitors are used in this type of inverter topology to achieve the three-
level of operation. It is a challenge to balance the voltage across these two
C1
Matrix Converter as Multilevel Inverter
Line Vs
LOAD1
LOAD2
C2
Bus
SW
136
capacitors. The proposed switching strategy overcomes this challenge.
Figure 7.2 shows the matrix converter having three arms, with each arm
having three sets of back-to-back connected switches (Cha 2004).
Figure 7.2 Matrix converter
The space vector based HCC switching algorithm is used. The
DSTATCOM is connected to the grid through a coupling transformer, as in
the case of a two-level inverter based DSTATCOM. The robustness of the
DSTATCOM controller is studied for load variations.
7.4 CONVENTIONAL HCC FOR THE PROPOSED MATRIX
CONVERTER TOPOLOGY
Section 4.4 had discussed the fundamentals of the Hysteresis
Current Control (HCC) technique for a two-level inverter. To apply the
LLc
Vc
Power Circuit
C1
C2
SC1A
SC2A
SNA SNC
SC1C
SC2C
SC1B
SC2B
SNB
LLa LLb
RLa RLb
Va Vb
3-ph Load
RLc
137
conventional HCC for the proposed matrix converter topology, two hysteresis
bands are used to maintain the error in the current to lie within the band,
whereas in the two-level inverter only one band was used. The outer and inner
bandwidths are selected as and /2 respectively. If the error in current,
( = ), crosses the upper limit of the outer band, + /2, the lower
switch of the respective phase is turned ON, such that the phase is connected
to the neutral and hence the current in the phase starts decreasing. When the
error in current, , crosses the lower limit of the outer band, /2, the
upper switch of the respective phase is turned ON, such that the phase get
connected to the capacitor C1 and the current in the phase starts to build up
rapidly resulting in the slope of the error in current, , being high. If the error
in current, , crosses the upper limit of the inner band, + /4, the middle
switch of the respective phase is turned ON so that the respective phase is
connected to the capacitor C2. At this instant, only half of the total voltage is
applied to the phase and hence the slope of the error in current will be low. By
doing so, the actual current is made to follow the reference current and hence
maintain the errors within the band limits. It should be noted that at any instant
of time, only one switch is conducting in any phase.
7.5 SPACE VECTORS FOR THE PROPOSED MATRIX
CONVERTER TOPOLOGY
Figure 7.3 shows the matrix converter based DSTATCOM
connected to the grid. Equations (4.7) to (4.10), given in section 4.5, that
govern the VSC based DSTATCOM are applicable for the matrix converter
based DSTATCOM too. However, the technique for applying the switching
vectors differs from the two-level VSC based DSTATCOM.
138
Figure 7.3 Grid connected matrix converter based DSTATCOM configuration
For an N-level inverter, switching vectors are possible. Hence,
for a three-level inverter, 27 switching vectors are possible. For these
switching states, the space vector diagram will be a concentric hexagon, as
shown in Figure 7.4. It is to be noted that the outer hexagon represents 12
active switching vectors; the inner hexagon represents 12 active switching
vectors and the origin represents 3 zero vectors. When the switching vectors
from the outer hexagon are used, voltage across both the capacitors C1 and C2
are applied to the load. Hence, there is no need to balance the capacitors in
this case. In the inner hexagon, each corner represents two active vectors. If a
particular switching vector is applied from the inner hexagon, it charges one
capacitor say C1 and discharges the other capacitor say C2. To charge the
capacitor C2 and discharge capacitor C1, the other switching vector from the
same corner of the inner hexagon is applied. A reference voltage of Vdc/2 is
set for each capacitor along with a tolerance bandwidth of Vdc/2. When the
actual capacitor voltage exceeds the tolerance band limit, the other switching
vector from the same corner of the inner hexagon is applied to keep the
capacitor voltage within the tolerance band. This technique helps in balancing
the capacitor voltages.
ica
icb
icc
Lf
Lf
LfRf
Rf
Rf
isa isb isc
vsa
vsc
vsb
iLa iLb iLc
C1
C2
MATRIX CONVERTER GRID
A
B
C
139
Figure 7.4 Space vector diagram for the matrix converter
7.6 SPACE VECTORS BASED HCC FOR THE MATRIX
CONVERTER BASED DSTATCOM
When the conventional method of hysteresis current control is used,
each phase of the inverter leg is controlled independently and hence the
switching frequency of the inverter goes abnormally high, which is not
desirable. Hence, in this section, a new vector based HCC is proposed to
overcome the problem of high switching frequency. If the actual current
crosses the tolerance region along a particular axis, a vector with an opposite
component along the same axis is applied, so that the actual current is brought
back into the tolerance region. Figure 7.5 shows the error region represented
in the frame around the actual current. For instance, if the actual current
hits the tolerance region on the top side (or bottom side), a vector with smaller
(or larger) component is applied, thus bringing back the actual current into
the tolerance region and maintaining a minimum slope in current error.
Similarly, if the actual current hits the tolerance region on the right (or left)
side, a vector with larger (or smaller) component is applied. In the
remaining cases, zero vectors are applied to reduce the switching losses.
( )
( )
( )
V(2)
V(2)
V(2)
V(2)
140
Figure 7.5 Error regions in the frame
It can be observed from Figure 7.6 that there are nine discrete levels
along the -axis and five discrete levels along the -axis. Hence, to identify
the region of the error in the current vector, an eight-level hysteresis
comparator HC in the -axis and a four level hysteresis comparator HC in
the -axis are used. Based on the output of the comparators HC and HC ,
optimal switching vectors are selected, as shown in Table 7.1. The switching
states corresponding to these vectors are given in Appendix 4. Figure 7.7a
shows the five discrete levels along the -axis and Figure 7.7b shows the
implementation of four level hysteresis comparator in the -axis. In the same
way, the eight-level hysteresis comparator is implemented along the -axis.
iref io
ie
BW
/6
BW
/3
141
Figure 7.6 Discrete levels in the frames
Table 7.1 Selection of the switching vectors based on the output of the comparators
DD 0 1 2 3 4
0 17 16 13 12 91 17 16 13 12 92 17 16 14,15 12 93 20 18,19 14,15 10,11 8 4 20 18,19 25,26,27 10,11 8 5 20 22,23 25,26,27 6,7 86 21 22,23 2,3 6,7 57 21 24 1 4 58 21 24 1 4 5
D =1 D =2 D =3 D =4 D =5 D =6 D =7 D =8
D =3
D =2
D =1
D =0
D =4
D =0
142
(a) Five discrete levels in the -axis
(b) Four hysteresis comparators in the -axis
Figure 7.7 Implementation of the hysteresis comparator in the -axis
The switching vectors are chosen such that the applied vector is
nearer to the error in current. Hence, as per Equation (7.1), which is derived
from Equation (4.15), the slope of the error in the current vector will be
minimized.
= (7.1)
10
23
4
{ }
1
2
3
401
01
01
01
D{ }
1 > 2 > 3 > 4
143
It should be noted that a small change in the error in current vector,
, is maintained to follow the reference current to achieve the minimum
switching frequency and hence reduce the losses. An optimal bandwidth is
selected considering the switching frequency and ripple in the output current.
The use of the matrix converter as a three-level inverter for
DSTATCOM application has many advantages. In the case of a two-level
inverter, if the reference voltage vector, Vn*, is in a particular sector, two
active vectors and one zero vector are to be used to bring the error in current
back to the tolerance region. In such a case, when the switching changes from
the active vector to the zero vector, a voltage stress of (Vdc – 0) is experienced
by the switch. However, in the case of a three-level inverter, if the reference
voltage vector Vn* is in a particular sector say sector I (S-I) as shown in
Figure 7.8, two active vectors of length Vdc, one active vector of length 3/2
Vdc from the outer hexagon and two active vectors of length Vdc/2 from the
inner hexagon and one zero vector out of the three zero vectors are used to
bring the error in the current back to the tolerance region. When the switching
state varies from the outer hexagon vector to the zero vector, a voltage stress
of ( 0) and ( 32 0)are experienced by the switches. When the
switching state varies from the inner hexagon vector to the zero vector, a
voltage stress of ( /2 0) is experienced by the switches. When the
switching state varies from the outer hexagon vector to the inner hexagon
vector, a voltage stress of ( 2 ) and ( 32 2) are
experienced by the switches. When the switching state varies from one outer
hexagon vector to another outer hexagon vector, a voltage stress of
( 32 ) is experienced by the switches.
144
Figure 7.8 Magnitude of the voltage vectors in sector I
Hence, except for the first change in the magnitude, all other
changes in the magnitude of the voltages are considerably less when
compared to a two-level inverter. The zero vector V0A (AAA) is chosen if the
previous active vector is any one of the vectors AAB, AAC, CAA, BAA,
ABA, ACA; zero vector V0B (BBB) is chosen if the previous active vector is
any one of the vectors ABB, BBC, BAB, CBB, BBA, BCB; zero vector V0C
(CCC) is chosen if the previous active vector is any one of the vectors BCC,
ACC, CBC, CAC, CCB, CCA.
7.7 SIMULATION STUDIES
The performance of the matrix converter based DSTATCOM for
load variation is studied with MATLAB simulation. The system consists of a
distribution bus modeled as a Thevinin’s equivalent voltage source, two RL
loads and a DSTATCOM. Load 1 is connected to the system permanently
whereas Load 2 is removed from the system at time t = 1 s and again
connected to the system at time t = 2 s. As both the loads are of RL type, the
system requires both real and reactive powers. When the DSTATCOM is
( )
( )
( )
Vdc/2
Vdc/2
Vdc
Vdc
3/2 Vdc
S-I
145
used, the source supplies only the real power to the load and the DSTATCOM
supplies the reactive power to the load. If the load draws the reactive power
from the source in addition to the real power, the source has to supply more
reactive component of current, which reduces the power factor on the source
side. To overcome this issue, the matrix converter based DSTATCOM is used
to supply the reactive power to the load and its performance is studied in
simulation for the above said load variation.
Figures 7.9 to 7.21 show the simulation results. Figure 7.9 shows
the real and reactive power supplied by the DSTATCOM. It is noted that the
DSTATCOM supplies only reactive power of 5 kVAR from the time t = 1 s to
t = 2 s and the rest of the time it supplies reactive power of 10 kVAR.
Figure 7.10 shows the real and reactive power supplied by the source. It is
clear that the source does not supply any reactive power to the system.
However, it supplies the real power of 15 kW when both the loads are
connected to the system and supplies the real power of 1 kW when only the
Load-1 is connected to the system. As the source supplies the entire real
power to the load, its current is in phase with its voltage, as shown in Figure
7.11. For a clearer view, Figure 7.12 shows the variation of source voltage
and current for a reduced time scale. As the source supplies the load active
power, the DSTATCOM should supply the load reactive power. Figure 7.13
shows the reactive power requirement of the load and the reactive power
supplied by the DSTATCOM. It is found that the load demand of reactive
power is fully supplied by the DSTATCOM. When the DSTATCOM
supplies the reactive power to the load, it injects the current in quadrature
with its voltage, as shown in Figure 7.14. Figures 7.15 and 7.16 respectively
show the variations of the phase A current in the DSTATCOM and in the
source. Figure 7.17 shows the variations of the three-phase voltages and
currents of the DSTATCOM. For improved visibility, the time scale is
reduced in Figure 7.18 for observing the variations of the three-phase voltages
146
and currents of the DSTATCOM. When the DSTATCOM is operated to
exchange only the reactive power with the system, its DC bus voltage should
be maintained constant. Figure 7.19 shows that the actual DC bus (made up of
two capacitors) voltage (Vdc) follows the reference voltage Vdc Ref = 1300 V
and hence the DC bus voltage is constant. This is achieved by maintaining
each capacitor voltage at its reference voltage of 650 V. Figures 7.20 and 7.21
show the variation of the voltage across the capacitors C1 and C2 respectively.
Hence, the space vector based HCC for the matrix converter based
DSTATCOM achieves its control objective.
Table 7.2 Simulation parameters for the matrix converter based DSTATCOM
Line voltage (V) 400
Source Resistance ( ) 0.01
Source Inductance (mH) 3
VSC Filter Inductance (mH) 5
Load-1 ( ) 1 + j34.55
Load-2 ( ) 10+ j3.14
Capacitance of DC Capacitors (C1, C2) (µF) 330
DC Capacitor Reference Voltage (V) 1300
Eight-level Hysteresis Comparator
1 0.02
2 0.04
3 0.06
4 0.08
5 0.10
6 0.12
7 0.14
8 0.16
147
Figure 7.9 Real and reactive powers supplied by the DSTATCOM
Figure 7.10 Real and reactive powers supplied by the source
0 0.5 1 1.5 2 2.5 3-2
-1.5
-1
-0.5
0
0.5
1
1.5x 10
4
Time (S)
P
Q
0 0.5 1 1.5 2 2.5 3-0.5
0
0.5
1
1.5
2
2.5
3
3.5x 10
4
Time (S)
P source
Q sourcs
148
Figure 7.11 Source voltage and current variations
Figure 7.12 Source voltage and current variations with reduced time
scale
0 0.5 1 1.5 2 2.5 3-400
-300
-200
-100
0
100
200
300
400
Time (S)
V source
I source
0.8 0.85 0.9 0.95 1 1.05 1.1
-300
-200
-100
0
100
200
300
Time (S)
I source
V source
149
Figure 7.13 Reactive power variation of the load and the DSTATCOM
Figure 7.14 Voltage and current variations of the DSTATCOM
0 0.5 1 1.5 2 2.5 3-1.5
-1
-0.5
0
0.5
1
1.5
2 x 104
Time (S)
Q L = QS
0.8 0.85 0.9 0.95 1 1.05 1.1 1.15 1.2
-300
-200
-100
0
100
200
300
Time (S)
I dstatcom
V dstatcom
150
Figure 7.15 Current variation in phase A of the DSTATCOM
Figure 7.16 Variation of the source current in phase A
0 0.5 1 1.5 2 2.5 3-40
-30
-20
-10
0
10
20
30
Time (S)
0 0.5 1 1.5 2 2.5 3-60
-40
-20
0
20
40
60
80
Time (S)
151
Figure 7.17 Three-phase voltage and current variations in the DSTATCOM
Figure 7.18 Three-phase voltage and current variations in the DSTATCOM with reduced time scale
1 1.2 1.4 1.6 1.8 2 2.2-400
-300
-200
-100
0
100
200
300
400
Time (S)
Iabc dstatcom Vabc dsta tcom
0.8 0.85 0.9 0.95 1 1.05 1.1
-300
-200
-100
0
100
200
300
Time (S)
Vabc dstatcomIabc dstatcom
152
Figure 7.19 DC bus (Vdc1+Vdc2) voltage
Figure 7.20 DC Capacitor-1 voltage
0 0.5 1 1.5 2 2.5 3-200
0
200
400
600
800
1000
1200
1400
1600
Time (s)
Vdc Ref
Vdc
0 0.5 1 1.5 2 2.5 3-100
0
100
200
300
400
500
600
700
800
Time (s)
Vdc1 Ref Vdc1
153
Figure 7.21 DC Capacitor-2 voltage
7.8 SUMMARY
In this chapter, a new converter topology with the matrix converter
is proposed for the DSTATCOM. This matrix converter is operated as a
multilevel inverter and is used in the DSTATCOM application instead of the
two-level VSC. The SVM based hysteresis current control scheme is
proposed for the matrix converter based DSTATCOM operating in reactive
power compensation mode. In this method, the switching vectors are selected
based on the output from the multilevel hysteresis comparators. Hence, for
any sector, five non-zero active vectors and a zero vector adjacent to the
reference vector are utilized. The non-zero vectors limit the error in the
current to lie within the error band. The zero vectors reduce the rate of change
of error in the current vector. This technique results in reduced stress on the
switches when compared to the two-level inverter. The SVM based HCC
results in faster transient response. The control scheme for power quality
improvement is robust especially for reactive power compensation.
0 0.5 1 1.5 2 2.5 3-100
0
100
200
300
400
500
600
700
800
Time (s)
Vdc2 Ref Vdc2