Chapter 5

The LC-3

LC-3 Computer– Architecture

– Memory Map

– Instruction Set Architecture (ISA)• Machine Instructions

• Address Modes

• Instructions - Operate - Data Move - Control

– Programming in Machine Code

The LC-3 Computera von Neumann machine

Memory

PSW (Program Status Word): Bits: 15 10 9 8 2 1 0 | S| |Priority| | N| Z| P|

PSW

Fetch: Next Instruction from Memory (PC) (points to) next instruction PC (PC) + 1 Decode: Fetched Instruction

Evaluate: Instr & Address (es) (find where the data is)

Load: Operand (s) (get data as specified)

Execute: Operation

Store: Result (if specified)

The Instruction Cycle:

Important Registers in the CPU

• 8 General Purpose Registers (R0 – R7) – Holds Data or Addresses

• Program Counter (PC) - Points to the next instruction

• Instruction Register (IR) – holds the instruction being executed

• Memory Address Register (MAR) – Holds the address of a memory location being accessed

• Memory Data Register (MDR) – Hold the data to be written into memory or the date read from memory

• Program Status Word (PSW) – holds the status of the program being executed, including N Z P: Negative, Zero, Positive result of an operate instruction

Note: These are all 16 bit registers

LC-3 Memory Map

(64K of 16 bit words)

256 words

(We will get to theses today)

256 words

(We will get to these later)

23.5 K words

39.5 K words

512 words

LC-3 Instructions (Fig 5.3 & Appendix a) Addressing Modes

• Register (Operand is in one of the 8 registers)

• PC-relative (Operand is “offset” from where the PC points

- offsets are sign extended to 16 bits)

• Base + Offset (Base relative) (Operand is “offset” from the contents of a register)

• Immediate (Operand is in the instruction)

• Indirect (The “Operand” points to the real address of Operand

– rather than being the operand)

Note: The LC-3 has No Direct Addressing Mode

Operate Instructions

• There are only three operate Instructions: - ADD Register mode [0001 DR SR1 0 00

SR2] Register/Immediate mode [0001 DR SR1 1

imm5]

- AND Register mode [0101 DR SR1 0 00 SR2]

Register/Immediate mode [0101 DR SR1 1 imm5]

- NOT Register mode [1001 DR SR 111111]

• The Source and Destination operands are: CPU Registers or Immediate Values

LC-3 Instructions (Fig 5.3 & Appendix a) Addressing Modes

• Register (Operand is in one of the 8 registers)

• PC-relative (Operand is “offset” from where the PC points

- offsets are sign extended to 16 bits)

• Base + Offset (Base relative) (Operand is “offset” from the contents of a register)

• Immediate (Operand is in the instruction)

• Indirect (The “Operand” points to the real address of Operand

– rather than being the operand)

Note: The LC-3 has No Direct Addressing Mode

Data Movement Instructions

• Load - read data from memory to a register– LD: PC-relative mode [0010 DR PCoffset9]– LDI: Indirect mode [1010 DR PCoffset9]– LDR: Base+offset mode [0110 DR BaseR offset6]

• Store - write data from a register to memory– ST: PC-relative mode [0011 DR PCoffset9]– STI: Indirect mode [1011 DR PCoffset9]– STR: Base+offset mode [0111 DR BaseR offset6]

• Load effective address – address saved in register

– LEA: PC-relative mode [1110 DR PCoffset9]

LC-3 Instructions (Fig 5.3 & Appendix a) Addressing Modes

• Register (Operand is in one of the 8 registers)

• PC-relative (Operand is “offset” from where the PC points

- offsets are sign extended to 16 bits)

• Base + Offset (Base relative) (Operand is “offset” from the contents of a register)

• Immediate (Operand is in the instruction)

• Indirect (The “Operand” points to the real address of Operand

– rather than being the operand)

Note: The LC-3 has No Direct Addressing Mode

Control Instructions

• Go to New Location in Program – “GO TO”– BR: PC-relative mode [0000 NZP PCoffset9]– JMP: Indirect mode [1100 000 BaseR

000000]

• Trap Service Routine Call– TRAP: Indirect [1111 0000 TrapVec8]

• Jump to Subroutine (will be covered later)– JSR: PC-relative mode [0100 1 PCoffset11]– JSRR: Indirect mode [0100 000 BaseR 000000]

• Return from Trap/Subroutine– RET: No operand [1100 000 111 000000]

• Return from Interrupt (will be covered later)– RTI: No operand [1000 000000000000]

LC-3 Instructions (Fig 5.3 & Appendix a) Addressing Modes

• Register (Operand is in one of the 8 registers)

• PC-relative (Operand is “offset” from where the PC points

- offsets are sign extended to 16 bits)

• Base + Offset (Base relative) (Operand is “offset” from the contents of a register)

• Immediate (Operand is in the instruction)

• Indirect (The “Operand” points to the real address of Operand

– rather than being the operand)

Note: The LC-3 has No Direct Addressing Mode

Branch Instruction

BR [0000 nzp PCoffset9]

• Branch specifies one or more condition codes

Program Status Word (PSW):

Bits: 15 10 9 8 2 1 0 | S| |Priority| |N|Z|P|

• If the specified bit(s) is (are) set, the branch is taken:– PC is set to the address specified in the instruction

- Target (new PC) address is computed by:

adding SEXT(IR[8:0]) to the PC contents

• If the branch is not taken: - the next sequential instruction is executed (presently pointed to by the PC).

BR

+

SEXT

Jump Instruction

JMP BaseR [1100 000 BaseR 000000]

• Jump is an unconditional branch -- always taken.

• BaseR– New PC contents (an Address) is the contents

of the Base register– Allows any target address !

Example LC-3 Program

• Write a program to add 12 integers and store the result in a Register.

Compute the Sum of 12 Integers Program

• Program begins at location x3000.• Integers begin at location x3100.

R1 x3100R3 0 (Sum)R2 12(count)

R2=0?

R4 M[R1] R3 R3+R4R1 R1+1R2 R2-1

NO

YES

R1: “Array” index pointer (Begin with location 3100)

R3: Accumulator for the sum of integers

R2: Loop counter (Count down from 12)

R4: Temporary register to store next integer

Sum integers from x3100 – x310B

Address Instruction Comments

x3000 1 1 1 0 0 0 1 0 1 1 1 1 1 1 1 1 R1 x3100

x3001 0 1 0 1 0 1 1 0 1 1 1 0 0 0 0 0 R3 0

x3002 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 R2 0

x3003 0 0 0 1 0 1 0 0 1 0 1 0 1 1 0 0 R2 12

x3004 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 If Z, goto x300A

x3005 0 1 1 0 1 0 0 0 0 1 0 0 0 0 0 0Load next value to R4

x3006 0 0 0 1 0 1 1 0 1 1 0 0 0 1 0 0 Add to R3

x3007 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 1Increment R1 (pointer)

X3008 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 1Decrement R2 (counter)

x3009 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0 Goto x3004

R1: “Array” index pointer (Begin with location 3100) R3: Accumulator for the sum of integers

R2: Loop counter (Count down from 12) R4: Temporary register to store next integer

What happens at location 300A ?

LC-3 Instructions (Fig 5.3 & Appendix a) Addressing Modes

• Register (Operand is in one of the 8 registers)

• PC-relative (Operand is “offset” from where the PC points

- offsets are sign extended to 16 bits)

• Base + Offset (Base relative) (Operand is “offset” from the contents of a register)

• Immediate (Operand is in the instruction)

• Indirect (The “Operand” points to the real address of Operand

– rather than being the operand)

Note: The LC-3 has No Direct Addressing Mode

The Sum program in “binary”

x3000 1110001011111111 ;R1=x3100x3001 0101011011100000 ;R3=0x3002 0101010010100000 ;R2=0x3003 0001010010101100 ;R2=R2+12x3004 0000010000000101 ;If z goto x300Ax3005 0110100001000000 ;Load next value into R4x3006 0001011011000100 ;R3=R3+R4x3007 0001001001100001 ;R1=R1+1x3008 0001010010111111 ;R2=R2-1x3009 0000111111111010 ;goto x3004x300A 1111000000100101 ;halt

The Sum program in “hex”

x3000 E2FF ;R1=x3100x3001 56E0 ;R3=0x3002 54A0 ;R2=0x3003 14AC ;R2=R2+12x3004 0405 ;If z goto x300Ax3005 6840 ;Load next value into R4x3006 16C4 ;R3=R3+R4x3007 1261 ;R1=R1+1x3008 14BF ;R2=R2-1x3009 0FFA ;goto x3004x300A F025 ;halt

The Sum program Data in “hex”

x3100 0001 ; Loc x3100x3101 0002x3102 0004x3103 0008x3104 FFFFx3105 1C10x3106 11B1x3107 0019x3108 0F07x3109 0004x310A 0A00x310B 400F ; Loc x310B

TRAP Instruction

• Calls a service routine, identified by 8-bit “trap vector.”

• Register R7 is loaded with the incremented contents of the PC.• The PC is loaded with the address in the Trapvector Table at

position “trapvector8”• R0 is typically used for passing values between the Program and

the Trap Routine

RET [1100 000 111 000000]• When service routine is done, an RET will load R7 (the

incremented value of the PC before jumping to the TRAP routine) into the PC, and the program will continue with the next instruction after the TRAP, i.e. the program will “return” from the TRAP Routine.

Note: an RET is a JMP Base-relative with Base = R7

vector

Service routine (Partial List)

x23 input a character from the keyboard

x21 output a character to the monitor

x25 halt the program

TRAPS

See page 543.