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Introduction to Computing Systemsfrom bits & gates to C & beyond
Chapter 5Chapter 5
The LC-2 Instruction Set Architecture
Operate instructions Data Movement instructions
Control Instructions
5 - 2
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
ISA OverviewISA OverviewMemory
Address space Addressability: Word or Byte
Registers Number Type
Instructions Operations Data Types Addressing Modes
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Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
LC-2 Memory OrganizationLC-2 Memory Organizationaddressability word (16 bits/location)
address space
216 locations= 64k
29 words/page= 512
27 pages=128
page location in page
[8:0][15:9]Address [16:0]
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Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
General Purpose Registers (GPRs)General Purpose Registers (GPRs)
Registers Special “memory” that is “inside” the CPU Very fast access: 1 clock cycle. General Purpose Registers: addressable by an instrcution
(visible to the user). Other registers may not be accessible (not architectured)
LC-2 8 general purpose registers: R0,R1,...,R7
a register can hold any 16 bit pattern - I.e. data or addresses
Other special purpose registers (later)
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Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
InstructionsInstructionsTwo main parts
Opcode: specifies what the instruction does. Operand(s): what the instruction acts on Instruction sets can be complex or simple
LC-2 4-bit opcode => 16 instructions up to two sources and one destination Example:
0 0 0 1 0 1 1 0 0 1 0 1 0 0 0 0 ADD R3 R1 R4
15 14 13 12 11 10 9 8 7 6 5 2 1 0 4 3
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Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
OperationsOperationsOperate
Manipulate data directly ADD, AND, NOT
Data Movement Move data between memory and registers (CPU)
LD, LDI, LDR, LEA, ST, STI, STR
Control Change the sequence of instruction execution
BR, JMP/JSR, JMPR/JSSR, RET, RTI, TRAP
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Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
Data TypesData Types
What data types are supported by the computer
instructions? Eg. integer, floating point, BCD, character ...
LC-2: only 2's complement integers bit strings and addresses are not data types
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
Condition CodesCondition Codes
3 single-bit registers (set to 1 or cleared to 0) N: value written was negative
Z: value written was zero
P: value written was positive
Affected each time any register is written
Condition codes are read by conditional branch
instructions
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Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
Addressing Modes - 1Addressing Modes - 1Where is the operand?
The addressing modes provide multiple mechanisms for the instruction to specify the location of an operand.
Effective Address (EA) The address that is used to locate the operand.
LC-2 supports five addressing modes: explicitly in the instruction itself (immediate) in a register in memory, by specifying
the address of the operand (two modes: direct and base+offset) the address of a location that contains the address of the operand
(indirect)
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
Immediate & Register OperandsImmediate & Register OperandsImmediate
If bit 5 = 1, the value in [4:0] (“immediate”) is sign extended (SEXT) to 16 bits and added to the contents of the source register SR1 ([8:6]).
Register
if bit 5 = 0, the contents of source register SR2 ([2:0]) are added to the contents of source register SR1 ([8:6]).
In both cases, the result goes to the destination register DR ([11:9]).
opcode operands
ADD DR SR1 1 imm
[15:12] [11:9] [8:6] [5] [4:0]
ADD DR SR1 0
[15:12] [11:9] [8:6] [5] [2:0]
SR2
opcode operands
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
Memory Addressing ModesMemory Addressing ModesDirect addressing
effective address = [instruction page no.]@[page offset] note that the 9 bit page offset (=> 512 locations) is concatenated with (not
added to) the 7 bit page number (=> 128 pages)
operand location must be on the same page as current instruction
Indirect addressing
Same mechanism as above, but the calculated memory location now contains the address of the operand, (i.e. the ea is indirect). Note that the memory has to be accessed twice to get the actual operand.
LD DR page offset
[15:12] [11:9] [8:0]
LDI DR page offset
[15:12] [11:9] [8:0]
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Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
Memory Addressing Modes - 2Memory Addressing Modes - 2
Base+Offset addressing
effective address = (BaseRegister) + offset zero extend (ZEXT) the 6 bit offset ([5:0]) to 16 bits add it to the contents of the Base Register ([8:6])
differences from Direct addressing (pageoffset): base offset is added, page offset is concatenated base offset range is only 6 bits (=> 64 locations), page offset is 9 bits base offset can address any location in memory, page offset only in
current page
LDR DR BaseR
[15:12] [11:9] [8:6] [5:0]
offset
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
Operate Instructions - 1Operate Instructions - 1Arithmetic and Logic
arithmetic: add, subtract, multiply, divide (the LC-2 only has add) logic: and, or, not, xor (the LC-2 only has and, not)
LC-2: ADD, AND & NOT
0 0 0 1 0 1 1 0 1 0 0 1 0 1 0 0
ADD R3 R2
dest reg src reg src reg
R5
NOT R3 R2
dest reg src reg
1 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
Operate Instructions - 2Operate Instructions - 2Not
uses one source [8:6] register and one destination [11:9] registerbits [5:0] are all 1s.
ADD & ANDdestination register in [11:9], one source register in [8:6]other source
register operand: if bit [5] = 0, bits [2:0] specify a register for the other source
immediate operand: if bit [5] = 1, bits [4:0] specify the other source number directly, as a 5 bit
2’s complement integer, which is sign extended (SEXT) to 16 bits.
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
ADD: Two's complement 16-bit AdditionADD: Two's complement 16-bit Addition Assembler Instruction
ADD DR, SR1, SR2 ; DR = SR1 + SR2 (register addressing)ADD DR, SR1, imm5 ; DR = SR1 + Sext(imm5) (immediate addressing)
Encoding0001 DR SR1 0 00 SR20001 DR SR1 1 imm5
ExamplesADD R2,R3,R6ADD R2,R3,#1
Note: Condition codes are set
5 - 16
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
AND: Bitwise Logical ANDAND: Bitwise Logical ANDAssembler Instruction
AND DR,SR1,SR2 ; DR = SR1 AND SR2AND DR,SR1,imm5 ; DR = SR1 AND Sext(imm5)
Encoding0101 DR SR1 0 00 SR20101 DR SR1 1 imm5
ExamplesAND R2,R3,R6AND R2,R2,#0 ; Clear R2 to 0
Note: Condition codes are set.
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
NOT: Bitwise Logical NOTNOT: Bitwise Logical NOT
Assembler Inst.NOT DR,SR ; DR = NOT SR
Encoding1001 DR SR 111111
ExampleNOT R2,R6
Note: Condition codes are set.
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
Data Movement Instructions - 1Data Movement Instructions - 1Move Data
from CPU register to memory => store nominated register is Source
from memory to register => load nominated register is Destination
also to/from I/O devices (later)
LC-2 Load/Store Instructions LD, LDI, LDR, LEA, ST, STI, STR Format:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
opcode DR or SR operand specifier
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
Data Movement Instructions - 2Data Movement Instructions - 2LC-2 Load/Store Instructions
immediate: LEANo Effective Address (EA) calculation; the value (PC[15:9] concatenated with instruction[8:0]) is loaded directly into DR - i.e.
DR <= PC[15:9] @ Inst[8:0]
direct: LD & STThe EA is [15:9] from PC, [8:0] from instruction (page-offset mode)- i.e.
EA = PC[15:9] @ Inst[8:0]
DR <= Mem[PC[15:9] @ Inst[8:0] ]
indirect: LDI & SDIEA = Mem[ PC[15:9] @ Inst[8:0] ]
DR <= Mem[Mem[ PC[15:9] @ Inst[8:0] ]
base+offset: LDR & STR (BaseReg is specified by Inst [8:6]) EA = BaseReg + Zext(Inst[5:0])
DR <= Mem[BaseReg + ZEXT(Inst[5:0])]
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Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
LD: Load DirectLD: Load Direct
Assembler Inst. LD DR, LABEL ; DR = Mem[LABEL]
Encoding0010 DR page-offset9
ExamplesLD R2, param
Notes: The LABEL must be on the same memory page as the instruction.
Condition codes are set.
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
LDI: Load IndirectLDI: Load Indirect
Assembler Inst.LDI DR, LABEL ; DR = Mem[Mem[LABEL]]
Encoding1010 DR pgoffset9
ExamplesLDI R2, POINTER
Notes: The LABEL must be on the same memory page as the instruction.
Condition codes are set.
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
LDR: Load Base+IndexLDR: Load Base+Index
Assembler Inst.LDR DR,BaseR,idx6 ; DR = Mem[BaseR+ZEXT(idx6)]
Encoding0110 DR BaseR index6
ExamplesLD R2,R3,#15 ; R2 = Mem[R3+15]
Notes: The index is zero-extended to 16 bits.Condition codes are set.
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
LEA: Load Effective AddressLEA: Load Effective Address
Assembler Inst.LEA DR, LABEL ; DR = LABEL
Encoding1110 DR pgoffset9 (i.e. address of LABEL = PC[15:9] + pgoffset9)
ExamplesLEA R2, DATA ; R2 gets the address of DATA
Notes: The LABEL must be on the same memory page as the instruction. Condition codes are set.
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
ST: Store DirectST: Store Direct
Assembler Inst.ST SR, LABEL ; Mem[LABEL] = SR
Encoding0011 SR pgoffset9
ExamplesST R2, VALUE ; Mem[VALUE] = R2
Notes: The LABEL must be on the same memory page as the instruction. Condition codes are not set.
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
STI: Store IndirectSTI: Store Indirect
Assembler Inst.STI SR, LABEL ; Mem[Mem[LABEL]] = SR
Encoding0011 SR pgoffset9
ExamplesSTI R2, POINTER ; Mem[Mem[POINTER]] = R2
Notes: The LABEL must be on the same memory page as the instruction. Condition codes are not set.
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
STR: Store Base+IndexSTR: Store Base+Index
Assembler Inst.STR SR, BaseR,idx6 ; Mem[BaseR+ZEXT(idx6)]=SR
Encoding 0111 SR pgoffset9
ExamplesSTR R2, R4, #15 ; Mem[R4+15] = R2
Notes: The index is zero-extended to 16 bits.Condition codes are not set.
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
Addressing ExamplesAddressing Examples What is the EA for the following instructions?
Given:PC = x2081, R6 = x2035, LOC = x2044, Mem[LOC] = x3456
ADD R1,R3,R2Register addressing:DR = R1, SR1 = R3, SR2 = R2DR <= ?
ADD R5,R1,#15Immediate addressing:DR = R5, SR1 = R1, S2 = 15DR <= ?
LD R1,LOCDirect addressing: DR <= ?
LDI R2,LOCIndirect addressing: EA = Mem[x2044] = x3456
LDR R1,R6,#12Base+Offset addressing:EA = R6+12 = x2035 + x000C
= x2041
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
Control InstructionsControl InstructionsChange the Program Counter
Conditionally or notRemember where it was (subroutine calls)
LC-2 InstructionsBRx, JMP/JSR, JMPR/JSRR, RET, TRAP
BRx, JMP, JSR use direct addressing JMPR, JSRR use base+offset addressing
Conditional Branch: BRx
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 page offsetN Z P
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
BR: Conditional BranchBR: Conditional Branch
Assembler Inst.BR LABELBRn LABEL BRz LABEL BRp LABELBRnz LABEL BRnp LABEL BRzp LABELBRnzp LABEL
Encoding0000 n z p pgoffset9
Examples BRzp LOOP ; branch to LOOP if previous op returned zero or
positive.
Note: Branch to LABEL iff the selected condition code(s) is set
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
TRAP InstructionTRAP Instruction
Used to invoke an operating system service call Trap vectors: a list of locations of the service call routines TRAP has one operand which indexes into the trap vector;
PC is set to the value (starting point of service routine) Some special trap vectors:
* x23: input a character from the keyboard
* x21: output a character to the monitor
* x25: halt the program More details later
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
TRAP: Invoke a system routineTRAP: Invoke a system routine
Assembler Inst.TRAP trapvec
Encoding1111 0000 trapvect8
ExamplesTRAP x23
Note: R7 <= PC (for eventual return)
PC <= mem[Zext(trapvect8)]
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
Data Path - 1Data Path - 1Global Bus 16-bit connects all components is shared by all
Memory Memory Address
Register: MAR address of location to be
accessed
Memory Data Register: MDR
data loaded or to be stored
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
Data Path - 2Data Path - 2ALU & Registers Two ALU sources
source 1: register source 2: register or
instruction Result: goes onto bus,
then to DR
PC & PCMUX PC sends address to
MAR for instruction fetch PCMUX: a 4:1 mux that
selects the new PC incremented PC BR TRAP, RET or JSR (later)
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
Data Path - 3Data Path - 3
MARMUXA 3:1 mux that selects the source of MAR
Right input: direct, indirect addressing
Middle input: base+offset addressing
Left input: trap instruction
5 - 35
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
Instruction Cycle - 1Instruction Cycle - 1
Given: PC = x3456, Mem[x3456] = x6684
FetchMAR PC, PC PC+1
MDR x6684
IR MDR
DecodeControl logic processes the instruction:
0110 011 010 000100 : LDR R3 R2 4
Evaluate AddressMAR R2 + 4
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
Instruction Cycle - 2Instruction Cycle - 2
Operand FetchMDR value from memory
Execute:none for LDR
Store ResultR3 MDR