Combinational Logic Design (1) PPT

8/12/2019 Combinational Logic Design (1) PPT

1/31

9/15/09 - L12 Combinational LogicDesign Copyright 2009 - Joanne DeGroat, ECE, OSU1

Combinational Logic

Design


2/31

9/15/09 - L12Combinational LogicDesign

Copyright 2009 - Joanne DeGroat, ECE, OSU 2

Class 12-Combinational LogicOther gate types

Material from section 3-1 and 3-2 of text


3/31

Combinational Logic DesignA process with 5 steps

Specification

FormulationOptimizationTechnology mapping

Verification1st three steps and last best illustrated byexample




4/31

Functional BlocksFundamental circuits that are the base building blocks of most larger digital circuitsThey are reusable and are common to manysystems.Examples of functional logic circuits

Decoders

EncodersCode convertersMultiplexers




5/31

Where they are usedMultiplexersSelectors for routing data to the processor, memory,I/O

Multiplexers route the data to the correct bus or port.Decoders

are used for selecting things like a bank of memoryand then the address within the bank. This is also the

function needed to decode the instruction todetermine the operation to perform.Encoders

are used in various components such as keyboards.




6/31

Specifications stepWrite a specification for the circuitsSpecification includes

What are the inputs: how many, how many bits in agiven output, how are they grouped,, are they control,are they active high?What are the outputs: how many and how many bits

in a each, active high, active low, tristate output?The functional operation that takes place in the chip,i.e., for given inputs what will appear on the outputs.




7/31

Formulation stepConvert the specifications into a variety formsfor optimal implementation.

Possible formsTruth TablesExpressionsK-mapsBinary Decision Diagrams

IF THE SPECIFCATION IS ERRONOUS ORINCOMPLETE (open for various interpretation)then the circuit will perform as specified but willnot perform as desired.




8/31

Last 3 stepsBest illustrated by example

A BCD to Excess-3 code converter

BCD-to-7-segment decoder




9/31

BCD-to-Excess-3 Code converterBCD is a code for the decimal digits 0-9Excess-3 is also a code for the decimal digits




10/31

Specification of BCD-to-Excess3Inputs: a BCD input, A,B,C,D with A as themost significant bit and D as the least

significant bit.Outputs: an Excess-3 output W,X,Y,Z thatcorresponds to the BCD input.

Internal operation circuit to do theconversion in combinational logic.




11/31

Formulation of BCD-to-Excess-3Excess-3 code is easily formed by adding a

binary 3 to the binary or BCD for the digit.

There are 16 possible inputs for both BCDand Excess-3.It can be assumed that only valid BCD inputs

will appear so the six combinations not usedcan be treated as dont cares.




12/31

Optimization BCD-to-Excess-3

Lay out K-maps for each output, W X Y Z

A step in the digital circuit design process.




13/31

Placing 1 on K-mapsWhere are the minterms located on a K-Map?




14/31

Expressions for W X Y ZW(A,B,C,D) = m(5,6,7,8,9)

+d(10,11,12,13,14,15)

X(A,B,C,D) = m(1,2,3,4,9)+d(10,11,12,13,14,15)

Y(A,B,C,D) = m(0,3,4,7,8)

+d(10,11,12,13,14,15)Z(A,B,C,D) = m(0,2,4,6,8)

+d(10,11,12,13,14,15)9/15/09 - L12Combinational LogicDesign



15/31

Minimize K-MapsW minimization

Find W = A + BC + BD




16/31

Minimize K-MapsX minimization

Find X = BCD+BC+BD




17/31

Minimize K-MapsY minimization

Find Y = CD + CD




18/31

Minimize K-MapsZ minimization

Find Z = D




19/31

Two level circuit implementationHave equations

W = A + BC + BD = A + B(C+D)X = BC + BD + BCD = B(C+D) + BCD

Y = CD + CD Z = D Factoring out (C+D) and call it TThen T = (C+D) = CD

W = A + BTX = BT + BT Y = CD + T Z = D




20/31

Create the digital circuitImplementingthe second set of

equations whereT=C+D resultsin a lower gatecount.This gate has afanout of 3




21/31

BCD-to-Seven-Segment DecoderSpecification

Digital readouts on many digital products often

use LED seven-segment displays.Each digit is created by lighting the appropriatesegments. The segments are labeled a,b,c,d,e,f,gThe decoder takes a BCD input and outputs thecorrect code for the seven-segment display.




22/31

SpecificationInput: A 4-bit binary value that is a BCDcoded input.

Outputs: 7 bits, a through g for each of thesegments of the display.Operation: Decode the input to activate the

correct segments.




23/31

FormulationConstruct a truth table




24/31

OptimizationCreate a K-map for each output and get

A = AC+ABD+BCD+ABC

B = AB+ACD+ACD+ABC C = AB+AD+BCD+ABC D = ACD+ABC+BCD+ABC+ABCD

E = ACD+BCD F = ABC+ACD+ABD+ABC G = ACD+ABC+ABC+ABC




25/31

Note on implementationDirect implementation would require 27 ANDgates and 7 OR gates.

By sharing terms, can actualize andimplementation with 14 less gates.

Normally decoder in a device name indicatesthat the number of outputs is less than thenumber of inputs.




26/31

4-bit Equality CheckerSpecification

Input: Two vectors, A(3:0) and B(3:0) each

being 4-bits. The msb bits the A(3) and B(3).Output: E which has a value of 1 when A=B and0 if any bit of A/=B.Operation: Combinational logic to compare the 4

bits of A with the 4 bits of B to produce E




27/31

4-bit Equality CheckerFormulation

For each bit position A i will be compared with B i

and if they are equal, a 0 will be output. If theydiffer a 1 will be output.Thus, if any bit position indicates a 1 then thevalues are different. These 1 st level comparators

outputs can then be Ored together.The ORed output is inverted to produce a 1 whenthey are equal.




28/31

4-bit Equality CheckerOptimizationDone by implementing

two separate blocks.1st the unit MX thatcompares two bit and

outputs a 0 if they areequal, i.e., an XORoperation.




29/31

The second unitThe ME unit takes the MX outputs andgenerates a 1 when all the inputs are 0, i.e., a

NOR operation.E = (N 0+N 1+N 2+N 3)




30/31

Heirarchical RepresentationFigure 3-5 of text




31/31

Class 12 assignmentCovered sections 3-1 and 3-2Problems for hand in

3-1 and 3-3 (due Monday)Problems for practice

3-2, 3-8, 3-10, 3-11a

Reading for next class:

9/15/09 - L12Combinational Logic


Documents

Combinational Logic Design (1) PPT