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Digital Logic Design CHAPTER 4
Combinational Logic
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Combinational v.s Sequential Circuits
• Logic circuits may be combinational or sequential • Combinational circuits:
– Consist of logic gates only– Outputs are determined from the present values of inputs– Operations can be specified by a set of Boolean functions
• Sequential circuits:– Consist of logic gates and storage elements– Outputs are a function of the inputs and the state of the storage
elements• Depend not only on present inputs, but also on past values
– Circuit behavior must be specified by a time sequence of inputs and internal states
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Combinational Circuit (1/2)
• A combinational circuit consists of:– Input variables– Logic gates– Output variables
• Transform binary information from the given input data to a required output data.
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Combinational Circuit (2/2)
• Each input and output variable is a binary signal– Represent logic 1 and logic 0– There are 2n possible binary input combinations for
n input variable• Only one possible output value for each
possible input combination– Can be specified with a truth table– Can also be described by m Boolean functions, one
for each output variable– Each output function is expressed in terms of n
input variables
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Design Procedure
• Input: the specification of the problem.• Output: the logic circuit diagram or Boolean
functions.– Step 1: determine the required number of inputs
and outputs from the specification– Step 2: derive the truth table that defines the
required relationship between inputs and outputs– Step 3: obtain the simplified Boolean function for
each output as a function of the input variables– Step 4: draw the logic diagram and verify the
correctness of the design.
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Adder
• The most basic arithmetic operation is the addition of two binary digits– When both augend and addend bits are equal to 1,
the binary sum consists of two digits (1 + 1 = 10)– The higher significant bit of this result is called a
carry• A combination circuit that performs the
addition of two bits is half adder.• A adder performs the addition of three bits (2
significant bits and a previous carry) is called a full adder
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Half Adder
• Inputs: x and y• Outputs: S (for sum) and C (for carry)• The simplified Boolean functions for the two
inputs can be obtained directly from the truth table.
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Implementation of Half Adder
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Full Adder
• A full adder is a combinational circuit that forms the arithmetic sum of three input bits– It consists of three inputs and two outputs.
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Implementation of Full Adder
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Implementation of Full Adder
• A full adder can be implemented with two half adders and an OR gate
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Subtractors
• The subtraction of two binary numbers may be accomplished by taking the complement of the subtrahend and adding it to the minuend.– A – B can be done by taking the 2’s complement of B
and adding it to A; A – B = A + (-B)– 2’complement can be obtained by taking the
1’complement and adding on to the least significant pair of bits; A - B = A + (B’ + 1)
• If the minuend bit is smaller than the subtrahend bit, a 1 is borrowed from the next significant position.
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Half-Subtractor
– A half-subtractor is a combinational circuit that subtracts two bits and produces their difference. It also has an output to specify if a 1 has been borrowed.
– To perform x – y:• if x ≥ y, we have three possibilities:
– 0 – 0 =0, 1 – 0 =1 and 1 – 1 =0. – The result is called the difference bit.
• If x<y, we have 0-1, – it is necessary to borrow a 1 from the next higher stage. The 1
borrowed from the next higher stage adds 2 to the minuend bit.– With the minuend equal to 2, the difference becomes 2 – 1 =
1
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Half-Subtractor
• The half-subtractor needs two outputs:– One output generates the difference. (symbol B)– The second output, designated B for borrow.
– The Boolean functions for the two outputs:• D=X’Y+XY’ □ B=X’Y
– It is interesting to note that the logic for D is exactly the same as the logic for output S in the half-adder.
x y B D0 0 0 00 1 1 11 0 0 11 1 0 0
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Full-Subtractor
• A full-subtractor is a combinational circuit that performs a subtraction between two bits, taking into account that a 1 may have been borrowed by a lower significant stage.
• This circuit has three inputs and two outputs.– The three inputs, x, y ,and z, denote the minuend,
subtrahend, and previous borrow, respectively. – The two outputs, D and B, represent the difference
and output borrow, respectively.
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Full-Subtractor
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Full-Subtractor
• Again we note that the logic function for output D in the full-subtractor is exactly the same as output S in the full-adder.
• Moreover, the output B resemble the function for C in the full-adder, except that the input variable x is complemented
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Code Conversion
• It is sometimes necessary to use the output of one system as the input to another. – A conversion circuit must be inserted between the two
system if each uses different codes for the same information. • Thus, a code converter is a circuit that makes the two system
compatible even though each uses a different binary code.
– To convert from binary code A to binary code B, the input lines must supply the bit combination of elements as specified by code A and the output lines must generate the corresponding bit combination of code B.
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Code Conversion Example
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Maps for Code Converter (1/2)
– The six don’t care minterms (10~15) are marked with X.– Each of four maps represents one of the four outputs of this circuit as a
function of the four input variables.
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Maps for Code Converter (2/2)
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Logic Diagram for the Converter
• Reduce the number of gates used.
z = D'y = CD + C' D' = CD + (C + D)'x = B'C + B'D + BC' D' = B' (C + D) + BC' D'
= B' ( C + D) + B(C + D)'w = A + BC + BD = A + B(C + D)
– C + D is used to implement the three outputs.
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Logic Diagram for the Converter
Logic Diagram for BCD-to- excess-3 code converter
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Analysis Procedure
• The “analysis” is the reverse of “design”.• Analysis: determine the function that the circuit
implements– Often start with a given logic diagram
• First step: make sure that circuit is combinational and not sequential.– Without feedback paths or memory elements
• Second step: obtain the output Boolean functions or the truth table
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Output Boolean Functions (1/3)
– Step 1:• Label all gate outputs that are a function of input
variables• Determine Boolean functions for each gate output
F2 = AB + AC + BCT1 = A + B + CT2 = ABC
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Output Boolean Functions (2/3)
– Step 2:• Label the gates that are a function of input variables and
previously labeled gates• Find the Boolean function for these gates
T3 = F'2 T1
F1 = T3 + T2
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Output Boolean Functions (3/3)
– Step 3:• Obtain the output Boolean function in term of input
variables– By repeated substitution of previously defined functions
F1 = T3 + T2 = F'2 T1 + ABC
= (AB + AC + BC)' (A + B + C) + ABC= (A' + B' )(A' + C' )(B' + C' ) (A + B + C) + ABC= (A' + B' C' )(AB' + AC' + BC' +B' C) + ABC= A' BC' + A' B' C + AB' C' + ABC
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Truth Table
• To obtain the truth table from the logic diagram:1. Determine the number of input variables– For n inputs:• 2n possible combinations• List the binary numbers from 0 to 2n -1 in a table
2. Label the outputs of selected gates3. Obtain the truth table for the outputs of those
gates that are a function of the input variables only4. Obtain the truth table for those gates that are a
function of previously defined variables at step 3• Repeatedly until all outputs are determined
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Truth Table for Logic Diagram
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Binary Parallel Adder
• A binary adder produces the arithmetic sum of two binary numbers in parallel.
• Can be constructed with full adders connected in cascade– The output carry from each full adder is connected
to input carry of the next full adder in the chain.– An n-bit parallel adder requires n full-adder– 4-bit adder: Interconnection of four full adder (FA)
circuits.
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4-bit Adder Example
– Consider two binary number:A = 1011 and B = 0111
4-bit full-adder
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Carry Propagation
• The addition of two binary numbers in parallel implies that all the bits of the augend and addend are available for computation at the same time.
• As in a combinational circuit, the signal must propagate through the gates before the correct output sum is available in the output terminals.
• The total propagation time is equal to the propagation delay of a typical gate times * the number of levels in the circuit.
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Carry Propagation
• The longest propagation delay in a adder is the time that carry propagate through the full adders
• Each bit of the sum output depends on the value of the input carry.– The value of Si will be in final value only after the
input carry Ci has been propagated– Thus only after the carry propagate through all stages
will the last output S3 and carry C4 settle to their final steady-state value.
– C3 has to wait for C2, C2 has to wait for C1 and so on down to C0
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Carry Propagation
• The number of gate levels for carry propagation can be found from the circuit of the full-adder.
• The input and output variables use the subscript i to denote a stage in the parallel adder.
• The signals at Pi and Gi settle to their steady-state value after the propagation through their respective gates.– These two signals are common to all full-adders and
depend only on the input augend and addend bits.
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Carry Propagation
• The signal from input carry Ci to output carry Ci+1 propagates through an AND and a OR gate (2 gate levels).– For n-bit adder, there are 2n gate levels for the carry
to propagate from input to output
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Carry Propagation
• The carry propagation time is a limiting factor on the speed with which two numbers are added
• All other arithmetic operations are implemented by successive additions– The time consumed during the addition is very critical
• To reduce the carry propagation delay– Employ faster gates with reduced delays– Increase the equipment complexity
• Several techniques for reducing the carry propagation time in a parallel adder– The most widely used technique employs the principle of look-ahead
carry
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Carry Propagation & Generation
– carry generate Gi: produces a carry of 1 when both Ai and Bi are 1, regardless of the input carry Ci
– carry propagate Pi: the term associated with the propagation of the carry from Ci to Ci+1
iii
iii
BAG
BAP
iiii
iii
CPGC
CPS
1
Carry Propagate
Carry Generate
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Carry Look-ahead Generator
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Carry Look-ahead Generator
• Boolean function for output carry is expressed in sum of product– Each function can be implemented with one level of
AND gates followed by an OR gate.
• Note that C3 does not have to wait for C2 and C1 to propagate;– C3 is propagated at the same time as C1 and C2
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Carry Look-ahead Adder
– Each sum output requires two XOR gates.
– The carries are propagated through the look-ahead carry and applied as inputs to the second XOR gates
– All output carries are generated after a delay through two levels of gates• Output S1 to S3 can have
equal propagation delay times
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Decoders
• A binary code of n bits representing up to 2n distinct elements of the coded.
• A decoder is a circuit that coverts binary information from n input lines to a max. of 2n unique output lines.– May have fewer than 2n outputs if has unused or
don’t care combinations.• A n-to-m-line decoder (m ≤ 2n):– Generate the m minterms of n input variables
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3-to-8-Line Decoder
• The 3 inputs are decoded into 8 outputs– Each output representing one of the minterms of the 3-
input variables.• For each possible input combination, there is only
one output that is equal to 1– The output whose value is equal to 1 represents the
minterm equivalent of the binary number presently available in the input lines.
• The three inverters provide the complement of the inputs, and each one of the eight AND gates generates one of the minterms.
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3-to-8-Line Decoder
• A particular application of this decoder would be a binary-to-octal conversion.
• The input variables may represent a binary number and the outputs represent the eight digits in the octal number system.
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2-to-4-Line Decoder with Enable
• Some decoders are constructed with NAND gates– Since a NAND gate produce the AND operation with
an inverted output, it becomes more economical to generate the decoder minterms in their complemented form.
• An enable input can be added to control the operation– All outputs are equal to 1 if enable input E is 1,
regardless of the values of inputs A and B.• E=1: disabled
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2-to-4-Line Decoder with Enable
– When the enable input is 0, the circuit operates as a decoder with complemented outputs.• Normal decoder operation occurs only with E=0• The outputs are selected when they are in the 0 state.
Complemented outputs
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Demultiplexer
• A circuit that receives information from a single line and directs it to one of 2n possible output lines– A decoder with enable input can function as a
demultiplexer– Often referred to as a decoder/demultiplexer– The selection of a specific output line is controlled
by bit combination of n selection lines
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Demultiplexer
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Construct Larger Decoders
• Decoders with enable inputs can be connected together to form a larger decoder
• The enable input is used as the most significant bit of the selection signal– w=0: the top decoder is enabled– w=1: the bottom one is enabled
• In general, enable inputs are a convenient feature for standard components to expand their numbers of inputs and outputs
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Construct Larger Decoders
• When w = 0, the top decoder is enabled and the bottom is disabled.– Top decoder generates 8
minterms 0000 to 0111, while the bottom decoder outputs are 0’s.
• When w = 1, the top decoder is disabled and the bottom is enabled.– Bottom decoder generates
8 minterms 1000 to 1111, while the top decoder outputs are 0’s.
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Encoder
• A circuit that performs the inverse operation of a decoder– Have 2n (or fewer) input lines and n output lines– The output lines generate the binary code of the
input positions• Only one input can be active at any given time• Note that the circuit has eight inputs and could
have 28 =256 possible input combinations.– Only eight have any meaning otherwise don’t care
condition.
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Encoder
– The low-order output bit z is 1 if the input octal digits is odd.
– Output y is 1 for octal digits 2,3,6, or 7.– Output x is a 1 for octal digits 4,5,6, or 7.– Note that D0 is not connected to any OR gate• The binary output must be all 0’s in this case.
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Priority Encoder
• The type of encoder available in IC form.• An encoder circuit that includes the priority
function• If two or more inputs are equal to 1 at the same
time, the input having the highest priority will take precedence
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Multiplexer (Data Selector)
• Multiplexing means transmitting a large number of information units over a smaller number of channels or lines.
• A digital multiplexer is a circuit that selects binary information from one of many input lines and directs it to a single output lines.
• The selection of a particular input line is controlled by a set of selection lines.– Have 2n input lines and n selection lines whose bit
combinations determine which input is selected.
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Multiplexer
• For the following 2-to-1-line multiplexer:– S=0 Y = I0 ; S=1 Y = I1
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4-to-1-Line Multiplexer
• The combinations of S0 and S1 control each AND gates
• Part of the multiplexer resembles a decoder– Selection lines s1 and s0 are decoded to select a
particular AND gate.• To construct a multiplexer:– Start with an n-to-2n decoder– Add 2n input lines, one to each AND gate– The outputs of the AND gates are applied to a single
OR gate.
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4-to-1-Line Multiplexer
• The function table lists the input-to-output path for each possible bit combination of the selection lines.
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Multiplexer
• The size of a multiplexer is specified by the number 2n of its input lines and the single output line.– It is then implied that it also contains n selection
lines.• As in decoders, multiplexer ICs may have an
enable input to control the operation of the unit.
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Quadruple 2-to-1-Line Multiplexer
• Multiplexers can be combined with common selection inputs to provide multiple-bit selection logic
• Quadruple 2-to-1-line multiplexer:– Four 2-to-1-line multiplexers– Each capable of selecting one of 2 input lines– E: enable input• E=1: disable the circuit• (all outputs are 0)
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Multiplexer
– It is used for connecting two or more sources to a single destination among computer units.
– It is useful for constructing a common bus system
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Boolean Function Implementation
• If we have a Boolean function of n variables– we take n-1 of these variables and connect them to
the selection lines of a multiplexer.– The remaining single variable of the function is used
for the inputs of the multiplexer.• If A is this single variable, the inputs of the multiplexer
are chosen to be either A or A’ or 1 or 0.
• By using inputs and connection lines we can generate any function of n variables with a 2n-1-to-1 multiplexer.
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General procedure
• To implement function with a multiplexer:1. Express the function in sum of minterms form2. Assume that the ordered sequence of variables
chosen for the minterms is ABCD .., where A is the left most variable in the ordered sequence of n variables and BCD are the remaining n-1 variables.
3. Connect the n-1 variables to the selection lines of the multiplexer with B connected to high-order selection line, C to the next lower, and so on down to last variable, which is connected to the lowest-order selection line s0
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General procedure
4. Now consider the single variable A:• Since this variable I in the highest order position in the
sequence of variables, it will be complemented in minterms 0 to (2n/2)-1 (the first half in the list).
• The second half of the minterms will have their A variable uncomplemented. E.g. for a 3-variable function A,B,C : A is complemented in
minterms 0 to 3 and uncomplemented in minterms 4 to 7.
5. List the inputs of the multiplexer and under them list all the minterms in two rows.• The first row all minterms where A is complemented• The second row all minterms with A uncomplemented
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General procedure
6. Circle all the minterms of the function and inspect each column separately:• If the two minterms in a column are not circled, apply 0
to the corresponding multiplexer input.• If the two minterms are circled, apply 1 to the
corresponding multyplexer input.• If the bottom minterm is circled and the top is not
circled, apply A to the corresponding multiplexer input.• If the top minterm is circled and the bottom is not
circled, aaplly A’ to the corresponding multiplexer input.
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Boolean Function Implementation
• Implementing F(A,B,C)= ∑(1,3,5,6)with multiplexer.
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Boolean Function Implementation
• Implement the following function with multiplexer: F(A,B,C,D)= ∑(0,1,3,4,8,9,15).
