Chapter 2 CMOS Processing Supplement (I)

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Making a wafer base (a)

Use seed crystal of Si Czochralski method of crystal growth

(b)

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Slice into wafers (c)

Wafer and chips

(d)

Wafer sites (die, test)

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Process steps (A) Change surface material (B) Add material (C) Remove material (A) Change surface material

Ion implantation: impurities are implemented into surface of the wafer

Brutally forced atoms into the silicon crystal will damage the crystal lattice

To repair the crystal lattice, the wafer is annealed (heating it)

Second effect of heating: Diffusion!

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(B) Adding a layer

Epitaxial deposition: growing a new layer of Sillicon while maintaining the lattice structure -- Approach: Chemical Vapor Deposition (CVD)

Arrange for highly reactive gases to pump in. Mixture of gases reacts with each other. Reacted gases travel through the tube until they encounter wafer Silicon of the mixture condenses on the surface, giving a nice epitaxial layer

Poly-crystalline Silicon (Poly): Silicon-on-silicon

Oxide Growth: Wet oxidation, Dry oxidation Evaporation: Metallization (adding Al, Cu)

(C) Removing a layer -- Patterning silicon dioxide through Optical Lithography (transfer a pattern to a layer on a chip is called Lithography)

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In each process, certain areas are defined on chip by appropriate masks.

The integrated circuit may be viewed as a set of patterned layer of: (a) Doped silicon (b) Polysilicon (c) Metal (Al, Cu) (d) Insulating SiO2

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Use of E-beam For accurate generation of high-density patterns required in sub-micron devices, Electron beam (E-beam) lithography is used instead of optical lithography. In the following, the main processing steps involved in the fabrication of an n-channel MOS transistor on a p-type substrate will be examined.

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Fabrication of the nMOS Transistor The process starts with the oxidation of the silicon substrate (Fig. 2.4(a)), in which a relatively thick silicon dioxide layer, also called field oxide, is created on the surface (Fig. 2.4(b)). Then, the field oide is selectively etched to expose the silicon surface on which the MOS transistor will be created (Fig. 2.4(c)). Following this step, the surface is covered with a thin, high-quality oxide layer, which will eventually form the gate oxide of the MOS transistor (Fig. 2.4(d)).

Grow Field Oxide

Etch Field Oxide

Grow Thin Oxide

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On top of the thin oxide layer, a layer of polysilicon (polycrystalline silicon) is deposited (Fig. 2.4(e)). Polysilicon is used both as gate electrode material for MOS transistors and also as an interconnect medium in silicon integrated circuits. Undoped polysillicon has relatively high resistivity. The resistivity of polysilicon can be reduced, however, by doping it with impurity atoms. After deposition, the polysilicon layer is patterned and etched to form the interconnects and the MOS transistor gates (Fig. 2.4(f)). The thin gate oxide not covered by polysilicon is also etched away, which exposes the bare silicon surface on which the source and drain junctions are to be formed (Fig. 2.4(g)).

Deposit Poly

The entire silicoimpurities, eithwith donor atothat the doping

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Undoped

Pattern Poly

Etch thinox not covered by poly

n surface is then doped with a high concentration of er through diffusion or ion implantation (in this case ms to produce n-type doping). Figure 2.4(h) show penetrates the exposed areas on the silicon surface,

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ultimately crating two n-type regions (source and drain junctions) in the p-type substrate. The impurity doping also penetrates the polysilicon on the surface, reducing its resistivity. Note that the polysilicon gate, which is patterned before doping, actually defines the precise location of the channel region and, hence, the location of the source and the drain regions. Since this procedure allows very precise positioning of the two regions relative to the gate, it is also called the self-aligned process.

Doped Self-aligned process

Once the source and drain regions are completed, the entire surface is again covered with an insulating layer of silicon dioxide (Fig. 2.4(i)). The insulating oxide layer is then patterned in order to provide contact windows for the drain and source junctions (Fig. 2.4(j)). The surfaces is covered with evaporated aluminum which will form the interconnects (Fig. 2.4(k)). Finally, the metal layer is

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patterned and etched, completing the interconnection of the MOS transistors on the surface (Fig. 2.4(l)). Usually, a second (and third) layer of metallic interconnect can also be added on top of this structure by creating another insulating oxide layer, cutting contact (via) holes, depositing, and patterning the metal.

Metal layer patterned & etched

Device Isolation Techniques The MOS transistors that comprise an integrated circuit must be electrically isolated from each other during fabrication. Isolation is required to prevent unwanted conduction paths between the devices, to avoid creation of inversion layer outside the channel regions of transistors, and to reduce leakage currents. To achieve a sufficient level of electrical isolation between neighboring transistors on a chip surface, the devices are typically created in dedicated regions called, active areas, where each active area is surrounded by a relatively thick oxide barrier called the field oxide. On possible technique to create isolated active areas on silicon surface is first to grow a thick field oxide over the entire surface of the chip, and then to selectively etch the oxide in certain regions, to

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define the active areas. This fabrication technique, called etched field-oxide isolation, is already illustrated in Fig. 2.4(b) and Fig. 2.4(c).

Local Oxidation of Silicon (LOCOS):

Selectively grow Field Oxide on certain region.

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Channel-StopImplant

Grow Field Oxide

Etch Nitride & Pad Oxide

Define Active Area

PAD Oxide: (Stress-relief Oxide): Protect the silicon surface from stress caused by nitride during the subsequent process steps

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Function of SiO2 1. Gate-oxide (thinox) 2. Field-oxide (thick) 3. Self-aligned process (source & drain donor extend over the gate) 4. "Field device" or "Parasitic MOS transistors"

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Fabrication of the CMOS Transistor CMOS Process Technology

1. n-well process 2. p-well process 3. Twin-tub process 4. Silicon-on-insulator (SOI) good candidate for low-power

CMOS design

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(e) D- LeaSourc

(c)- -

-

(-

(a)- n- n- Wdif

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Define n-well (n-tub) -well for PMOS -well-shallow is better ell is extended by lateral

fusion

Channel-stop Implant: Use p-well Mask Dope the p-sub with p+ in areas where no NMOS using photoresisit Prevent conduction between unrelated transistor source/drain

b) Define Active Region Grow SiO2/Si3N4

- Strip Photoresist - Grow thick field oxide where

Si3N4 layer is absent - (LOCOS) (Bird’s break): Final

field oxide and Gate Oxide interface is very planar --> smaller L

efine Polysilicon gate d to “Self-aligned” e/Drain Region

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(i) - Grow SiO2 - Define contact cut: Etch SiO2 down to surface to be conducted.

(h) P+ mask - (LDD is not required), - Less Hot-carrier susceptibility.

(g) Light-Doped Drain

(f) Define NMOS - Use N+ mask - Poly is doped

(j) Metallization: Add metal to produce circuit connectivity

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● Substrate Contact (Well contacts, Body ties, Tub ties)

1. Place n+ region in the n-well (Vdd contacts)

2. Place p+ region in the p-type substrate (Vss contacts)

● p-well process

1. n-well process is more popular in recent years 2. (p-well process is popular in the past) 3. n-well <--> p-well in process 4. The device in the substrate has better characteristics

- p-well process has better p devices than the n devices

- Note p-devices have lower gain than the n devices - n-well process exacerbates the difference <->

p-well process can balance the difference

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Summary: Figures from Append A: VLSI Fabrication Technology (from Sedra/Smith, Microelectronics Circuits, 4th ed, 1998)

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