CEN214_Chapter8.ppt

7/23/2019 CEN214_Chapter8.ppt

http://slidepdf.com/reader/full/cen214chapter8ppt 1/38

Charles Kime & Thomas Kaminski

© 2008 Pearson Education, Inc.(Hyperlinks are active in View Sow !ode"

Chapter 8 – Memory Basics

Logic and Computer Design Fundamentals



#apter 8 2

Overview

Memory definitions

andom !ccess Memory "!M#

$tatic !M "$!M# integrated circuits$ Cells and slices

$ Cell arrays and coincident selection

!rrays of $!M integrated circuits

Dynamic !M "D!M# integrated circuits

D!M Types

$ $ynchronous "$D!M#$ Dou%leData ate "DD $!M#

$ !M'($ D!M "D!M#

!rrays of D!M integrated circuits



#apter 8 %

Memory Definitions

Memory ) ! collection of storage cells together withthe necessary circuits to transfer information to and

from them*

Memory Organi+ation ) the %asic architectural

structure of a memory in terms of how data is accessed* andom !ccess Memory "!M# ) a memory

organi+ed such that data can %e transferred to or from

any cell "or collection of cells# in a time that is not

dependent upon the particular cell selected* Memory !ddress ) ! vector of %its that identifies a

particular memory element "or collection of elements#*



#apter 8 &

Memory Definitions "Continued#

Typical data elements are,$ %it ) a single %inary digit

$ %yte ) a collection of eight %its accessed together

$ word ) a collection of %inary %its whose si+e is atypical unit of access for the memory* -t is typically apower of two multiple of %ytes "e*g*. / %yte. 0 %ytes. 1%ytes. 2 %ytes. etc*#

Memory Data ) a %it or a collection of %its to %estored into or accessed from memory cells*

Memory Operations ) operations on memorydata supported %y the memory unit* Typically.read and write operations over some dataelement "%it. %yte. word. etc*#*



#apter 8 '

Memory Organi+ation

Organi+ed as an inde3ed array of words* 4alue of theinde3 for each word is the memory address*

Often organi+ed to fit the needs of a particular

computer architecture* $ome historically significant

computer architectures and their associated memoryorgani+ation,

$ Digital 56uipment Corporation 7D72 8 used a /0%it address

to address 19:; /0%it words*

$ -'M <;9 8 used a 01%it address to address /;.===.0/; 2%it

%ytes. or 1./:1.<91 <0%it words*

$ -ntel 2929 8 "2%it predecessor to the 292; and the current

-ntel processors# used a /;%it address to address ;>.><; 2%it

%ytes*



#apter 8

Memory 'lock Diagram

! %asic memory system isshown here,

k address lines are

decoded to address 0k

words of memory*

5ach word is n %its*

ead and ?rite are single

control lines defining the

simplest of memory

operations*

n Data Input Line

k AddressLines

Read

Write

n Data Output Li

Memory Unit

2k Wordsn Bits per Word

k

1

1

n

n


http://slidepdf.com/reader/full/cen214chapter8ppt 7/38#apter 8 )

Memory Organi+ation 53ample

53ample memorycontents,

$ ! memory with <

address %its & 2data %its has,

$ k @ < and n @ 2 so0< @ 2 addresses

la%eled 9 to =*$ 0< @ 2 words of 2%it

data

Memory !ddress

'inary Decimal

Memory

Content

9 9 9 9 / 9 9 9 / / / /

9 9 / / / / / / / / / /

9 / 9 0 / 9 / / 9 9 9 /

9 / / < 9 9 9 9 9 9 9 9

/ 9 9 1 / 9 / / / 9 9 /

/ 9 / > / 9 9 9 9 / / 9/ / 9 ; 9 9 / / 9 9 / /

/ / / = / / 9 9 / / 9 9


http://slidepdf.com/reader/full/cen214chapter8ppt 8/38#apter 8 8

'asic Memory Operations

Memory operations re6uire the following,$ Data ) data written to. or read from. memory as

re6uired %y the operation*

$ !ddress ) specifies the memory location to operate

on* The address lines carry this information intothe memory* Typically, n %its specify locations of 0n words*

$ !n operation ) -nformation sent to the memory andinterpreted as control information which specifies

the type of operation to %e performed* Typicaloperations are 5!D and ?-T5* Others are5!D followed %y ?-T5 and a variety ofoperations associated with delivering %locks of data*Operation signals may also specify timing info*


http://slidepdf.com/reader/full/cen214chapter8ppt 9/38#apter 8 *

'asic Memory Operations (continued"

ead Memory ) an operation that reads a data valuestored in memory,$ 7lace a valid address on the address lines*

$ ?ait for the read data to %ecome sta%le*

?rite Memory ) an operation that writes a data value to

memory,$ 7lace a valid address on the address lines and valid data on the

data lines*

$ Toggle the memory write control line

$ometimes the read or write ena%le line is defined as aclock with precise timing information "e*g* ead Clock.?rite $tro%e#*$ Otherwise. it is Aust an interface signal*

$ $ometimes memory must acknowledge that it has completed theoperation*


http://slidepdf.com/reader/full/cen214chapter8ppt 10/38#apter 8 +0

Memory Operation Timing

Most %asic memories are asynchronous

$ $torage in latches or storage of electrical charge

$ Bo clock

Controlled %y control inputs and address

Timing of signal changes and data o%servation is critical to theoperation

ead timing,

Read cycle

Clock

Address

Memoryenable

ReadWrite

Dataoutput

2! ns

"1 "2 "# "$ "1

Address %alid

&' ns

Data %alid


http://slidepdf.com/reader/full/cen214chapter8ppt 11/38#apter 8 ++

Memory Operation Timing

?rite timing,

Critical times measured with respect to edges of write pulse "/9/#,$ !ddress must %e esta%lished at least a specified time %efore /9 and held for at

least a specified time after 9/ to avoid distur%ing stored contents of otheraddresses

$ Data must %e esta%lished at least a specified time %efore 9/ and held for atleast a specified time after 9/ to write correctly

Write cycle

Clock

Address

Memoryenable

ReadWrite

Datainput

2! ns

"1 "2 "# "$ "1

Address %alid

Data %alid

(' ns



!M -ntegrated Circuits

Types of random access memory$ $tatic 8 information stored in latches

$ Dynamic 8 information stored as electrical charges

on capacitors

Charge leaks off

7eriodic refresh of charge re6uired

Dependence on 7ower $upply

$ 4olatile 8 loses stored information when power

turned off

$ Bonvolatile 8 retains information when power

turned off


http://slidepdf.com/reader/full/cen214chapter8ppt 13/38#apter 8 +%

$tatic !M E Cell

!rray of storage cells used to implement static!M

$torage Cell

$ $ Latch

$ $elect input forcontrol

$ Dual ail Data

-nputs ' and '$ Dual ail Data

Outputs C and C

$elect

'

!M cell

C

C

'

$


http://slidepdf.com/reader/full/cen214chapter8ppt 14/38#apter 8 +&

$tatic !M E 'it $lice

epresents all circuitry that is re6uired for 0n

/%it words

$ Multiple !M cells

$ Control Lines,

?ord select i 8 one for each word

ead G ?rite

'it $elect

$ Data Lines,

Data in

Data out

(a) Logic diagram

Select

S

R

Q

Q

B

RA M cell

C

CB

SelectWordselect2n 2 1

Wordselect2n 2 1

Wordselect0

Word

select1

S

R

Q

Q

RA M cell

X

Wordselect0

Data in

Write logic

Read/

Write

Bit

select

S

R

Q

Q

X

X

X

Read/Write

logic

Data in

Data ot

Read/Write

Bitselect

(!) S"m!ol

RA M cell

RA M cell

RA M cell

Data otRead logic


http://slidepdf.com/reader/full/cen214chapter8ppt 15/38#apter 8 +'

eadG

0n?ord /'it !M -C

To %uild a !M -Cfrom a !M slice.

we need,

$ Decoder E decodes

the n address lines to

0n word select lines

$ ! <state %uffer E

on the data output

permits !M -Cs to%e com%ined into a

!M with c 0n words

?ord select

eadG?ritelogic

Data in

Data out

?rite'itselect

"%# 'lock diagram

!M cell

!M cell

!M cell

Data input

Chip select

eadG?rite

Dataoutput

!<

!0

!/

!9

0<

00

0/

09

1to/;Decoder 9

/

0

<

1

>

;

=

2

:

/9

//

/0

/<

/1

/>

!<

!0

!/

!9

Datainput

Dataoutput

"a# $ym%ol

eadG?rite

Memoryena%le

/;x/!M


http://slidepdf.com/reader/full/cen214chapter8ppt 16/38#apter 8 +

Memory arrays can %e very large$ Large decoders

$ Large fanouts for the %it lines

$ The decoder si+e and fanouts can %e reduced %y

appro3imately %y using a coincident selection ina 0dimensional array

$ (ses two decoders. one for words and one for %its

$ ?ord select %ecomes ow select

$ 'it select %ecomes Column select $ee ne3t slide for e3ample

$ !< and !0 used for ow select

$ !/ and !9 for Column select

Cell !rrays and Coincident $election

n


http://slidepdf.com/reader/full/cen214chapter8ppt 17/38#apter 8 +)

Cell !rrays and Coincident $election

Data input

eadG?rite

H HH

!/ !9

!M cell9

!M cell1

!M cell2

!M cell/0

eadG?ritelogic

Data in

Data out

eadG?rite

'itselect

!M cell/

!M cell>

!M cell:

!M cell/<

eadG?ritelogic

Data in

Data out

eadG?rite

'itselect

!M cell0

!M cell;

!M cell/9

!M cell/1

eadG?ritelogic

Data in

Data out

eadG?rite

'itselect

!M cell<

!M cell=

!M cell//

!M cell/>

eadG?ritelogic

Data in

Data out

eadG?rite

'itselect

Columndecoder

0to1 Decoderwith ena%le

0/ 09

9 /

Column select

0

5na%le

<

Chip select

Dataoutput

owselect

ow decoder

!0

!<

H

0to1Decoder

09

0/

/

0

<

9



!M -Cs with I / 'itG?ord

?ord length can %e 6uite high* To %etter %alance the num%er of words

and word length. use -Cs with I /

%itGword

53ample

$ 0 Data input %its

$ 0 Data output %its

$ ow select selects 1 rows

$ Column select selects 0 pairs of columns


http://slidepdf.com/reader/full/cen214chapter8ppt 19/38#apter 8 +*

'lock Diagram of an 2J0 !M

Data input 9

eadG?rite

H H

!9

!M cell9

!M cell1

!M cell2

!M cell/0

eadG?ritelogic

Data in

Data out

eadG?rite

'itselect

!M cell/

!M cell>

!M cell:

!M cell/<

eadG?ritelogic

Data in

Data out

eadG?rite

'itselect

!M cell0

!M cell;

!M cell/9

!M cell/1

eadG?ritelogic

Data in

Data out

eadG?rite

'itselect

!M cell<

!M cell=

!M cell//

!M cell/>

eadG?ritelogic

Data in

Data out

eadG?rite

'itselect

Columndecoder

/to0 Decoder

with ena%le

09

9 /

Column select

5na%le

Chip select

DataOutput 9

owselect

ow decoder

!/

!0

0to1Decoder

09

0/

/

0

<

9

Data input /

DataOutput /H H


http://slidepdf.com/reader/full/cen214chapter8ppt 20/38#apter 8 20

Making Larger Memories

(sing the C$ lines. wecan make largermemories from smallerones %y tying alladdress. data. and G?

lines in parallel. andusing the decodedhigher order address%its to control C$*

(sing the 1?ord %y /

'it memory from%efore. we construct a/;?ord %y/'it memory*

⇒

D#

)1

)!

D2

D1

D!

Decoder

RW

A2

A#

A1

A!

Data In

Data Out

RWC)

A!A1 D*In

D*Out

RW

C)

A!A1 D*In

D*Out

RWC)

A!A1 D*In

D*Out

RWC)

A!

A1 D*In

D*Out



#apter 8 2+

Making ?ider Memories

To construct widermemories from narrowones. we tie the addressand control lines inparallel and keep the data

lines separate* For e3ample. to make a 1

word %y 1%it memoryfrom 1. 1word %y /%itmemories

⇒

Bote, 'oth /;3/ and 131memories take 1chipsand hold /; %its of data* RW

A1A!

Data In

Data Out

RWC)

A!A1 D*In

D*Out

RWC)A!

A1 D*In

D*Out

RWC)

A!A1 D*In

D*Out

RWC)

A!A1 D*In

D*Out

C)

# 2 1 !

# 2 1 !



'lock Diagram of a 0>;KJ2 !M

#apter 8 22

;1K J 2 !M

D!T!

!D$

C$

G?

;1K J 2 !M

D!T!

!D$

C$

G?

;1K J 2 !M

D!T!

!D$C$

G?

;1K J 2 !M

D!T!

!D$

C$

G?

-nput

DataLines 9 />

!ddress

0to1 DecoderMemory 5na%le

Lines/= /;

5B< 0 / 9

eadG ?rite

2/;

2

Output Data

9 ;>><>

;>><; /</9=/

/</9=0 /:;;9=

/:;;92 0;0/1<



'lock Diagram of a ;1KJ/; !M

#apter 8 2%

;1K J 2 !M

D!T!

!D$

C$

G?

;1K J 2 !M

D!T!

!D$

C$

G?

2

22

/; -nput Data Lines

2

/;!ddress

/; /;

Chip $elect

ead G ?rite

22

/; Output Data Lines



'lock Diagram of a 0>;KJ/; !M

#apter 8 2&

;1K J 2 !M

D!T!

!D$

C$

G?

;1K J 2 !M

D!T!

!D$

C$

G?

;1K J 2 !M

D!T!

!D$

C$G?

;1K J 2 !M

D!T!

!D$

C$

G?

/; -nput Data Lines

Lines 9 />

!ddress

0to1 DecoderMemory 5na%le

Lines/= /;

5B< 0 / 9

eadG ?rite

2

/;

2

;1K J 2 !M

D!T!

!D$

C$

G?

;1K J 2 !M

D!T!

!D$

C$

G?

;1K J 2 !M

D!T!

!D$

C$G?

;1K J 2 !M

D!T!

!D$

C$

G?

2

/; Output Data Lines

2



#apter 8 2'

Dynamic !M "D!M#

'asic 7rinciple, $torage of informationon capacitors*

Charge and discharge of capacitor to

change stored value (se of transistor as switch to,

$ $tore charge

$ Charge or discharge

$ee ne3t slide for circuit. hydraulicanalogy. and logical model*



#apter 8 2

Dynamic !M (continued"

"a# "c#

$elect

D

C

'

D!M cell

model

C

"f# "g#"h#

$elect

'T

C

D!M cell

To 7ump

"%#

"d# "e#

$tored / $tored 9

?rite / ?rite 9

ead / ead 9



#apter 8 2)

Dynamic !M 'it $lice

C is driven %y <statedrivers

$ense amplifier is used

to change the small

voltage change on Cinto or L

-n the electronics. '. C.

and the sense amplifier

output are connected to

make destructive read

into nondestructive

read(!) S"m!ol

(a) Logic diagram

Select

B

Select

Word

select0

Data in

Write logic

Bitselect

Data otRead logic

D

C

Q

DRA M cellmodel

D

C

Q

DRAM cellmodel

C

Senseam#li$er

Read/Writelogic

Data inData ot

Bitselect

DRA M cell

DRA M cell

DRA M cell

Wordselect0

Wordselect1

Read/Write

Read/Write

2 1

2 1



Dynamic !M 'lock Diagram

#apter 8 28

efresh

Controller

efresh

Counter

ow !ddress

egister

ow Timing

Logic

ow !ddress

egister

ow Timing

Logic

ow

!ddress

!$

C!$

Column

!ddressColumn Decoder

D!M

'it $lice

D!M

'it $lice

D!M

'it $lice

-nput G Output Logic

L

Data -n G

Data Out

G?

O5



#apter 8 2*

Dynamic !M 'lock Diagram

efresh Controller and efresh Counter

ead and ?rite Operations$ !pplication of row address

$ !pplication of column address

$ ?hy is the address split

$ ?hy is the row address applied first

The row address is used to select the row of cells to %e read within the memory*

The address is split to roughly halve the large num%er of address pins on the typical !M -C*

The column address is used to select the word to %e placed on the output from the data read

from the row of cells*

$ince the data must %e read from the cells %efore it can %e selected. the row address must %e

applied first*



#apter 8 %0

Dynamic !M ead Timing

ead Cycle

09 ns

T/ T0 T< T1 T/

Data valid

;> ns

iN

eadG?rite

Data

output

Clock

ow

!ddress

Column!ddress

!$

C!$

!ddress

Outputena%le



#apter 8 %+

Dynamic !M ?rite Timing

?rite Cycle

09 ns

T/ T0 T< T1 T/

Data valid

=> ns

eadG?rite

Data

output

Clock

ow

!ddress

Column!ddress

!$

C!$

!ddress

Outputena%le



#apter 8 %2

D!M Types

D!M Types,

$ $ynchronous D!M "$D!M#

$ Dou%le Data ate $D!M "DD $D!M#

$ !M'($ D!M "D!M#

Pustification for effectiveness of these types$ D!M often used as a part of a memory hierarchy "$ee details in

chapter /1#

$ eads from D!M %ring data into lower levels of the hierarchy

$ Transfers from D!M involve multiple consecutively addressed

words

$ Many words are internally read within the D!M -Cs using a

single row address and captured within the memory

$ This read involves a fairly long delay



#apter 8 %%

D!M Types

Pustification for effectiveness of these types (continued"$ These words are then transferred out over the memory data

%us using a series of clocked transfers

$ These transfers have a low delay. so several can %e done in a

short time

$ The column address is captured and used %y a synchronouscounter within the D!M to provide consecutive column

addresses for the transfers

'urst read – the resulting multiple word read fromconsecutive addresses



#apter 8 %&

$ynchronous D!M

Transfers to and from the D!M are synchroni+e with a clock

$ynchronous registers appear on,

$ !ddress input

$ Data input

$ Data output

Column address counter

$ for addressing internal data to %e transferred on each clock cycle

$ %eginning with the column address counts up to column address Q %urst

si+e 8 /

53ample, Memory data path width, / word @ 1 %ytes

'urst si+e, 2 words @ <0 %ytes

Memory clock fre6uency, > nsLatency time "from application of row address until first word

availa%le#, 1 clock cycles

ead cycle time, "1 Q 2# 3 > ns @ ;9 ns

Memory 'andwidth, <0G";9 3 /9:# @ ><< M%ytesGsec



#apter 8 %'

Dou%le Data ate $ynchronous D!M

Transfers data on %oth edges of the clock 7rovides a transfer rate of 0 data words per

clock cycle

53ample, $ame as for synchronous D!M

$ ead cycle time @ ;9 ns

$ Memory 'andwidth, "0 3 <0#G";9 3 /9&:# @ /*9;;

M%ytesGsec



#apter 8 %

!M'($ D!M "D!M#

(ses a packet%ased %us for interaction %etween the D!M -Cs and thememory %us to the processor

The %us consists of,

$ ! <%it row address %us

$ ! >%it column address %us

$ ! /; or /2%it "for error correction# data %us

The %us is synchronous and transfers on %oth edges of the clock

7ackets are 1clock cycles long giving 2 transfers per packet representing,

$ ! /0%it row address packet

$ ! 09%it column address packet

$ ! /02 or /11%it data packet

Multiple memory %anks are used to permit concurrent memory accesses

with different row addresses

The electronic design is sophisticated permitting very fast clock speeds



#apter 8 %)

!rrays of D!M -ntegrated Circuits

$imilar to arrays of $!M -Cs. %ut there aredifferences typically handled %y an -C called a

DRAM controller ,

$ $eparation of the address into row address and

column address and timing their application$ 7roviding !$ and C!$ and timing their

application

$ 7erforming refresh operations at re6uired intervals

$ 7roviding status signals to the rest of the system

"e*g*. indicating whether or not the memory is active

or is %usy performing refresh#



Terms of (se

!ll "or portions# of this material R 0992 %y 7earson5ducation. -nc*

7ermission is given to incorporate this material oradaptations thereof into classroom presentations andhandouts to instructors in courses adopting the latest

edition of Logic and Computer Design Fundamentals asthe course te3t%ook*

These materials or adaptations thereof are not to %esold or otherwise offered for consideration*

This Terms of (se slide or page is to %e included withinthe original materials or any adaptations thereof*

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CEN214_Chapter8.ppt