Cement Bag Loading Sys

EMBEDDED BASED CEMENT BAG LOADING SYSTEM

CONTENTS

CHAPTER PAGE NO

1 INTRODUCTION 3

1.1 Overview on Dalmia Cement (B) Ltd. 3

1.2 Embedded Based Cement Bag Loading System- 6Overview

2 METHODOLOGY 7

2.1 Problem Statement 8

2.1 Idea Implementation 9

2.2 Block Diagram 10

3 CIRCUIT DESCRIPTION 11

3.1 Power supply Circuit Diagram 11

3.2 Schematic Circuit Diagram 12

3.3 Algorithm and Flow Chart 25, 26

3.4 Programming Code 27

4 OUTCOME 31

5 CONCLUSION 34

6 BIBLIOGRAPHY 35

ST. JOSEPH’S COLLEGE 1 DEPARTMENT OF ELECTRONICS


CHAPTER PAGE NO

7 APPENDIX 37

AT89C51 MICRO CONTROLLER 38

LIQUID CRYSTAL DISPLAY (16*1) 46

555 OPERATION 53



1.INTRODUCTION

1.1.OVERVIEW ON DALMIA CEMENT (B) LTD

DALMIA CEMENT BHARATH LIMITEDDALMIA PURAM

Only in the year 1914, India entered of cement

manufacturing. Now there are many cement factories spreader all over

India expect west Bengal, ASSAM and KASHMIR. Shri. Ramkrishna

Dalmia, a daring foresighted pioneer in the industrialization of India

planned to establish Many cement factories in different parts of the

country and act upon it by establish cement plans at Dalmia Nagar in

Bihar, Karachi, Dalmia Dadri, Dondal in Punjab, Sawai Modhapur in

Rajastan and Dalmia puram in Tamilnadu.

Dalmia cement Bharath limited, is the largest and

leading cement manufacturing company in tamilnadu. It is located in

Trichy-Chennai chord line and it is 45 kilometres north east of Trichy

town. DCBL, commenced its production in the year 1939, with and



installed capacity of 250 tones of clinker per day produced from the

Polsius Lepol kiln, a semidry process technology. In 1949 the second wet

process UNAX KILAN was installed. These two plants added to raise

the installed capacity to 1250 tones per day. To increase the capacity by

200 tones per day mini cement plant viz., VERTICAL SHAFT KILN

(VSK) of fuel slurry process technology was launched in the year 1981-

1982. This is the first cement plant in asia which absorbed this

technology, in the year 1987 the company has completed in

modernization by installing 1500 TPD dry process KILD KILN with

PRE CALCINATOR technology with computerized control system. In

this KILN heat energy utilization is optimum and power consumption is

comparatively low. In addition, a 110KV sub station was erected in the

year 1982.

In order to augment the power position and to meet

any future power cut, four captive generator sets were installed having

15 MVA Capacity in Dalmia Puram works. After modernization the



installed capacity in the production of cinker reached 1950 tones per day.

And hence wet process kilns UNAX and folks.

TYPES OF CEMENT PRODUCED:

OPC - Ordinary Portland Cement

PPC - Portland Pozzaolana Cement

GPHSSC - Grey Portland High Strength Special Cement

OWC - Oil Well Cement

PSC - Portland Slag Cement

DALMIAPURAM UNIT HAS A LOT OF FIRST TO ITS CREDITS

1) It was first to introduce the vertical roller mill technology in India

conserving valuable energy

2) This unit is a pioneer in the production of high strength special

cement required for manufacture of concrete railway sleeper as

also in manufacture of oil well cement required in oil drilling

corporation



3) It was first to install captive power generator which can run on

heavy fuel oil thus saving scarce and valuable light distillated like

diesel

4) It was the first to introduce fuel shurry process through

VERTICAL SHAFT KILN Technology.

1.1.EMBEDDED BASED CEMENT BAG LOADING SYSTEM

This project has been selected in order to rectify the

problem while counting and loading the cement bags.

Now a days they count the cement bags manually and

loaded in to the vehicle. This method of counting may cause an error and

consumes more time , this would cause a big problem in marketing and

distribution.

In order to overcome these drawbacks the cement bag

counting and loading system should be automated. In order to automate,

the embedded based cement bag counting and loading system has been

developed. A cement bag has been identified by means of sensor and has



interfaced to the micro controller to count the number of cement bags.

The required number of cement bags has been delivered from the

keyboard through the hostport to the microcontroller. And thus this

system has the control of counting and loading the cement bags.

CHAPTER 2

2.1. PROBLEM STATEMENT 8

2.2. IDEA IMPLEMENTATION 9

2.3. BLOCK DIAGRAM 10



2.1.PROBLEM STATEMENT:

In order to achieve very rapid marketing and

product distribution from the manufacturing area to the agencies, should not

take much time in packing section of Dalmia cement Factory, The Cement

bag which are packed form the rotary backer is kept on the conveyer belt

and counted manually and loaded in to the lorry as well.

This work is time consuming one, And there was

a chance of miscounting. This would cause to reduce the economy of that

concern.

This manual method deploys more number of

employees ultimately this rises the production cost. To overcome these

difficulties the cement bag loading system should be automated.



2.2. IMPLEMENTATION

To automate the cement bag loading system

here the embedded system has been used. The Embedded system has been

constructed using the AT89C51 Micro Controller.

The vehicle in which the cement bag would

be loaded can be identified by the micro switch which are placed on the

loading system has been interfaced to the controller to activate conveyer belt

Motor.

The occurance of cement bag on the

conveyer belt is identified by the sensor, and is counted by the AT89C51

Microcontroller. The number of cement bag which are going to be loaded in

to the vehicle has been specified as a reference, from a PC to Micro

Controller through the host port. When the count has been attained the

reference value it in the duty of micro controller to stop the conveyer, which



will stop the loading cement bag, after counting this cement bag the counted

value has been displayed on the display section.

2.3. BLOCK DIAGRAM

Light Source

Conveyer Belt

Light Detector

Vehicle Sensor

Motor


µC

555 Circuit

.

.

.

.

PC LCD


HostPort

FIG : 2.3 (A)

3.CIRCUIT DESCRIPTION

3.1.POWER SUPPLY CIRCUIT DIAGRAM

POWER SUPPLY SECTION

Here the process need a 5V DC power supply for the Microcontroller,

Analog to Digital converter, Driver IC, LCD, and Multiplexer. So, the power

supply has designed with a Bridge rectifier which has an output of 12V. This

output is given to a Regulator IC 7805. This IC gives a constant output of

5V DC. This 5V DC supply is given to the various IC’s which is used in the

Water Spray Control System.

The circuit diagram of the power supply section is given below.



Figure 3.1(A)

3.2.SCHEMATIC CIRCUIT DIAGRAM



The over all circuit diagram of Embedded Based

Cement Bag loading System is as shown in figure 3.2.(A) It includes

different parts as follows.



3.1.1 VEHICLE MONITORING SECTION:

In this project load cell must be implemented so as to check

the vehicle is present or not, more over Cement bag count checking can be

accomplished Initially the weight of the vehicle will be measured after

loading process, the entire weight along with cement bags will be measured

it will compared with the weight of cement bags loaded that has been

counted by the sensor circuitary.

Since the availability of the load cell is hard and cost

effectiveness. I make use of single toggle switch to indicate the presence of

vehicle.

3.1.2 CEMENT BAG SENSING SECTION:

This part will sense the number of cement bags that has been

passed. This project makes use of light source and light detector circuit. The



detector circuit is LDR it has 2M Ohm, when it is kept in dark otherwise it

will provide 900 ohm, so as to accommodate the ambient condition

necessary arrangement has made.

3.1.3 HOST PORT INTERFACE SECTION:

The data from host computer must reach the system, to make

a job ease, I choose parallel port, of course it can be done with the help of

serial port.

Address of the data bus in the parallel is 378H similarly to

implement hand shaking mode. This project uses control bus of the parallel

port, this will seize the data bus. So as to transfer the data from host to

system. The address of control bus in 379H, The address of status bus is

37AH.

3.1.4 MOTOR SECTION:

The motor used in these project is DC motor which substitutes

the conveyer motor. The output from the micro controller section may not

drive the DC motor. So I have used an interface circuit which in corporates



555IC with which speed of the motor can be controlled. Even switching

circuit may be used to drive the motor section.

The difficulty of switching circuit is speed of motor remains

constant by making use of interface circuit we can alter the speed by varying

the resistance RA and RB, Energizing the circuit is done with the help of

reset pin of 555IC. If the reset pin is at ground state the entire circuit will be

deactivate. In order to activate this pin must be provided with high state.

3.1.4(a) ASTABLE MULTIVIBRATOR USING 555IC:

The device is connected for astable operation as shown in the

figure 3.2.For better understanding, the complete diagram of astable

multivibrator with detailed internal diagram of 555 is shown in

Figure 3.2.Comparing with monostable operation,the timing resistor is now

split into two resistors RA and RB.pin 7 of discharging transistor Q1 is

connected to the junction of RA and RB.When the power supply Vcc is



connected,the external capacitor C charges towards Vcc with a time

constant(RA+RB)C.During this time,output(pin 3) is high (equals Vcc) as

reset R=0,Set S=1 and this combination makes Q=0 which is unclamped the

timing capacitor C.When the capacitor voltage equals Vcc the upper

comparator triggers the control flip-flop so that Q =1.

This in turn makes transistor Q1 on and capacitor C

starts discharging towards ground through RB and transistor Q1 with a time

constant RB C.Current also flows into transistor Q1 through RA.Resistors

RA and RB must be be large enough to limit this current and prevent

damage to the discharge transistor Q1.The minimum value of RA is

approximately equal to Vcc/0.2 where 0.2A is the maximum current through

the on transistor Q1.



FIG: 3.2. (B) Astable Multivibrator Using 555 Timer

During the discharge of the timing capacitor C, as it reaches

Vcc/3 the lower comparator is triggered and at this stage S=1,R=0, which

turns Q=0.Now Q=0 unclamps the external timing capacitor C. The

capacitor C is thus periodically charged and discharged between (2/3) Vcc

and (1/3)Vcc repectively.Figure 2.3. (C) shows the timing sequence and

capacitor voltage waveform.The length of time that the output remains

HIGH is the time for the capacitor to charge from (1/3)Vcc to (2/3)Vcc.It

may be calculated as follows,



FIG : 3.2 (C) Functional Diagram of Astable Multivibrator Using 555 Timer

The capacitor voltage for a low pass RC circuit subjected to a

step input of Vcc volts given by,

vc=Vcc(1-e-t/RC) --------(3.1.1)

The time t1 taken by the circuit to charge from 0 to (2/3)Vcc is,

(2/3) vcc=Vcc(1-e-t1/RC) -------(3.1.2)

t1=1.09RC



and the time t2 to charge from 0 to (1/3)Vcc is,

(1/3) vcc=Vcc(1-e-t1/RC) ---------(3.1.3)

t2=0.405RC

So the time to charge from (1/3)Vcc to (2/3)Vcc is

tHIGH=t1-t2

tHIGH=0.69(RA+RB)C --------(3.1.4)

The output is low while the capacitor discharges from (2/3)Vcc to (1/3)Vcc

And the voltage across the capacitor is given by

(1/3) vcc=(2/3)Vcce-t/RC

solving we get t=0.69RC

Therefore the total time

T=tHIGH+tLOW

Or T=0.68(RA+2RB)C

So, f =1/T=1.45 ------- (3.1.5)(RA+2RB) C



Shows FIG 3.2 (D) a graph of the various combination of (RA+2RB)

and C necessary to produce a given stable output frequency. The duty cycle

D of a circuit is defined as the ratio of ON time period T = (tON +

tOFF) in this circuit, when the transistor Q1 is on, the output goes low.

capacitance 0.1 0.1 in F 0.01

0.001 1 10 100 1k 10k 100k

Astable frequency in Hz

FIG. 3.2. Frequency Dependence of RA, RB and C

3.1.5 MICRO CONTROLLER INTERFACE SECTION:


1M 0.1M 10k 1k

10M

(RA+2RB)


The port1.2 is connected to vehicle sensor, Entire port2 is

connected to data bus. Port1.4 is connected to status port, the port1.5 is

connected to control port the prot1.1 is connected to light sensor, the port1.3

is connected to reset pin of the 555IC and the Entire port3 is connected to

display section.

3.1.5(a) DISPLAY SECTION:

In order to display the require statement that a user would use

to display, a Liquid Crystal Display (LCD) has selected.

A 16*1 LCD has interfaced to the AT89C51 micro controller.

The block diagram of 16*1 LCD as follows.


/\/\/\


K

A

DB0-DB7

E

RS

R/W

V0

Vdd

Vss

FIG : 3.2. (E) Block Diagram of (16X1) LCD


LED BACK LIGHT

DOT MATRIX LCD CONTROL – - LER

LCD PANEL

SEGMENT DRIVER

R


PIN CONFIGURATION OF LCD (16X1):


PIN. NO SYMBOL FUNCTION

1 Vss GROUND

2 Vdd +5 V

3 Vo CONTRAST PIN FOR LCD

4 RS REGISTER SELECT

5 R/W READ/WRITE

6 E ENABLE

7 DB0 DATABUS

8 DB1 DATABUS

9 DB2 DATABUS

10 DB3 DATABUS

11 DB4 DATABUS

12 DB5 DATABUS

13 DB6 DATABUS

14 DB7 DATABUS

15 A ANODE

16 K CATHODE


The function of LCD can be easily understood by the pin

configuration of LCD. The backlight of LCD can be easily activated when

applying forward voltage to its terminals. The power supply pins can be

supplied by the + 5v D>C> The RS (register select) pin decides whether the

data bus has the data or control word.

If it is set, the data bus has data otherwise it is command

word. Read and write operation can be achieved through R/W pin. Each read

and write operation can be achieved when Enable pin (E) is activated.



3.3(a) ALGORITHM:

STEP 1. Initialize the LCD

STEP 2. Check whether the vehicle is present or not

STEP 3. Enter the number of cement bags

STEP 4. Activate the conveyer belt motor

STEP 5. Count the number of cement bags and check

whether it is equal to the reference value

STEP 6. Switch of the conveyer motor.

STEP 7. Display the counted value of cement bag.



3.3(b) FLOW CHART

NO

YES

NO

YES


START

INITIALIZELCD

ISLORRY

?

ENTER THE NUMBER OF BAGS(REFERENCE)

ACTIVATE THEMOTOR

COUNT THE NUMBER OF

BAGS

ISC>REF

DEACTIVATE THE

MOTOR

DISPLAY THE NUMBER OFBAGS

STOP


3.4.PROGRAMMING CODETable 3.4(a)


LABEL MNEMONICS COMMENTS

$o JB P1.3,$o CHECK THE VEHICLE SENSOR BIT

START SETB P1.4

CLR P1.4 SEND INTR TO PC TO GET NUMBER OF CEMENT BAGS (DATA)

SETB P1.4

$1 JNB P1.5, $1 CHECK THE STATUS OF PC$2 JB P1.5, $2

$3 JNB P1.5, $3

MOV R2, P2 GET DATA FROM PC

MOV A, R2RPT LCALL DISP DISPLAY THE DATA IN LCD

$4 JNB P1.1, $4 COUNT THE NUMBER OF CEMENT BAGS$5 JB P1.1, $5

$6 JNB P1.1, $6

SETB P1.3 ACTIVATE THE CONVEYER

DJNZ, R2, RPT MOTOR IS COUNT VALUE = REFERENCE VALUE

CLK P1.3 DEACTIVATE THE MOTOR

LJMP START


LCD PROGRAM:



INITIALI- MOV A, #38H (16X1) LCD solution control word initialization -ZATION ACALL CMD

CALL LONGDELAY

MOV A, #0EH increment cursor

ACALL CMD

CALL LONGDELAY

MOV A, #01H clear display

ACALL CMD

CALL LONGDELAY

MOV A, #06H shift - right cursor

ACALL CMD

CALL LONGDELAY

MOV A, #81H data location to be displayed

ACALL CMD

CALL LONGDELAY

CMD CLR P0.0 ‘RS’ pin control for command Word

CLR P0.1 ‘R/ W’ pin control for Command Word

CLR P0.2 ‘E’ pin control for command Word

MOV P2, ASETB P0.2

NOP




NOP

CLR P0.2

CALL DELAY Delay Program calling

CALL DELAY

RET

LCWR CLR P0.0 LCD initializing for

CLR P0.1 Data word

CLR P0.2

SETB P0.0

MOV P2, A

SETB P0.2

NOP

NOP

CLR P0.2

CALL BUSY Check LCD is busy or not

CALL DELAY

CALL DELAY

MOV R0, #FFH

C00 NOP

MOV R1, #FFH

C01 NOP



LABEL MNEMONICS COMMNETS

DJNZ R1, C01

DJNZ R0, C00

RET

BUSY CLR P0.0

SETB P0.1

CLR P0.2

SETB P0.2

JB P1.7, $

CLR P0.2

CALL DELAY

CALL DELAY

RET

DELAY MOV R5, #00H

NOP

DJNZ R5, $

RET LONG DELAY MOV R6, #00H

LOOP1 NOP

NOP

DJNZ R6, LOOP1

RET


4.OUTCOME

Embedded based cement bag loading system has been

Constructed after several difficulties.

In order to know the presence of vehicle, In which the

cement bag has to be loaded, a load cell was decided to use. But in the

commercial market availability is rare and costlier. This would cause to

change the vehicle sensing system to switch.

To count the cement bag a photo detective technique

has been used, It consists of infrared light source and detector, When

implementing this technique the response of the IR detector has not satisfied

the desire. It has a very poor range in order to rectify this problem an

LDR(Light Dependent Resistor) has been decided as a sensor and a normal

light source act as source.



4.1RESPONSE OF LDR:

Table(4.1(a))

To display the number of cement bags 7-segment

display section has decided to use. While interfacing the 7-segment section

to the AT89C51 Micro Controller there has been a storage of port pins. To

overcome this problem LCD (Liquid Crystal Display) has been decided to

use. Finally, the embedded based cement bag loading system has been

constructed successfully.


VOLTAGE ACROSS

FUNCTION THE LDR(V)

WHEN THE CEMENTBAG CUT THIS 3.8 SOURCE

AT NORMAL 0.3V


FURTHER DEVELOPMENT:

The embedded based cement bag loading system can

be improved when implementing a wireless

technology through Ethernet for remote sensing

And it can be implemented with load cell in order to

fully atomize.



5.CONCLUSION

Since the system has been automated, it will reduces man power

It may be implemented in any quality control system for counting

Since it has be automated, time consumption will drastically reduce

The reliability of this system will be higher when compared with

manual system

If this system is implemented high level security can be achieved.

Since the project has several advantages as

mentioned above, it can be implemented in the real time system.



CHAPTER 6



6. BIBLIOGRAPHY

BOOKS REFERRED:

THE MICROCONTROLLER AND EMBEDDED SYSTEM – MUHAMMAD ALI MAZIDI

PROGRAMMING AND CUSTOMIZING THE 8051 MICROCONTROLLER

- MYKE PREDKO

LINEAR INTEGRATED CIRCUITS - ROY CHOUDRY

WEBSITES:

www.alldatasheets.comwww.retron.comwww.electronicsforu.com


http://www.electronicsforu.com/

http://www.retron.com/

http://www.alldatasheets.com/


CHAPTER 7



i) MICRO CONTROLLER 89C51

GENERAL DESCRIPTION

The AT89C51 is a low-power, high-performance CMOS 8-bit

microcomputer with 4Kbytes of Flash Programmable and Erasable Read

Only Memory (PEROM). The device is manufactured using Atmel’s high

density nonvolatile memory technology and is compatible with the industry

standard MCS-51™ instruction set and pin out as shown in fig 2.4. The on-

chip Flash allows the program memory to be reprogrammed in-system or by

a conventional nonvolatile memory programmer. By combining a versatile

8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a

powerful microcomputer which provides a highly flexible and cost effective

solution to many embedded control applications.

FEATURES

• Compatible with MCS-51™ Products

• 4K Bytes of In-System Reprogramable Flash Memory

– Endurance: 1,000 Write/Erase Cycles

• Fully Static Operation: 0 Hz to 24 MHz

• Three-Level Program Memory Lock

• 128 x 8-Bit Internal RAM

• 32 Programmable I/O Lines

• Two 16-Bit Timer/Counters

• Six Interrupt Sources

• Programmable Serial Channel

• Low Power Idle and Power Down Modes



PIN CONFIGURATION

PIN CONFIGURATION

Ground (VSS) : 0 V reference.

Power Supply (VDD): This is the power supply voltage for normal, idle,

and power- down operation.



Port 0: Port 0 is an open-drain, bi-directional I/O port. Port 0

pins that have 1s written tothem float and can be used as

high-impedance inputs. Port 0 is also the multiplexed

low-order address and data bus during accesses to

external program and data memory. In this application, it

uses strong internal pull-ups when emitting 1s.

Port 1: Port 1 is an 8-bit bi-directional I/O port with internal

pull-ups. Port 1 pins that have 1s written to them are

pulled high by the internal pull-ups and can be used as

inputs. As inputs, port 1 pins that are externally pulled

low will source current because of the internal pull-ups.

T2 (P1.0): Timer/Counter2 external count input/clock

out.

T2EX(P1.1):Timer/Counter2 reload/capture/direction

control.




inputs. As inputs, port 2 pins that are externally being

pulled low will source current because of the internal

pull-ups. Port 2 emits the high-order address byte during

fetches from external program memory and during

accesses to external data memory that use 16-bit

addresses (MOVX @DPTR). In this application, it uses



strong internal pull-ups when emitting 1s. During

accesses to external data memory that use 8-bit addresses

(MOV @Ri), port 2 emits the contents of the P2 special

function register.




inputs. As inputs, port 3 pins that are externally being

pulled low will source current because of the pull-ups.

Port 3 also serves the special features of the as listed

below:

RxD (P3.0): Serial input port.

TxD (P3.1): Serial output port.

INT0 (P3.2): External interrupt.

INT1 (P3.3): External interrupt.

T0 (P3.4): Timer 0 external input.

T1 (P3.5): Timer 1 external input.

WR (P3.6): External data memory write strobe.

RD (P3.7): External data memory read strobe.



Reset (RST): A high on this pin for two machine cycles while the

oscillator is running, resets the device. An internal

diffused resistor to VSS permits a power-on reset using

only an external capacitor to VCC.

Address Latch: Output pulse for latching the low byte of the address

Enable (ALE) during an access to external memory. In normal

operation, ALE is emitted at a constant rate of 1/6 the

oscillator frequency, and can be used for external timing

or clocking. Note that one ALE pulse is skipped during

each access to external data memory. ALE can be

disabled by setting SFR auxiliary.0. With this bit set,

ALE will be active only during a MOVX instruction.

Program Store: The read strobe to external program memory. When

Enable (PSEN) Executing code from the external program memory, PSEN

is activated twice each machine cycle, except that two

PSEN activations are skipped during each access to

external data memory. PSEN is not activated during

fetches from internal program memory.



External Access Enable/Programming Supply Voltage (EA/VPP):

EA must be externally held low to enable the device to

fetch code from external program memory locations

0000H to the maximum internal memory boundary. If

EA is held high, the device executes from internal

program memory unless the program counter contains an

address greater than 0FFFH for 4 k devices, 1FFFH for 8

k devices, 3FFFH for 16 k devices, and 7FFFH for 32 k

devices. The value on the EA pin is latched when RST is

released and any subsequent changes have no effect. This

pin also receives the 12.00 V programming supply

voltage (VPP) during FLASH programming.

Crystal 1(XTAL1): Input to the inverting oscillator amplifier and input

to the internal clock generator circuits.

Crystal 2(XTAL2): Output from the inverting oscillator amplifier.

NOTE

To avoid “latch-up” effect at power-on, the voltage on any pin (other

than VPP) at any time must not be higher than VCC + 0.5 V or VSS – 0.5 V,

respectively.



ARCHITECTURE OF 89C51



OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output, respectively, of

an inverting amplifier which can be configured for use asan on-chip

oscillator, as shown in figure.

OSCILLATOR CONNECTION

Either a quartz crystal or ceramic resonator may be used.

To drive the device from an external clock source, XTAL2 should be

left unconnected while XTAL1 is driven as shown in figure.



EXTERNAL CLOCK DRIVE CONFIGURATION

There are no requirements on the duty cycle of the external clock signal,

since the input to the internal clocking circuitry is through a divide-by-two flip-

flop, but minimum and maximum voltage high and low time specifications must

be observed.

7.2. LCD (LIQUID CRYSTAL DISPLAY)

This section describes the operation modes of LCD and then describes how

to program and interface an LCD to an AT 89C51.

FEATURES:

In recent years the LCD is finding widespread use in replacing LEDs

(seven segment LEDs or other multisegment LEDs). This is due to the

following reasons:

1. Low cost.

2. The ability to display numbers, characters, and graphics. This is in

contrast to LED’s, which are limited to numbers and a few characters

only.



3. Incorporation of a refreshing controller into the LCD, thereby

relieving the CPU of the task of refreshing the LCD. In contrast, the

LED must be refreshed by the CPU (or in some other way) to keep

displaying the data.

4. Ease of programming for characters and graphics.

LCD PIN DIAGRAM:

DB7L+L-

LAMPEX16106

13141516

789101112

123456

V

DB6

s sVddVoRS

R/WEN

DB0DB1DB2DB3DB4DB5

FIG 7.2 LCD PIN DIAGRAM



DESCRIPTION:

The LCD has 16 pins. The function of each pin is given in the following table 7.2

PIN SYMBOL I/O DESCRIPTION

1 Vss --- Ground

2 VDD --- +5V power supply

3 VO --- Power supply to control contrast

4 RS IRS=0 to select command register,

RS=1 to select data register

5 R/W I R/W=0 for writeR/W=1 for read

6 E I/O Enable

7 DB0 I/O The 8-bit data bus







14 DB7 I/O The 8-bit data bus15 L+ - Back Light16 L- - Back Light

FIG 7.2 LCD PIN DESCRIPTION



INTERFACING 4- BITS:

Normally there are eight data bits available in the LCD. Here there are

only four data bits are used to interface LCD with the microcontroller. The

following procedure helps how to interface a 4-bit.


POWER ON

WAIT FOR MORE THAN 15 ms FOR VDD

TO RISE TO 4.5V RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 0

WAIT FOR MORE THAN 4.1 ms

WAIT FOR MORE THAN 100 s

RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 0

0 0 0 0 1 0

RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 0

0 0 0 0 1 0A


FUNCTION SET

CURSOR DISPLAY SHIFT

ENTRY MODE SET

CLEAR DISPLAY

ABBREVIATIONS:

I/D = 1 Increment

I/D = 0 Decrement

S = 1 Accompanies display shift

S/C = 1 Display shift

S/C = 0 Cursor move

R/L = 1 Shift to the right

R/L = 0 Shift to the left

DL = 1 8 bits

DL = 0 4 bits

N = 0 1 line


RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 0 0 0 N F * * 0 0 0 0 0 1 0 0 S/C R/L * * 0 0 0 0 0 0 0 0 0 1 1/D SH 0 0 0 0 0 0 0 0 0 0 0 1

INITIALIZATION ENDS

A


F = 1 5x10 dots

F = 0 5x7 dots

HOW TO CONNECT MICROCONTROLLER WITH LCD?

2

34

56789

1011121314

15

16

V oRSR/WE N

DB 0DB 1DB 2

DB 3DB 4DB 5

DB 6DB 7

L+

L-

L

C

D

1V ss

V dd10 K P RE S E T

P1 .1 P1 .2 P1 .3

P1 .4P1 .5

P1 .6

P1 .7

AT 8 9 C5 1

R S R /W EN

+ V cc

FIG 7.2 MICROCONTROLLER WITH LCD



CIRCUIT DESCRIPTION:

There are sixteen pins available in the LCD. They are VSS, VDD, VO,

R/W, RS, EN, DB0-DB7, L+ and L-. The microcontroller has connected

with the LCD through Port 1. The VSS, VDD and VO are connected with GND,

+VCC and 10K Preset. The port pins P1.1, P1.2, and P1.3 are connected with

RS, R/W, and EN. From the data bits DB0 – DB7, the DB4 -DB7 is

connected with P1.4 – P1.7. The following program shows the LCD

initialization with microcontroller.



7.3. Introduction

The 555 timer is a highly stable device

for generating accurate time delay or oscillation. Signifies corporation

first introduced this device as the SE555/NE 555 and it is available in

two package styles,8-pin circular style,TO-99 can or 8-pin mini DIP

or as 14-oin DIP. There is also available counter timer such as Exira’s

XR-2240 which contains a 555 timer plus a programmable binary

counter in a single 16-pin package. A single 555 counter can provide

time delay ranging from microseconds to hours whereas counter timer

can have a maximum timing range of days.

The 555 timer can be used with supply voltage in the range of

+5v to +18v and can drive load up to 200mA.It is compatible with

both TTL and CMOS logic circuits. Because of the wide range of



supply voltage, the 555 timer is versatile and easy to use in various

applications. Various applications include oscillator, pulse generator,

ramp and square wave generator, monoshot multivibrator, burglar

alarm, traffic light control and voltage monitor etc

Ground Vcc

Trigger Discharge

Output 555 Threshold

Reset control voltage

Description of Functional Diagram

Figure 7.3 gives the pin diagram and fig.7.3 gives the functional

diagram for 555 IC timer. Referring to Fig.7.3, three 5k internal

resistors act as voltage divider, providing bias voltage of (2/3)Vcc to

the upper comparator(UC) and (1/3)Vcc to the lower

comparator(LC),where Vcc is the supply voltage. Since these two

voltages fix the necessary comparator threshold voltage, they also aid



in determining the timing interval .It is possible to vary time

electronically too, by applying a modulation voltage to the control

voltage input terminal (pin5).In applications where no such

modulation is intended, it is recommended by manufacturers that a

capacitor (0.01F) be connected between control voltage terminal(pin

5) and ground to by-pass nose or ripple from the supply.

In the standby state, the output Q of the control flip-

flop (FF) is HIGH. This makes the output LOW because of power

amplifier, which is basically an inverter. A negative going trigger

pulse is applied to pin 2 and should have its dc level greater than the

threshold level of the lower comparator. At the negative going edge of

the trigger, as the trigger passes through (Vcc/3), the output of the

lower comparator goes HIGH and sets the FF. During the positive

excursion, when the threshold voltage at pin 6 passes through (2/3)

Vcc, the output of the upper comparator goes HIGH and resets the FF.



The reset input (pin 4) provides a mechanism to reset the FF

in a manner, which overrides the effect of any instruction coming to

FF from lower comparator. This overriding reset is effective when the

reset input is less than about 0.4V.

When reset this reset is not used, it is returned to Vcc. The

transistor Q2 serves as a buffer to isolate the reset input from the FF.

And the transistor Q1.The transistor Q2 is driven by an internal

reference voltage Vref obtained from the supply voltage Vcc.


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