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Code: 7CS4
Se%ester II
Global Institute Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
In)e. - ourse /ile
/aculty 4 4ean
*erforance of 'tudents in +id Ter Eas
51SE /I6E
+id Ter Eas
14 *erforance of Assignent //
11 =uestion >an? /
10 +id ter =uestion *apers 4
1& +odel Test *apers .
- . -
Global Institute Technology, Jaipur (Approved by AICTE
and Affiliated to T!, "ota#
51SE /I6E
.@ ;esignation % Assistant *rofessor
3ae of the *rograe % >@Tech >atch % .44-.41.
>ranch % C'E 'eester % )II
Title of the 'ub6ect % CA; for )2'I 'ub6ect Code % 9C'&
C5E 'ub6ect 3o@ of 'tudents% 9.
- 0 -
*ote to the /aculty 9e%ber on ho: to use this course 8ile
8or%at;
1@ Tie Table and syllabus copy ust be enclosed@
.@ *lease attach the +ar?s 2ist of the 'tudents in respect of +TE I
(+id Ter Ea#, and +TE II for this sub6ect
in your Course ile@ 0@ TTT (Tie rae Tie Table7 Course *lan#@
&@ 2ecture *lan@
@ Tutorial 'heet (If reBuired, as per the syllabus#@
/@ 2ist of Assignents 7 'einar Topics given to students should also
be included in the Course ile@ 9@ !nit Test@
@ 2ab anual if reBuired@
8@ +odel =uestion *aper of the sub6ect hich ould be distributed to
the students, should be included in the
Course ile *apers (=uestion >an? of iportant =uestions#@ 14@
=uestion of previous years (!niversity# @
11@ +id D Ter =uestion *aper ( I II#@
1.@ *erforance of the unit test should the enclosed@
10@ Grading of Assignent@ 1&@ *hotocopy of the best and the
average anser sheets of +TE I II, should be included in the Course
ile@
1@ *hotocopy of the best and the average assignent copies should be
enclosed in the course file@
(Approved by AICTE and Affiliated to T!, "ota#
51SE /I6E
$ear % &th
'e % )II
.@ ;esignation % Assistant *rofessor
b# 'coring above /4 % FFFFFFFFFFFFFFFFFFF@
2 51SE P67*
(*lease rite ho you intend to cover the syllabus% i@e@ coverage of
!nits by lecturers, guest lecturers, design eercises, solving
nuerical probles, deonstration of odels, odel preparation, or by
assignent, etc@#
3 9ET4 / E7657TI*
0@1 +id Ter Eainations (+TE I II#
0@. Assignent 7 'eesters
0@0 +ini *ro6ects
0@ Ter End Eaination
0@/ 5thers (!nit D Test *apers#
6ist out any ne: topic <s= or any inno>ation you :oul)
like to intro)uce in teaching the sub(ect in this se%ester
?
Signature o8 ea) o8 the 4epart%ent Signature o8 /aculty
4ate 4ate
51SE /I6E
.@ ;esignation % Assistant *rofessor
- -
(Approved by AICTE and Affiliated to T!, "ota#
51SE /I6E
.@ ;esignation % Assistant *rofessor
!nit I
Copleity in icroelectronic circuit design and +oores 2a, design
styles Dull custo design,
standard-cell design, *rograable 2ogic ;evices, ield *rograable
Gate Arrays, ;esign 'tages,
Coputer-Aided 'ynthesis and 5ptiiHations, design flo and related
probles@
!nit II
>oolean functions and its representations D co-factor, unite,
derivatives, consensus and soothing tabular
representations and >inary ;ecision ;iagra (>;;#, 5>;;,
5>;; and >ryants reduction algorith
and ITE algorith@ :ardare abstract odels D structures and logic
netor?s, 'tate diagra, data-flo
and seBuencing graphs, hierarchical seBuencing graphs@ Copilation
and behavioral optiiHations@
!nit III
Architectural 'ynthesis D Circuit description and proble
definition, teporal and spatial doain
scheduling, synchroniHation proble@ 'cheduling algoriths D A'A* and
A2A* scheduling algoriths,
scheduling under constraints, relative scheduling, list scheduling
heuristic@ 'cheduling in pipelined
circuits@
- / -
esource 'haring >inding in seBuencing graphs for resource
doinated circuits, sharing of registers
and busses binding variables to registers@ To-level logic
optiiHation principles D definitions and eact
logic iniiHations@
!nit )
*hysical ;esign@ loor planning D goals and ob6ectives@ Channel
definition, I75 and poer planning@
Cloc? *lanning@ *laceent D goals and ob6ectives@ *laceent
algoriths@ Iterative iproveent
algoriths@ 'iulated Annealing@ Tiing-driven *laceent@ Global
routing D goals and ob6ectives@ Global
routing ethods@ Tiingdriven global routing@ ;etailed outing D goals
and ob6ectives@ 2eft-edge
algorith@ Constraints and routing graphs@ Channel routing
algoriths@ )ia iniiHation@ Cloc? routing,
poer routing, circuit etraction and ;esign ule Chec?ing
Te.tbooks%
1@ >"1@ G@;@ +icheli, K'ynthesis and 5ptiiHation of ;igital
CircuitsL, +cGra-:ill
.@ >".@ +ichael John 'ebastian 'ith@ Application-'pecific
Integrated Circuits@ Addison-<esley
(;onloaded at% httpiroiseue)ucnbooksasics=
1e8erences%
1@ >"&@ '@ 'ait and :@ $oussef,L)2'I *hysical ;esign
Autoation theory and practiceL
Signature o8 ea) o8 the 4epart%ent Signature o8 /aculty
- 9 -
4ate 4ate
Global Institute Technology, Jaipur (Approved by AICTE
and Affiliated to T!, "ota#
*erforance of 'tudents in
+id Ter Eas
$ear % &th
'e % )II
.@ ;esignation % Assistant *rofessor
S *o 1oll *o 'tudent 3ae 9a. 9arks- 20
!Ter% 2Ter% 7>erage
- -
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2esson 3o@ % I ;uration of 2esson% 9
0@ Title % Introduction to +icroelectronics Circuits
S* Topic Ti%e
7llotte)
1 Introduction, Copleity in icroelectronic circuit design and
+oores
2a 1
standard-cell design 1
1
1
1
5ptiiHations 1
Teaching Aids%-
Teaching *oints%-
1e8erence 1ea)ings-
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2esson 3o@ % II ;uration of 2esson% /
0@ Title % >oolean functions and its representations
S* Topic Ti%e
.
1
0 5>;;, 5>;; and >ryants reduction algorith and ITE
algorith
1
& :ardare abstract odels D structures and logic netor?s, 'tate
diagra
1
1
1
Teaching Aids%-
Teaching *oints%-
1e8erence 1ea)ings-
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2esson 3o@ % I) ;uration of 2esson%
0@ Title % Architectural Synthesis
S* Topic Ti%e
1
1
1
& 'cheduling algoriths D A'A* and A2A* scheduling algoriths
1
5 scheduling under constraints
1
1
Teaching Aids%-
Teaching *oints%-
1e8erence 1ea)ings-
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2esson 3o@ % I) ;uration of 2esson% /
0@ Title % Resource Sharing & Bining
S* Topic Ti%e
7llotte)
.
1
1
1
1
1
Teaching Aids%-
Teaching *oints%-
1e8erence 1ea)ings-
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2esson 3o@ % ) ;uration of 2esson%
0@ Title % !hysical "esign
S* Topic Ti%e
1
.
Channel definition, I75 and poer planning, Cloc? *lanning@ *laceent
1
0 *laceent algoriths@ Iterative iproveent algoriths
1
& 'iulated Annealing@ Tiing-driven *laceent@ Global routing
D
goals and ob6ectives 1
1
1
7 Constraints and routing graphs, Channel routing algoriths@ )ia
iniiHation 1
8 Cloc? routing, poer routing, circuit etraction and ;esign ule
Chec?ing 1
2evel of ;ifficulty (for faculty#% Tough Easy
Teaching Aids%-
Teaching *oints%-
1e8erence 1ea)ings-
$ear % &th
Technology, Jaipur (Approved by AICTE and Affiliated to T!,
"ota#
51SE /I6E
'e % )II
.@ ;esignation % Assistant *rofessor
Gui)elines to Stu)y the Sub(ect
The desi"n o# e$e%&!oni% %i!%ui&s %an 'e a%hie(ed
a& many di)e!en&
!e*nemen& $e(e$s #!om &he mos& de&ai$ed $ayou&
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a!%hi&e%&u!es+ ,i(en &he %om$e.i&y o# Ve!y a!"e
%a$ed In&e"!a&ed
i!%ui&s VI hi%h is #a! 'eyond human a'i$i&y %omu&e!s
a!e
in%!easin"$y used &o aid in &he desi"n and
o&imi6a&ion !o%esses+ I& is no
$on"e! e7%ien& &o use manua$ desi"n &e%hniues in hi%h
ea%h $aye! is
hand e&%hed o! %omosed 'y $ayin" &ae on *$m due &o
&he &ime %onsumin"
!o%ess and $a% o# a%%u!a%y+ The!e#o!e omu&e! Aided Desi"n
AD
&oo$s a!e hea(i$y in(o$(ed in &he desi"n !o%ess+ In
&odays ma!e& &he!e
a!e $en&y o# VI AD &oo$s; hoe(e! mos& o# &hem a!e
e.ensi(e and
!eui!e hi"h e!#o!man%e $a&#o!ms+ e$e%&in" an a!o!ia&e
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a%ademi% use is %onside!ed as one o# &he ey %ha$$en"es in
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desi"n %ou!ses+ In &his ae! num'e! o# oen-sou!%e and #!eea!e
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&oo$s a!e !esen&ed and e(a$ua&ed+ Based on &he
o'<e%&i(es o# &he use!
&his su'<e%& #u!nishes "uide$ines &ha& he$ in
se$e%&in" &he mos&
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a VI
desi"n %ou!se+
51SE /I6E
.@ ;esignation % Assistant *rofessor
0@ ;epartent % ECE
n co%pletion o8 this Sub(ect ourse the stu)ents shall be able
to
S*o b(ecti>es utco%es
! Ability to apply ?noledge of basic digital
electronics, physical science, Graph theory, >asic
concepts in )2'I CA; to odel and analyHe soe
;igital Circuits
;evices
2
Ability to design ipleent and analyHe basic digital
coponents and circuits
design, *GAs, Architectural 'ynthesis
3 >asic s?ill in ethods of design and analysis across a
broad range of electronicsl and coputer engineering
areas
:ardare abstract odels, Copilation
and behavioral optiiHations, *hysical
;esign
fabrication techniBues ithin a student selected
electrical and coputer engineering concentration
area
>inding, To-level logic optiiHation
principles, loor planning, *laceent,
Global routing,
and ;esign ule Chec?ing
necessary for engineering practice
Architectural 'ynthesis, *hysical ;esign,
Signature o8 /aculty
4ate
*ote /or each o8 the +JETIE in)icate the appropriate 5T9ES to be
achie>e)
Global Institute of Technology,
51SE /I6E
$ear % &th
'e % )II
.@ ;esignation % Assistant *rofessor
The e.pecte) outco%es o8 the ourse Sub(ect are
S*o General ategories o8 utco%es Speci8ic utco%es o8 the ourse a
Ability to apply ?noledge of basic digital
electronics, physical science, Graph theory,
>asic concepts in )2'I CA; to odel and
analyHe soe ;igital Circuits
'tudy of >asics of CA; )2'I
b Ability to design ipleent and analyHe
basic digital coponents and circuits
'tudy of >asics of ;igital 'ystes and their
Ipleentation
across a broad range of electrical and
coputer engineering areas
fabrication techniBues ithin a student
selected electrical and coputer engineering
concentration area e Ability to use techniBues, '?ills and
odern
tools necessary for engineering practice
'ynthesis of Tools used for CA; )2'I and ;esign +ethodologies
b(ecti>es ? utco%e 1elationship 9atri. <In)icate the
relationship by . %ark=
- 19 -
(Approved by AICTE and Affiliated to T!, "ota#
51SE /I6E
.@ ;esignation % Assistant *rofessor
o%pletion
Perio)s
! 5nit !-
0!0B!! 0!0B!! C
3 5nit-3- Architectural Synthesis
!#!0!! !#!0!! #
$ 5nit-$- !hysical "esign
0A!!!! 0A!!!! A
Total *o o8 Instruction Perio)s a>ailable 8or the course ours
Perio)s
- 18 -
(Approved by AICTE and Affiliated to T!, "ota#
51SE SE456E<5nit Dise=
5*IT - I
.@ ;esignation % Assistant *rofessor
Perio)s
& utco%e
icroelectronic circuit design and
'ei Custo ;esign styles standard-cell design
>"-17/-11
boo?s7asics7>oo?.7C:417 C:41@1@htNpgfIdO1001
474711 design flo and related probles
/ 1.74711 ;esign 'tages, >"-171.-1&
9 174711 Coputer-Aided 'ynthesis and 5ptiiHations
>"-171&-18
Signature o8 /aculty
4ate
3ote % 1@ E3'!E T:AT A22 T:E T5*IC' '*ECIIE; I3 T:E C5!'E AE
+E3TI53E;@
.@ A;;ITI53A2 T5*IC' C5)EE;, I A3$, +A$ A2'5 >E '*ECIIE; I3
>52;@
0@ +E3TI53 T:E C5E'*53;I3G C5!'E 5>JECTI)E A3; 5!TC5+E 3!+>E'
AGAI3'T EAC: T5*IC@
(Approved by AICTE and Affiliated to T!, "ota#
51SE SE456E<5nit Dise=
5*IT ? II
.@ ;esignation % Assistant *rofessor
Perio)s
utco%e
representations D co-factor, unite, derivatives,consensus and
soothing
. >"-17/9-9&
>"-1790-9
0 .74711 5>;;, 5>;; and >ryants reduction algorith and
ITE
algorith
>"-179/-0
& ./74711 :ardare abstract odels D structures and logic
netor?s, 'tate
diagra
hierarchical seBuencing graphs
optiiHations@
4ate
3ote % 1@ E3'!E T:AT A22 T:E T5*IC' '*ECIIE; I3 T:E C5!'E AE
+E3TI53E;@
.@ A;;ITI53A2 T5*IC' C5)EE;, I A3$, +A$ A2'5 >E '*ECIIE; I3
>52;@
0@ +E3TI53 T:E C5E'*53;I3G C5!'E 5>JECTI)E A3; 5!TC5+E 3!+>E'
AGAI3'T EAC: T5*IC@
- .1 -
Global Institute
of Technology, Jaipur (Approved by AICTE and Affiliated to
T!, "ota#
51SE SE456E<5nit Dise=
5*IT ? I
.@ ;esignation % Assistant *rofessor
Perio)s
& utco%e
description and proble definition
scheduling
A2A* scheduling algoriths
/ 1748711 relative scheduling >"-17180-189
9 1/748711 'cheduling ith resource constraints ,
list scheduling heuristic
pipelined circuits
Signature o8 /aculty
4ate
3ote % 1@ E3'!E T:AT A22 T:E T5*IC' '*ECIIE; I3 T:E C5!'E AE
+E3TI53E;@ .@ A;;ITI53A2 T5*IC' C5)EE;, I A3$, +A$ A2'5 >E
'*ECIIE; I3 >52;@
0@ +E3TI53 T:E C5E'*53;I3G C5!'E 5>JECTI)E A3; 5!TC5+E 3!+>E'
AGAI3'T
EAC: T5*IC@
51SE SE456E<5nit Dise=
5*IT ? I
.@ ;esignation % Assistant *rofessor
Perio)s
& utco%e
1 40714711 esource 'haring >inding in seBuencing graphs for
resource
doinated circuits
0 >"-17.04-.&4
0 49714711 binding variables to registers@ >"-17.&-.4
& 14714711 To-level logic optiiHation
principles
>"-17.94-.9/
iniiHations
>"-17.99-.0
>"-17.-.81
Signature o8 /aculty
4ate
3ote % 1@ E3'!E T:AT A22 T:E T5*IC' '*ECIIE; I3 T:E C5!'E AE
+E3TI53E;@
.@ A;;ITI53A2 T5*IC' C5)EE;, I A3$, +A$ A2'5 >E '*ECIIE; I3
>52;@
0@ +E3TI53 T:E C5E'*53;I3G C5!'E 5>JECTI)E A3; 5!TC5+E 3!+>E'
AGAI3'T EAC:
T5*IC@
(Approved by AICTE and Affiliated to T!, "ota#
51SE SE456E<5nit Dise=
5*IT ?
$ear % &th
'e % )II
.@ ;esignation % Assistant *rofessor
Perio)s
& utco%e
goals and ob6ectives & http%77iroi@seu@edu@cn7
boo?s7asics7>oo?.7
planning, Cloc? *lanning@ *laceent
0 01714711 *laceent algoriths@ Iterative
iproveent algoriths
& 41711711 'iulated Annealing@ Tiing-driven
*laceent@ Global routing D goals
and ob6ectives
driven global routing
ob6ectives 2ef-edge algorith
Channel routing algoriths@ )ia
iniiHation
etraction and ;esign ule Chec?ing
8 4711711 eedial Class
Signature o8 /aculty
4ate
3ote % 1@ E3'!E T:AT A22 T:E T5*IC' '*ECIIE; I3 T:E C5!'E AE
+E3TI53E;@
.@ A;;ITI53A2 T5*IC' C5)EE;, I A3$, +A$ A2'5 >E '*ECIIE; I3
>52;@ 0@ +E3TI53 T:E C5E'*53;I3G C5!'E 5>JECTI)E A3; 5!TC5+E
3!+>E' AGAI3'T EAC:
T5*IC@
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
6ET51E P67*
.@ 2ecture 3o@ % 1 ;uration of 2ecture % inutes
'@35@ Topic% Tie
0 +oores 2a 14
2evel of ;ifficulty (for faculty#% Tough Easy Teaching Aids%-
1e8erence 1ea)ings-
- . -
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2ecture 3o@ % . ;uration of 2ecture % inutes
'@35@ Topic% Tie
0 standard-cell design 14
Teaching Aids%-
1e8erence 1ea)ings-
- ./ -
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2ecture 3o@ % 0 ;uration of 2ecture % inutes
'@35@ Topic% Tie
2evel of ;ifficulty (for faculty#% Tough Easy
Teaching Aids%-
1e8erence 1ea)ings-
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2ecture 3o@ % & ;uration of 2ecture % inutes
'@35@ Topic% Tie
Teaching Aids%-
1e8erence 1ea)ings-
- . -
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2ecture 3o@ % ;uration of 2ecture % inutes
'@35@ Topic% Tie
. related probles to ;esign flo 04
2evel of ;ifficulty (for faculty#% Tough Easy
Teaching Aids%-
1e8erence 1ea)ings-
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2ecture 3o@ % / ;uration of 2ecture % inutes
'@35@ Topic% Tie
Teaching Aids%-
1e8erence 1ea)ings-
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2ecture 3o@ % 9 ;uration of 2ecture % inutes
'@35@ Topic% Tie
. 5ptiiHations 1
Teaching Aids%-
1e8erence 1ea)ings-
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2ecture 3o@ % ;uration of 2ecture % inutes
'@35@ Topic% Tie
2evel of ;ifficulty (for faculty#% Tough Easy
Teaching Aids%-
1e8erence 1ea)ings-
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2ecture 3o@ % 8 ;uration of 2ecture % inutes
'@35@ Topic% Tie
Teaching Aids%-
1e8erence 1ea)ings-
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2ecture 3o@ % 14 ;uration of 2ecture % inutes
'@35@ Topic% Tie
& ITE algorith 14
Teaching Aids%-
1e8erence 1ea)ings-
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2ecture 3o@ % 11 ;uration of 2ecture % inutes
'@35@ Topic% Tie
0 'tate diagra .4
Teaching Aids%-
1e8erence 1ea)ings-
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2ecture 3o@ % 1. ;uration of 2ecture % inutes
'@35@ Topic% Tie
. hierarchical seBuencing graphs .
Teaching Aids%-
1e8erence 1ea)ings-
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2ecture 3o@ % 10 ;uration of 2ecture % inutes
'@35@ Topic% Tie
. evies 04
1e8erence 1ea)ings-
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
6ET51E P67*
.@ 2ecture 3o@ % 1& ;uration of 2ecture % inutes
'@35@ Topic% Tie
2evel of ;ifficulty (for faculty#% Tough Easy
Teaching Aids%-
1e8erence 1ea)ings-
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2ecture 3o@ % 1 ;uration of 2ecture % inutes
'@35@ Topic% Tie
. spatial doain scheduling .
Teaching Aids%-
1e8erence 1ea)ings-
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2ecture 3o@ % 1/ ;uration of 2ecture % inutes
'@35@ Topic% Tie
Teaching Aids%-
1e8erence 1ea)ings-
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2ecture 3o@ % 19 ;uration of 2ecture % inutes
'@35@ Topic% Tie
Allotted
1 'cheduling algoriths D A'A* and A2A* scheduling algoriths 4
2evel of ;ifficulty (for faculty#% Tough Easy
Teaching Aids%-
1e8erence 1ea)ings-
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2ecture 3o@ % 1 ;uration of 2ecture % inutes
'@35@ Topic% Tie
2evel of ;ifficulty (for faculty#% Tough Easy
Teaching Aids%-
1e8erence 1ea)ings-
- &. -
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2ecture 3o@ % 18 ;uration of 2ecture % inutes
'@35@ Topic% Tie
Teaching Aids%-
1e8erence 1ea)ings-
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2ecture 3o@ % .4 ;uration of 2ecture % inutes
'@35@ Topic% Tie
. list scheduling heuristic .
Teaching Aids%-
1e8erence 1ea)ings-
- && -
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2ecture 3o@ % .1 ;uration of 2ecture % inutes
'@35@ Topic% Tie
0 evies 04
Teaching Aids%-
1e8erence 1ea)ings-
- & -
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2ECT!E *2A3
.@ 2ecture 3o@ % .. ;uration of 2ecture % inutes
'@35@ Topic% Tie
. >inding in seBuencing graphs for resource doinated circuits
.
2evel of ;ifficulty (for faculty#% Tough Easy
Teaching Aids%-
1e8erence 1ea)ings-
- &/ -
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2ecture 3o@ % .0 ;uration of 2ecture % inutes
'@35@ Topic% Tie
Teaching Aids%-
1e8erence 1ea)ings-
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2ecture 3o@ % .& ;uration of 2ecture % inutes
'@35@ Topic% Tie
2evel of ;ifficulty (for faculty#% Tough Easy
Teaching Aids%-
1e8erence 1ea)ings-
- & -
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
6ET51E P67*
.@ 2ecture 3o@ % . ;uration of 2ecture % inutes
'@35@ Topic% Tie
2evel of ;ifficulty (for faculty#% Tough Easy Teaching Aids%-
1e8erence 1ea)ings-
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Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2ecture 3o@ % ./ ;uration of 2ecture % inutes
'@35@ Topic% Tie
2evel of ;ifficulty (for faculty#% Tough Easy
Teaching Aids%-
1e8erence 1ea)ings-
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2ecture 3o@ % .9 ;uration of 2ecture % inutes
'@35@ Topic% Tie
2evel of ;ifficulty (for faculty#% Tough Easy Teaching Aids%-
1e8erence 1ea)ings-
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Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2ecture 3o@ % . ;uration of 2ecture % inutes
'@35@ Topic% Tie
Teaching Aids%-
1e8erence 1ea)ings-
- . -
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2ecture 3o@ % .8 ;uration of 2ecture % inutes
'@35@ Topic% Tie
Teaching Aids%-
1e8erence 1ea)ings-
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2ecture 3o@ % 04 ;uration of 2ecture % inutes
'@35@ Topic% Tie
0 Cloc? *lanning@ .4
1e8erence 1ea)ings-
- & -
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2ECT!E *2A3
.@ 2ecture 3o@ % 01 ;uration of 2ecture % inutes
'@35@ Topic% Tie
. Iterative iproveent algoriths .
2evel of ;ifficulty (for faculty#% Tough Easy
Teaching Aids%-
1e8erence 1ea)ings-
- -
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2ECT!E *2A3
.@ 2ecture 3o@ % 0. ;uration of 2ecture % inutes
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. Tiing-driven *laceent@ .
2evel of ;ifficulty (for faculty#% Tough Easy
Teaching Aids%-
1e8erence 1ea)ings-
- / -
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Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2ecture 3o@ %00 ;uration of 2ecture % inutes
'@35@ Topic% Tie
Teaching Aids%-
1e8erence 1ea)ings-
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Affiliated to T!, "ota#
2ECT!E *2A3
.@ 2ecture 3o@ % 0& ;uration of 2ecture % inutes
'@35@ Topic% Tie
. 2ef-edge algorith .4
Teaching Aids%-
1e8erence 1ea)ings-
- -
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2ECT!E *2A3
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'@35@ Topic% Tie
. Channel routing algoriths )ia iniiHation 04
2evel of ;ifficulty (for faculty#% Tough Easy Teaching Aids%-
1e8erence 1ea)ings-
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.@ 2ecture 3o@ % 0/ ;uration of 2ecture % inutes
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& ;esign ule Chec?ing .4
Teaching Aids%-
1e8erence 1ea)ings-
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Affiliated to T!, "ota#
7SSIG*9E*T SEET-I
$ear % &th
'e % )II
.@ ;esignation % Assistant *rofessor
;ate of Assignent% FFFFFF@
;ate of 'ubission% FFFFFF@@ This Assignent corresponds to !nit
3o@I
'1( )*at +, -oore., La/0 E23a+ De,+5 St63e, of -+croe3ectro+c
C+rcu+t,
'!( E23a+ ro5rammab3e Lo5+c De8+ce, + deta+3
'&( E23a+ FA F+e3d ro5rammab3e ate Arra6,;0 <o/ +t +,
D+fferet from -A
-a,= ro5rammab3e ate Arra6,;(
'4( +8e Ad8ata5e, of com2uter A+ded S6t*e,+, ad
o2t+m+>at+o
'"( D+fferet+ate Cu,tom De,+5 St63e /+t* Sem+cu,tom De,+5
St63e
Signature o8 ea) o8 the 4epart%ent Signature o8 /aculty
4ate 4ate
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
7SSIG*9E*T SEET-II
$ear % &th
'e % )II
.@ ;esignation % Assistant *rofessor
This Assignent corresponds to !nit 3o@II
'1()*at +, %oo3ea Fuct+o0 E23a+ *o/ %oo3ea fuct+o, ca be
re2re,eted
'!( E23a+ RO%DD + deta+3 a3,o 5+8e +t, A35or+t*m
'&( E23a+ %r6at., reduct+o a35or+t*m ad I?E a35or+t*m +
deta+3
'4( E23a+ State D+a5ram, ad Data F3o/ D+a5ram, /+t* t*e *e32 of a
Eam23e
'"( De,cr+be Com2+3at+o ad %e*a8+ora3 O2t+m+>at+o + deta+3
Signature o8 ea) o8 the 4epart%ent Signature o8 /aculty
4ate 4ate
- /. -
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
7SSIG*9E*T SEET-III
$ear % &th
'e % )II
.@ ;esignation % Assistant *rofessor
This Assignent corresponds to !nit 3o@III
'1( )*at +, Arc*+tectura3 S6t*e,+,0 E23a+ /+t* t*e *e32 of a
Eam23e
'!( E23a+ ?em2ora3 Doma+ Sc*edu3+5 ad S2at+a3 Doma+ Sc*edu3+5
'&( )*at +, S6c*ro+>at+o rob3em0 E23a+ /+t* t*e *e32 of a
eam23e
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'"( <o/ ,c*edu3+5 ca be ac*+e8ed + 2+2e3+ed c+rcu+t,0 E23a+ /+t*
t*e *e32 of a eam23e
- /0 -
Signature o8 ea) o8 the 4epart%ent Signature o8 /aculty
4ate 4ate
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
7SSIG*9E*T SEET-I
$ear % &th
'e % )II
.@ ;esignation % Assistant *rofessor
This Assignent corresponds to !nit 3o@I)
'1( E23a+ Se@uec+5 5ra2*,0 <o/ Re,ource ,*ar+5 +, doe +
,e@uet+a3 5ra2*,
'!( E23a+ b+d+5 /+t* t*e *e32 of a eam23e a3,o e23a+ *o/ +t +,
d+ffer from 2art+a3
%+d+5
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'4( )*at +, t*e d+fferece bet/ee ,+53e 8a3ued 3o5+c ad mu3t+ 8a3ued
3o5+c
'"( E23a+ o,+t+oa3 Cube Notat+o, /+t* t*e *e32 of a Eam23e
Signature o8 ea) o8 the 4epart%ent Signature o8 /aculty
4ate 4ate
- /& -
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
7SSIG*9E*T SEET-
$ear % &th
'e % )II
.@ ;esignation % Assistant *rofessor
;ate of Assignent% FFFFFF@
;ate of 'ubission% FFFFFF@@ This Assignent corresponds to !nit
3o@)
'1( E23a+ F3oor 3a+5 /+t* +t, oa3, ad Object+8e,
'!( De,cr+be 3acemet A35or+t*m, /+t* +t, A223+cat+o,
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Object+8e,
'4( E23a+ LeftEd5e A35or+t*m
'"( )*at +, C+rcu+t Etract+o ad De,+5 Ru3e C*ec=+50 E23a+
- / -
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
=uestion >an?
$ear % &th
'e % )II
.@ ;esignation % Assistant *rofessor
Unit-1
'1( )*at +, -oore., La/0 E23a+ De,+5 St63e, of -+croe3ectro+c
C+rcu+t,
'!( E23a+ ro5rammab3e Lo5+c De8+ce, + deta+3
'&( E23a+ FA F+e3d ro5rammab3e ate Arra6,;0 <o/ +t +,
D+fferet from -A
-a,= ro5rammab3e ate Arra6,;(
'4( +8e Ad8ata5e, of com2uter A+ded S6t*e,+, ad
o2t+m+>at+o
'"( D+fferet+ate Cu,tom De,+5 St63e /+t* Sem+cu,tom De,+5
St63e,
'$ E23a+ t*e D+fferece bet/ee FA B -A
'7 /*at are t*e 2rob3em, re3ated to t*e De,+5 f3o/
' E23a+ Var+ou, t62e, of O2t+m+>at+o, + -+croe3ectro+c
c+rcu+t,
- / -
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
=uestion >an?
$ear % &th
'e % )II
.@ ;esignation % Assistant *rofessor
'1()*at +, %oo3ea Fuct+o0
'!( E23a+ RO%DD + deta+3 a3,o 5+8e +t, A35or+t*m
'&( E23a+ %r6at., reduct+o a35or+t*m + deta+3
'4( E23a+ State D+a5ram,
'"( De,cr+be Com2+3at+o ad %e*a8+ora3 O2t+m+>at+o + deta+3
'$ E23a+ Data F3o/ D+a5ram, /+t* t*e *e32 of a Eam23e
'7 E23a+ *o/ %oo3ea fuct+o, ca be re2re,eted
' E23a+ I?E a35or+t*m + deta+3
'9 E23a+ <+erarc*+ca3 Se@uec+5 ra2*, /+t* t*e *e32 of a
eam23e
'1# /r+te S*ort ote, o ,tructure, ad 3o5+c et/or=,
- /8 -
(Approved by AICTE and Affiliated to T!, "ota#
=uestion >an?
$ear % &th
'e % )II
.@ ;esignation % Assistant *rofessor
Unit-III
'1( )*at +, Arc*+tectura3 S6t*e,+,0 E23a+ /+t* t*e *e32 of a
Eam23e
'!( E23a+ ?em2ora3 Doma+ Sc*edu3+5
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eam23e
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'"( <o/ ,c*edu3+5 ca be ac*+e8ed + 2+2e3+ed c+rcu+t,0 E23a+ /+t*
t*e *e32 of a eam23e
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=9 E23a+ A2A* scheduling algoriths
= E23a+ S2at+a3 Doma+ Sc*edu3+5
%9 hat is list scheduling heuristicP Eplain
=14 Eplain orce ;irected scheduling
- 94 -
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
=uestion >an?
$ear % &th
'e % )II
.@ ;esignation % Assistant *rofessor
'1( E23a+ Se@uec+5 5ra2*, + deta+3
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3o5+c
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' )*at +, L+,t Or+eted -a+2u3at+o0 E23a+
'9 <o/ Re5+,ter, ad bu,,e, ca be ,*ared0 E23a+
- 91 -
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
=uestion >an?
$ear % &th
'e % )II
.@ ;esignation % Assistant *rofessor
Unit-V
'1( E23a+ F3oor 3a+5 /+t* +t, oa3, ad Object+8e,
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Object+8e,
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'7 E23a+ deta+3ed Rout+5
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'9 )r+te S*ort ote o S+mu3ated Aea3+5
'1# )r+te S*ort ote o C3oc= 3a+5
- 9. -
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
5b6ective =uestion >an?
.@ ;esignation % Assistant *rofessor
(a# ust necessarily be negative
(b# could be negative or positive
(c# ust necessarily be positive
(d# ust necessarily be either Hero or Q )
.@ The output =n of a J-" flip-flop is Hero@ It changes to 1 hen a
cloc? pulse is applied@ The inputs Jn and
"n are respectively
(a# 1 and M
(b# 4 and M
(c# M and 4
(d# M and 1
0@ The larger the A+ of a coputer, the faster is its speed, since
it eliinates
(a# need for 5+
(c# freBuency dis? I75 s
(d# need for a data-ide path
&@ ;>, ;< and ;; directives are used to place data in
particular location or to siply allocate space
ithout preassigning anything to space@ The ;< and ;; directories
are used to generate
(a# offsets
(d#offsets of full address of labels and variables
@ The nuber of bits needed to address &" eory is
(a#/
(b#
(c#1.
(d# 1/
/@ The E'C instruction of 4/ ay have to forats@ In one of the
forats, no eory operand is used@
!nder this forat, the nuber of eternal op-codes (for the
co-processor# hich can be specified isP
(a# /&
(d# 1.
9@ The TA* is one of the interrupts available its I3TE2 4@ <hich
one of the folloing stateents is
true of TA*P
(a# It is level triggered
(b# It is negative edge triggered
(c# It is positive edge triggered
(d# It is both positive edge triggered and level triggered
@ In a 1/-bit icroprocessor, ords are stored in to consecutive eory
locations@ The entire ord can
be read in one operation provided the first
(a# ord is even
(b# ord is odd
(c# eory location is odd
(d# eory address is even
8@ A 0 decoder ith to enable inputs is to be used to address bloc?s
of eory@ <hat ill be the
siHe of each eory bloc? hen addressed fro a siteen bit bus ith to
+'>s used to enable the
decoder
- 9& -
(d# /&"
The folloing @ ites consist of to stateents, one labeled as
RAssertion A R and the other labeled the Reason @ $ou are to eaine
these to stateents carefully and decide if the Assertion A and
the
eason are individually true and if so, hether the eason is a
correct eplanation of the Assertion@
'elect your ansers to these ites using the codes given belo and ar?
your anser sheet accordingly%
Codes%
(a# >oth A and are true and is the correct eplanation of
A@
(b#>oth A and are true but is 35T a correct eplanation of
A@
(c# A is true but is false
(d#A is false but is true
14@ Assertion (A#% TT2 and C+5' cannot be norally used
together@
eason (# % @TT2 operates on a (S 4@.# ) regulated supply voltage
and soe A, hile the C+5'
operates on unregulated supply voltage of 0 to 1 and soe
icroA@
11@ Assertion (A#% +achine language progra is ritten in
headecial@
eason (# % +icroprocessor can understand headecial nuber
syste@
1.@A J" flip-flop has its J input connected to logic level 1 and
its " input to the =
output@ A cloc? pulse is fed to its cloc? input@ The flip-flop ill
no
(a# change its state at each cloc? pulse
(b# go to state 1 and stay there
(c# go to state 4 and stay there
(d# retain its previous state
10@A decade counter reBuires
(d# . flip-flops@
1& The decial value for the >C; coded nuber 44414414
is
(a# /
ay be siplified as
(a# A> C>
(a# one, to
(c# three, to
(d# to, three@
19@1 Increasing the precision of the EA2 data type reBuires using
at least one additional bit in
(a# the antissa
(d# none of the above@
1@ 2et V be the binary operation on rational nubers given
aVbOab.ab@ <hich of folloing are trueP
I@ V is coutative
II@ There is a rational nuber that is aVidentity
- 9/ -
(a# I only
(b# II only
representation of 1 ./ 1/ 0P
(a#
(b# 8
(c# 14
(d#11
.4@ <hich of the folloing cobinations of gates does not allo the
ipleentation
of an arbitrary >oolean functionP
(a# 5 gates and inverters only
(b# 3A3; gates only
(c# 5 gates and eclusive D 5 gates only
(d# 5 gates and 3A3; gates@
.1@<hich logic circuit is the fastestP
(a# TT2
(b# ;T2
(c# T2
..@A half adder has
(a# . inputs and . outputs
(c# 0 inputs and 0 outputs
- 99 -
.0@ The ain advantage of flip-flops over transistor circuit
is
(a# iunity fro noise
(b# lo heating
(d# high propagation@
.&@ The Integrated in6ection 2ogic has higher density of
integration than TT2 because it
(a# does not reBuire transistors ith high current gain and hence
they have saller geoetry
(b# uses bipolar transistor
(d# uses dynaic logic instead of static logic@
.@In a positive edge triggered J" flip-flop, a
lo J and a lo " produce theFF@ state A
high J and a high " ean that the output
ill FF@on the rising edge of the cloc?
(a# activeF@ race
(b# inactive FFdead
(c# inactive F@@toggle
(d# active F@@constant
./@:o any bits does one need to encode all tenty-si letters, ten
sybols, and ten
nueralsP
(d# &/
.9@ Consider the representation of si-bit nubers by tos copleent,
ones
- 9 -
copleent, or by sign O and agnitude@In hich representation is there
overflo
fro the addition of the integers 1444 and 411444 P
(a# Tos copleent only
(b# 'ign and agnitude and ones copleent only
(c# Tos copleent and ones copleent only
(d# All three representations@
.@ <hich of the folloing sets represents a universal logic
failyP
(a#3A3;
(b#M5
(c#3A;
(d# 3one of the above@
.8@ The aiu propagation value in case of 9&44 3A3; gates
is
(a# 1 second
(c# less than .4 nano seconds
(d# less than .4 pico seconds@
04 @ The total nuber of >oolean functions hich can be realiHed
ith your variables
Is P
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
+id Ter =uestion *apers 'e % )II
.@ ;esignation % Assistant *rofessor
oll 3o@ % FFFFFFFFF ;ate % FFFFF@@
Global Institute o8 Technology +Tech -"th Hear ? II SE9,
o%puter Science
Ist 9i) Ter%
7tte%pt all the uestions 7ll uestions carry E@ual 9arks
5nit-!
1# a# <hat are the circuit odelsP ;iscuss of the classification
of odels on the basis of levels and
vies@Eplain g6as?i y-chart for the three vie of a circuitP
b# Eplain different icroelectronics circuit design
stylesP
5r
a# Copare beteen full custo and sei custo design styles P
b# Eplain abstraction levels of a circuit representation and
also discuss corresponding vies ith
the help of a circuit eapleP
5nit-2
.# a# <hat is the >oolean function and also discuss its
representation classified in tabular, logic
epression and >;;s@ b# <hat do you understand by
circuit optiiHationP Eplain its need and the process @
5r
a= Eplain physical design cycle ith appropriate diagraP
a= ;ifferentiate beteen behavioral, structural and physical vies in
circuit odelsP
- 4 -
a# Global routing ethod &
5r
Global Institute o8 Technology +Tech -"th Hear ? II SE9, o%puter
Science
2n) 9i) Ter%
7tte%pt all the uestions 7ll uestions carry E@ual 9arks
5nit-2
&# Consider function fO ab bc and gOac dra 5>;;
corresponding to f or gP
# ;escribe any to feature of hardare description language
given one distinctions beteen
behavioral :;2 and structure :;2P
5nit-3
/# Given the folloing netlist sho to other possible representationP
&
+1% n1,n.,n&
- 1 -
5nit-"
8# ;iscuss sharing and binding for resource doinated circuit
(both hierarchical and non-
hierarichal seBuence#P
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
+odel Test *aper
74 8or 6SI <Set-7=
7tte%pt all the uestions 7ll uestions carry E@ual 9arks
5nit-!
=1 <hat is +oores 2aP Eplain various phases of creating
+icroelectronics chips
5
<hat is the difference beteen *GA and +*GAP Eplain *2;s
1/
=. Consider function f O ab bc ca@ ind out the cofactors ith
respect toc, and >oolean
difference, Consensus and 'oothing, then represent the function in
0 ; >oolean space
5
- . -
5
Eplain +ultiprocessor 'cheduling algorith in detail 1/
=& <rite the Algorith for eact logic iniiHation ith an eaple
also eplain unite functions
5
Eplain logic 5ptiiHation *rinciples ith necessary
;efinitions 1/
= Eplain Channel outing Algorith and Iterative Iproveent
Algorith
5
@ Eplain Integer 2inear *rograing odel ith the help of an eaple
1/
Global Institute of Technology, Jaipur (Approved by AICTE and
Affiliated to T!, "ota#
+odel Test *aper
74 8or 6SI <Set-7=
7tte%pt all the uestions 7ll uestions carry E@ual 9arks
5nit-!
=1 +a?e a Coparison 'tudy of design styles of +icroelectronic
circuits
5
Eplain the various ethods of representation of >oolean
functions 1/
2 Eplain a process for the design syste of digital syste using
appropriate bloc? diagra
5
Eplain ;ataflo and 'eBuencing graph ith the help of an eaple
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Eplain orce ;irected 'cheduling Algorith algorith in detail
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Eplain logic 5ptiiHation *rinciples ith all the necessary
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=@<hat is Circuit Etraction, eplain it in contet to ;esign ule
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