IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 42, NO. I , FEBRUARY 1993 25

Built-In Self-Test Structure for Mixed-Mode Circuits Larry T. Wurtz

Abstract-The complexity of today’s analog integrated cir- cuits and improvements in fabrication densities have made test- ing an important and difficult task. Analog circuit test methods have, traditionally, been limited by the number of externally available test pins. A new BIST structure is presented which provides controllability and observability to analog circuits un- der test with significantly reduced hardware overhead com- pared to previously reported methods. The test structure is equally applicable to digital circuits, and lends itself to auto- mated insertion into circuits under test.

I. INTRODUCTION HE increased complexity required of electronic cir- T cuits and systems coupled with improved VLSI fab-

rication densities has significantly increased the difficulty of adequately testing analog and digital integrated cir- cuits. The marketing pressures have, additionally, in- creased the demand for both quality and the rapid tum- around of integrated circuit (IC) testing. The way in which an IC is tested can determine whether a project succeeds or fails in that testing typically accounts for nearly a third of an IC’s development cycle [l].

Not only have increased circuit densities made testing more difficult, but many integrated circuits today are both analog and digital mixed-mode designs. It has become common for single IC’s to support analog voltage refer- ences, amplifiers, and analog-to-digital converters for sensory electronics, a digital microprocessor for data pro- cessing, and analog electronics to control motor actua- tors, displays, etc. Such analog and digital mixed-mode circuits present a more formidable problem for testing than 100% digital IC’s.

Much work has been reported in the literature to test digital circuits [2]-[7]. Methods including behavioral testing, ad hoc testability techniques, full scan, partial scan, built-in self-test (BIST), and Crosscheck are meth- ods which have been reported to increase the controlla- bility and observability of digital circuits [ 11. Impor- tantly, techniques such as digital BIST structures can be implemented in digital systems in an automated fashion [SI.

Traditionally, analog circuits have been tested with support from a “bed-of-nails” tester which allows access to input and output signals which are normally inacces-

Manuscript received June 25, 1992. This work was supported by the U.S. Army Missile Command, Redstone Arsenal, AL. under Contract DAAHOl -91-D-RWl , task 4.

The author is with the Department of Electrical Engineering, University of Alabama, Box 870286, Tuscaloosa, AL 35487.

IEEE Log Number 9204220.

sible. The increased complexity of analog integrated cir- cuits and the limited number of output pins have made “bed-of-nails’’ testing not only impractical, but impos- sible [9]. Several analog circuit test structures have been reported; however, they are restricted by the number and locations of externally available test points [2]-[7].

One testing approach to the increased accessibility of internal nodes is to incorporate a built-in self-test (BIST) circuit into the unit under test (UUT). BIST designs have been successfully applied to digital circuitry [SI. In fact, of the may new military weapon system designs that I have reviewed, digital BIST structures have been the sin- gle method implemented for the improved testability of large digital subsystems [lo], [ 1 11.

This paper presents a modified BIST structure for test- ing analog circuitry. The structure can be extended to test digital circuitry in mixed-mode systems as well. The new BIST structure requires substantially less hardware to im- plement than previously reported techniques.

11. BIST STRUCTURES In digital circuits, a BIST structure that has been widely

implemented involves a scan-path technique using shift register latches (SRL). Fig. 1 illustrates the technique where latches in the sequential circuit have been replaced with shift register latches, one of which is shown in Fig. 2. In this way, the SRL’s can be connected together to form a single shift register to shift in known node values for enhanced controllability and shift out node values for improved observability [SI.

The SRL is controlled by its A and B inputs. As long as inputs A and B are low, L1 operates as an ordinary latch with CLOCK and DATA IN input signals and the output signal latched at DATA OUT. When the SRL operates as a shift register, data from the previous SRL stage are latched at the output of L2 via input TEST IN on L1. The shift operation is performed by pulsing high input A fol- lowed by a high pulse on input B.

111. ANALOG BIST STRUCTURES By modifying the design concept of the digital BIST

structure, it is simple to construct an analog equivalent. Fig. 3 shows one such analog equivalent, where the SRL of Fig. 2 has been realized by a sample-and-hold (S/H) circuit [ 121.

Fig. 4 illustrates the implementation of the analog shift register (ASR), shown in Fig. 3, as a BIST structure to improve the testability of analog circuits. Each analog test

0018-9456/92$3.00 0 1993 IEEE

26 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 42. NO. 1. FEBRUARY 1993

vantages. The drawbacks are noted by defining the switch timing of Fig. 5 . Switches S 5 , S 6 , and S 7 close and open to simultaneously sample all analog test points. Test point charges are held on capacitors C 1, C2, and C3. Test point three charge is shifted out by closing switch S4. With 34 closed, test point two charge is shifted out by closing switch S 3 . Accordingly, test point charges are shifted out one by one from right to left. The modified structure, ac- cordingly, requires more time to make test data observ- able.

In short, the modified analog BIST structure has the same limitations as the previously described structure,

INPUTS COMBINATIONAL L O G I C OUTPUTS

TEST OUT TEST I N

CLOCK

A

B Fig. 1 . Digital circuit with SRL BIST structure.

OUT

OUT

Fig. 2. Shift register latch (SRL).

TEST VOLTAGE

Fig. 3 . Analog shift register (ASR)

point is isolated from the ASR BIST structure to reduce error introduced by impedance loading. Isolation is ac- complished by using unity-gain buffers which demon- strate high input impedance and low output impedance. The testing arrangement of Fig. 4 allows simultaneous sampling of test points and serial shift-out. High hardware overhead and sizing considerations of the sample-and-hold capacitors are disadvantages of this test scheme. More- over, the analog BIST structure improves observability while doing nothing to enhance controllability. Power supplies for the analog BIST components must be greater than those of the UUT to prevent loss of accuracy due to limited signal swing. In addition, a timing circuit must be designed to control sample-and-hold switches.

Wey recently reported a modified version of his analog BIST structure which is illustrated in Fig. 5 [9]. The ad- vantage of the modified structure is that less circuitry is needed to implement the sample-and-hold components. The reduced hardware requirement does introduce disad-

with the biggest enhancement being reduced hardware overhead at a cost of increased delay time for test data observability.

IV. NEW MIXED-MODE BIST STRUCTURE Fig. 6 illustrates a new BIST structure designed to en-

hance observability. Although initially applied to analog circuits, it is equally applicable to digital circuits. Similar to the analog BIST structures described above, unity-gain buffers provide isolation from the analog UUT. If the dig- ital UUT has sufficient drive at its test points, buffers B3 and B4 are not required. Otherwise, digital buffers can be implemented by two properly sized back-to-back invert- ers. Transmission gates T1-T6 are pulsed on and off one by one to gate analog and digital test point voltages to the output test point TEST OUT.

The new mixed-mode BIST structure provides the same testing function as Wey 's modified analog BIST structure, but requires substantially less hardware to implement. Comparing the output test signal patterns of Wey 's mod- ified structure and the new BIST structure, one would not be able to differentiate the two. The new analog BIST structure does not, however, require sample-and-hold cir- cuits, and therefore does not suffer from the error intro- duced by nonideal buffers and sample-and-hold capacitor charge losses. Importantly, the new BIST can operate over a wide range of clock rates. Like the previous analog BIST structures, a separate power supply is needed to ensure adequate signal swing for the analog UUT.The fact that the new BIST structure does not sample its test points si- multaneously may be considered a disadvantage. For the cases studied, this was not a limitation.

Similar to the previous analog BIST structures, a clock circuit is required to control switching. The previous an- alog BIST structures suggested using static D flip-flops to implement the clock circuit. A preferred clock circuit consists of two-phase static flip-flops (SFF), shown in Fig. 7. The two-phase flip-flop design has been well docu- mented, and requires fewer transistors to implement than the standard D flip-flop. Fig. 8 illustrates the timing se- quence needed at inputs TESTIN and TCLK to properly switch, one by one, switches T l - T 6 on and off.

Analog BIST structures reported to date have only been concerned with enhanced observability in analog circuits. Of importance, the new mixed-mode BIST structure, ad- ditionally, enables enhanced controllability. Fig. 9 illus-

I

INPUT--

TEST

WURTZ: BIST STRUCTURE FOR MIXED-MODE CIRCUITS 27

OUTPUT W I T UNDER TEST ... TEST POINT 1 TEST POINT 2

BUFFER B..

w u T - + ' p & y 'ppw- TEST OUTPUT

INPUT--

I . I

OUTPUT UNIT UNDER TEST ...

TEST POINT 1 TEST POINT 2

TEST INPUT yy-p-*pf c2 TEST OUT

I I

Fig. 5 . Modified analog BIST structure.

ANALOG INPUTS ANALOG UUT DIGITAL UUT ANALOG W T

TEST I N

TSETIN TCLK

PHI PHI-

Fig. 6. Mixed-mode BIST structure for enhanced observability.

TSETIN TSETOUT

TCLK

Fig. 7. Two-phase static flip-flop.

TCLK - T S E T I N

T1- T 2 A

T3 m T 4 - T5 T 6 m

Fig. 8. Mixed-mode BIST switch timing.

trates where control points have been pulled out of the analog circuits under test. Transmission gates allow each path to be cut while a test signal is substituted via test input TEST IN. For example, an analog test voltage may

OUTPUTS

TEST R I T

TSETWT

be applied to TEST IN while transmission gate T1 is turned off and T2 is set on. Again, a clock circuit based on two-phase static flip-flops will provide timing for the BIST transmission gates.

The new BIST structure allows controllability of digital test points through the same mechanism. However, for digital circuit controllability, SRL-based digital BIST structures provide greater controllability with less hard- ware overhead.

V. VLSI FABRICATION CONSIDERATIONS This section describes layout considerations for the an-

alog buffer, switch, and two-phase static flip-flop needed for implementation of the mixed-mode BIST structure. The BIST components were implemented in a 2 pm n-well CMOS process through the MOSIS fabrication service, Information Sciences Institute, University of Southern California, Los Angeles, CA. SPICE.MODEL parame- ters for this process are listed in Table I.

The unity-gain buffer can be implemented with an un- buffered CMOS amplifier, shown in Fig. 10, by applying 100% negative feedback. Values for transistor channel

28 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 42, NO. 1 , FEBRUARY 1993

rcn m r s i m T S E m n

Fig. 9. Mixed-mode BIST stxucture for enhanced controllability. Tcu

TABLE I MOSIS 2 pm n-wELL CMOS.MODEL PARAMETERS

.MODEL NMOS NMOS LEVEL = 2 LD = 0.28U TOX + VTO = 0.587229 KP = 3.84805E-5 GAMMA = 0.922197 PHI = 0.6 U 0 + UEXP = 1.001E-3 UCRIT = 999000 DELTA = 1.59123 VMAX = 1OOOOO XJ = 0.4U + LAMBDA = 2.208002E-2 NFS = 5.033532E11 NEFF = 1.001E-2 NSS = 0 + TPG = 1.0 RSH = 20 CGSO = 5.2E-10 CGDO = 5.2E-10 CJ = 4.5E-4 MJ = 0.5 + CJSW = 6.OE-10 MJSW = 0.33

.MODEL PMOS PMOS LEVEL = 2 LD = 0.28U TOX = 520E-10 NSUB = 2.53495814 + VTO = -0.784085 KP = 1.394594E-5 GAMMA = 0.536443 PHI = 0.6 U 0 = 100

520E-10 NSUB = 4.57578815 200

+ UEXP = 0.171475 UCRIT = 51857.9 DELTA = 1.89818 VMAX = 1OOOOO + XJ = 0.4U LAMBDA = 4.720123E-2 NFS = 8.870574Ell NEFF + NSS = 0 TPG = -1.0 RSH = 55 CGSO = 4E-10 CGDO = 4E-10 CJ = 3.6E-4 + MJ = 0.5 CJSW = 6.OE-10 MJSW = 0.33

1.001E-2

VDD 6 VOLTS

VEE -6 VOLTS

Fig. 10. Unbuffered CMOS amplifier.

width-to-length ( W / L ) ratios and compensation capaci- tance Cc were determined from the design specifications listed in Table I1 and the design procedure discussed in [ 141. Transistor W/ L ratios calculated according to the design procedure are shown in Table 111. From the design procedure and specifications, many transistor W / L ratios were calculated to be less than the minimum channel W / L ratio of 3 pm/2 pm supported by the selected fabrication process. Except for transistors M9-M 1 1 which provide dc bias, transistors with calculated W / L ratios less than the minimum were changed to the minimum to reduce channel area requirements. The result was an amplifier of higher performance than required in the design specifi- cations. The implemented buffer had a unity-gain band- width (GB) and slew rate (SR) of 8 MHz and 26.5 V/ps, respectively, Other amplifier performances are listed in Table 11.

TABLE I1 UNBUFFERED CMOS AMPLIFIER DESIGN SPECIFICATIONS

Design Simulation

A, open-loop A,, closed-loop

VDD

VEE GB SR

CMR

Channel width pdiss

R,,, (Q 8 MHz) R,, (@ 8 MHz)

4000 1

2 PF 6 V

-6 V 1 MHz

- 5 to 5 v < 10 mW

10 v / p s

2 pm - -

- 1

2 PF 6 V

-6 V 8 MHz

26.5 V/ps -6 to 5.04 V

0.43 mW 2 Pm 782 Q

9.4 MQ

TABLE I11 UNBUFFERED CMOS AMPLIFIER COMFQNENT VALUES

Mosfet's W / L Channel Ratios

M9, M10, M11, M12 3 pm/lO pm M8, M5 32 pm/s pm

M7 76 pm/2 pm

cc 0.44 pF M1, M2, M3, M4, M 6 3 pm/2 pm

As indicated earlier, the test structure must be driven from a power supply greater than the UUT to ensure ad- equate signal swing for sampled test voltages. The input common mode ratio (CMR) is important for the unity- gain buffer because the output voltage follows the input. A power supply of +6 V for the unity-gain buffer resulted

WURTZ: BIST STRUCTURE FOR MIXED-MODE CIRCUITS 29

Fig. 13. Two-phase static D flip-flop layout.

Fig. 11. Unbuffered CMOS amplifier layout.

C L K *

C L K X INPUT OUTPUT

INPUT

I C L K

Fig. 12. CMOS transmission gate.

in a CMR of -6 to 5.04 V, which was acceptable for the mixed-mode circuits under test with + 5 V supplies.

Fig. 11 shows the buffer layout which was done using the MAGIC layout editor. MAGIC was obtained from the Department of EECS, University of Califomia, Berkeley, CA. Device dimensions in the 2 pm CMOS process are 125 x 95 pm.

Switches shown throughout the mixed-mode BIST structure may be implemented with simple transmission gates, one of which is shown in Fig. 12. Care must be given to size each transmission gate to drive the capaci- tive load of the output signal path and all other connected transmission gates.

The two-phase static flip-flop, shown in Fig. 7, was used to implement the switch clocking circuit. This flip- flop requires 50% fewer transistors to implement than a standard D flip-flop. Fig. 13 shows the two-phase static D flip-flop layout using the MAGIC layout editor in the 2 pm CMOS process. All transistors are of minimum channel dimensions of 3 X 2 pm. The layout dimensions are 98 X 54 pm.

V. CONCLUSIONS Analog circuit test methods have, traditionally, been

limited by the number of externally available test pins. The analog BIST structures described by Wey did much to improve the observability of analog circuits, but the hardware overhead associated with the BIST structures is

high. The new mixed-mode BIST structure provides con- trollability and observability for both the analog and dig- ital circuits under test. The hardware overhead is signifi- cantly less than that reported by any similar test structure. The new test structure is suitable for automated insertion into circuits under test. Care must, however, be given to ensure that the switches, or transmission gates, are sized properly to drive the capacitance associated with the out- put signal path and other switches connected. Also, an extra power supply is required to ensure that the test struc- ture provides adequate signal swing sampled test volt- ages.

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