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GUIDE:Anushrri mam HIGH-SPEED MIXED-MODE CMOS FULL ADDER CIRCUITS TEAM MEMBERS Hemraj Kapileshwar Ketan Kishan

high speed mixed mode adder

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GUIDE:Anushrri mam

HIGH-SPEED MIXED-MODE CMOSFULL ADDER CIRCUITS

TEAM MEMBERS• Hemraj• Kapileshwar• Ketan• Kishan

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INTRODUCTION• In mixed mode designing the majority not

function in voltage mode is the matching part of majority function in current mode.

• In the current mode, the current which is pulled from the Carry bar transistor must be twice as much as the current from input transistors to satisfy the following

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CURRENT MODE LOGIC

• Current from different branch add on single node.

• I1 + I2 + I3= I(out)

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MAJORITY NOT FUNCTION

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MIXED MODE FULL ADDER 2 (MIXFA2)

• In MixFA2, full adder circuit uses 19 transistors.

• Its output Sum function is based on current mode majority function.

• In this design, the first majority-not gate is implemented with a high-performance Static CMOS bridge circuit.

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MixFA2

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MIXFA2 READING

0 0 0 1 2v 0 21mv

0 0 1 1 2v 1 42mv

0 1 0 1 2v 1 42mv

0 1 1 0 32nv 0 26mv

1 0 0 1 2v 1 42mv

1 0 1 0 0v 0 26mv

1 1 0 0 0v 0 26mv

1 1 1 0 10nv 1 60mv

A B C CARRY BAR SUM

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COMPARISION

T=Transistors & C=Capacitors

HYFA1 16T 4C

HYFA2 16T 3C

HYFA3 15T 3C

HYFA4 16T 4C

HYFA5 12T 4C

MIXFA1 16T

MIXFA2 19T

DESIGN TYPES COMPONENTS USED

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ADVANTAGES

• Higher speed.• Lower components count.• It compromises noise margin.• Smaller area requirement with lesser delay at

low voltage.• Low complexity.

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SOFTWARE

LT spice Linear Technology provides a variety of custom design simulation tools and device models to allow even novice designers to quickly and easily evaluate circuits using high performance switching regulators, amplifiers, data converters, filters and more.

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FUTURE SCOPE

• Will help in reducing power consumption.

• Will help in reducing propagation delay.

• Will help in reducing area of digital circuits.

• Will help in high speed operation of ALU & CPU.

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MIXED MODE FULL ADDER 3 (MIXFA3)

• In MixFA3 full adder output Carry bar function is designed with 3 input Majority Not function logic.

• output Sum function generated in current mode majority function logic style.

• In this design, the majority-not gate is implemented with capacitors.

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MixFA3

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REFERENCES

• International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.2, June 2011 by Subodh Wairya, Rajendra Kumar Nagaria, Sudarshan Tiwari.

• World Applied Sciences Journal 4 (2): 289-294, 2008 by Keivan Navi, Roshanak Zabihi, Majid Haghparast and Touraj Nikobin.

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