Built-In Self-Test and Calibration of Mixed-Signal Devices

Built-In Self-Test and Calibration of Mixed-Signal

DevicesPh.D Final Exam

Wei Jiang

Advisor: Vishwani D. AgrawalUniversity ReaderMinseo Park

Committee Members: Fa F. DaiVictor P. NelsonAdit D. Singh

March 24 2011

Outline

• Introduction• Background• BIST Architecture for Mixed-Signal Devices

– Overview of Proposed Architecture– Test of DAC/ADC– Calibration of DAC

• Sigma-Delta Modulation• Polynomial Fitting Algorithm• Conclusion

Wei Jiang General Final Exam 2

Motivation

• Digital BIST techniques– Defect-oriented– Logic BIST, scan chain, boundary scan,

JTAG, etc• Mixed-Signal BIST techniques

– Specification-oriented– No universally accepted standard– Issues

• Parameter deviation• Process variation


Approach

• Problem– Design a post-fabrication variation-

tolerant process-independent technique for mixed-signal devices

• Solution– Test and characterize mixed-signal

devices using digital circuitry– Use DSP as BIST controller for test pattern

generation (TPG) and output data analysis (ORA)

– Calibrate mixed-signal devicesWei Jiang General Final Exam 4

Mixed-Signal Devices

• Both digital and analog circuitry in single die– DSP usually embedded for data processing– Analog circuitry controllable by digital part

• Converters– Analog-to-digital converter (ADC)

• Flash ADC, successive-approximation ADC, Pipeline ADC, Sigma-Delta ADC

– Digital-to-analog converter (DAC)• PWM/Oversampling DAC, Binary-weighted DAC


Testing of Mixed-Signal Devices• Both digital and analog circuitry need

test• Defects and faults

– Catastrophic faults (hard faults)– Parametric faults (soft faults)

• Test approaches– Functional test (specification oriented)– Structural test (defect oriented)


Digital BIST

• Conventional logic BIST technology• LFSR-based random test; Scan-based

deterministic test• DSP can be TPG and ORA• Digital circuitry must be fault-free

before being used for mixed-signal test

• May be hardware or software based


Faulty Mixed-Signal Circuitry• Good circuitry

– All parameters and characteristics are within pre-defined specified range

• Fault-tolerance factor– Post-fabrication and software-controllable– Trade-off between fault-tolerance of

parameter deviation and calibration resolution

– Larger value for wider fixing range; smaller one for better fixing results

– Fault-tolerance factor may vary for different applications


A Basic Digital BIST Architecture


Digital Circuit-under-test

(CUT)

BIST CONTROLLER

TPG ORA

enable enable

Challenges

• Analog circuitry– No convincing fault model– Difficult to identify faults– Device parameters more susceptible to

process variation than digital circuitry– Fault-free behavior based on a known range

of acceptable values for component parameters

• Large statistical process variation effects in deep sub-micron MOSFET devices


Process Variation

• Parameter variation in nanoscale process• Yield, reliability and cost• Feature size scaling down and performance

improvement• Effects on digital and analog circuitry

– Analog circuitry more affected by process variation– Parameter deviation severed in nanoscale process– System performance degraded when parameter

deviation exceeds beyond tolerant limits


Outline

• Introduction• Background• BIST Architecture for Mixed-Signal

Devices– Overview of Proposed Architecture– Test of DAC/ADC– Calibration of DAC

• Sigma-Delta Modulation• Polynomial Fitting Algorithm• ConclusionWei Jiang General Final Exam 12

Resolution and Non-linearity Error• Resolution: N-bit• Least significant bit

(LSB)

• Non-linearity errors– Differential non-

linearity (DNL)– Integral non-

linearity (INL)

Wei Jiang 13

kLSB

vvDNLINL

LSB

vvDNL

VLSB

kk

ikk

kkk

DDN

0

1

1 1

2

1

General Final Exam

Non-linearity Error of ADC

• Signal values at lower and upper edges of each codes

Wei Jiang 14

kkk

k

ikk

kkk

kkk

kk

kk

DNLINL

LSBDNL

LSB

LSB

2

ˆˆ2

ˆˆ2

ˆˆ

5.0ˆ

5.0ˆ

1

1

2

1

1

General Final Exam

Non-linearity Error of ADC/DAC


Analog input

Dig

ital c

ode

outp

ut

Ideal

Actual (νK)

Ideal

Actual (νK)

Ana

log

outp

ut

Digital code input

Non-linearity error of ADC Non-linearity error of DAC

k

kν

ν

Non-linearity error

Non-linearity

error

Noise and SNR

Wei Jiang 16General Final Exam

input

output

1

-1

Δ/2

-Δ/2

3Δ/2

-3Δ/2

Δ: LSBN: number of bit

76.102.612

1281

log10

128

112

022

1

2

22

10

22

222

NSNR

P

PSNR

P

deeepe

otherwise

eifep

N

noise

signal

N

rms

Outline

• Introduction• Background

• BIST Architecture for Mixed-Signal Devices– Overview of Proposed Architecture– Test of DAC/ADC– Calibration of DAC


Typical Mixed-Signal Architecture


Mixed-Signal System Test Architecture


* F. F. Dai and C. E. Stroud, “Analog and Mixed-Signal Test Architectures,” Chapter 15, p. 722 in System-on-Chip Test Architectures: Nanometer Design for Testability, Morgan Kaufmann, 2008.

Test Architecture

• Digital system– Digital I/O, digital loopback– Digital signal processor (DSP)– TPG and ORA and test control unit

• Mixed-signal system– DAC and ADC, Analog loopback

• Analog system– Analog circuitry– Analog signal I/O, analog I/O loopback


Available Testing Approaches• Servo-loop Method• Oscillation BIST Method• Sigma-Delta Testing Method• FFT-based Testing Method• Histogram Testing Method

– Widely used for testing of on-chip ADC/DAC– Need large amount of samples and slow-

gain current source– Unsuitable for high-resolution converters


Outline




Simplified Mixed-Signal System

Wei Jiang 23General Oral Examination

Proposed Approach


DSP

ADCunder-test

DACunder-test

m-ADC

Signal Generator

Analog System

d-DAC Polynomial evaluation

N

N

NDiagnosis

TPG

TPG

Testing Components

• Analog Signal Generator (ASG)– Linear ramp signals– Sinusoidal signals

• Measuring ADC (m-ADC)– High-resolution and high linearity– First-order single-bit Sigma-Delta ADC

• Dithering DAC (d-DAC)– Low resolution and low cost– Output voltage: specified error-tolerant

range– Polynomial evaluation unit


Design of Ramp Signal Generator


Switch for resetting ramp

I I

I/19.5

ΔV+Vth ΔV

Range: 0 v~ Vdd-ΔV

Carefully chosen to make ΔV ≈ 0

Sinusoidal Testing Signal

• More complex design• Used for dynamic testing (non-

linearity (IP3), dynamic range, harmonic distortion)

• Fast Fourier Transformation (FFT) by DSP required

• Optional in the proposed BIST approach


Testing Components

• Measuring ADC (m-ADC)– First-order single-bit Sigma-Delta ADC– ENOB determined by oversampling ratio

• Dithering DAC (d-DAC)– Low resolution DAC: binary-weighted– Fault-tolerance factor


76.102.68

3log10 3

210 ENOBOSRSNRdB

Outline




Testing Steps

• Diagnosis of testing components• Testing of on-chip ADC using analog

testing signals• Testing of on-chip DAC using

embedded DSP and measuring ADC• Calibration of on-chip DAC using

dithering DAC• Validation of DAC calibration results

using on-chip ADC/DAC


Diagnosis of Testing Components


DSP

DACunder-test

m-ADC

Signal Generator

d-DAC

0

N

NDiagnosis

TPG

TPG

*Assume non-linearities in signal generator and d-DAC do NOT match

Diagnosis of Testing Components• ASG and m-ADC

– Analog signal generated; usually linear ramp– m-ADC measures analog signals– DSP determines gain and offset of measurements

• d-DAC and m-ADC– DSP makes on-chip DAC output constant 0– DSP generates digital test patterns; usually linear

ramp– m-ADC measures d-DAC outputs– DSP determines gain and offset of measurements

•Only situation that fault undetected– ASG and d-DAC have exactly same non-linearity

errors


Testing of ADC

• Similar to histogram testing method


DSPADC

under-test

Signal Generator

Analog System

N

Testing of ADC

• Divided full-range of ADC codes into two equal-size sections

• Sum up measurements of each section

• Lower bound M(0) and upper bound M(K) are discarded because of possible out-of-range measurements


X

s0 s1

0 n/2 n

baxy

Estimating Coefficients


KbaTKKLSB

kfLSB

kMs

KbaTKKLSB

kfLSB

kMs

K

Kk

K

Kk

K

k

K

k

2

122

8

11

1

2

12

8

11

1

1

2/

1

2/1

2/

1

2/

10

2

421

1

2

41

1

3

24

11

011

0

011

010

KK

SSKS

LSBb

TKK

S

LSBa

baTKLSB

ssS

aTKKLSB

ssS

Detailed Steps• Reset ramp testing signal generator• Detect first non-zero ADC output (lower-bound of

samples)• Measure all subsequent samples• Stop at the maximum ADC output (upper-bound of

samples)• DSP collects all valid measurements and start to

processing data• Divide measured samples into two equal-size parts• Accumulate measurements of each part to obtain two

sums• Calculate two syndromes from two sums• Calculate two estimated coefficients of the linear ramp

function• (Optional) Compare each measured data to estimated one

from ramp function


Simulation Results

DNL and INL Estimation results


Other considerations

• Minimal number of samples– More samples, less quantization noise, more

accurate estimation– Not all codes need to be sampled in order to

reduce testing time– At least 2N-2 samples are found necessary in

practice

• The same idea may be used with low-frequency sinusoidal testing signals instead of ramp signal– More overhead and complexities with

sinusoidal generator


Testing of DAC

• DSP as both TPG and ORA


DSP

DACunder-test

m-ADCAnalog System

d-DAC Polynomial evaluation

0

N

Diagnosis TPG

TPG

N

Test of DAC


BIST CONTROL

DACunder-test

1st-order 1-bit ΣΔ Modulator

LPFDigital Filter

Ramp code generator

Characteristics analysis

Pass/fail indicator

Offset,Gain,2nd and 3rd harmonic distortion

Coefficientsfor polynomial evaluation

14

ΣΔ ADC

Polynomial evaluation

Dithering DAC

Components• Digital circuitry (including DSP) as BIST control

unit– Test pattern generation (TPG) and output response

analysis (ORA) • Measuring ADC

– First-order 1-bit Sigma-Delta modulator– Digital low-pass filter– Measuring outputs of DAC-under-test

• Dither DAC (not used)– Low resolution DAC– Generating correcting signal for calibration– Calibrated DAC for test of ADC-under-test

• ADC Polynomial Fix (not used during testing)– Digital process to revise ADC output codes


Polynomial Fitting Algorithm• Introduced by Sunter et al.

in ITC’97 and A. Roy et al. in ITC’02

• Summary:– Divide DAC transfer

function into four sections

– Combine function outputs of each section (S0, S1, S2, S3)

– Calculate four coefficients (b0, b1, b2, b3) by easily-generated equations


33

2210 xbxbxbby

Third-order Polynomial

• Offset• Gain• And

Harmonic Distortion


343

232

3121

200

01233

01232

01231

01230

33

2210

3

128

163

443

41

33

Bn

b

Bn

b

BBn

b

BBn

b

SSSSB

SSSSB

SSSSB

SSSSB

xbxbxbby

Simulation ResultsINL of 14-bit DAC Results of fitting polynomial


Oversampling ratio for m-ADC

219510

8

3log1076.102.6

30

2.1476.11402.6

3210

OSR

OSRNSNRdB

Outline




Calibration of DAC


• The output of calibrated DAC can be considered as linear

DACunder-test

Polynomial evaluation

Dithering DAC

coefficients

DSP14

Dithering DAC • low-

resolution DAC

• Better linearity output with DEM

• Must be tested by measuring ADC before test of on-chip mixed-signal devices


3

α=1

17bits

Resolution of dithering-DAC (bits)

Overs

am

plin

g r

ati

o (

OS

R)

2

Polynomial Evaluation

• Either hardware or software implementation

• Hardware Implementation– Faster and DSP not occupied– High overhead due to huge block of

digital multiply circuit• Software Implementation

– DSP drives both on-chip DAC and dithering DAC with calculated value

– Performance penaltyWei Jiang General Final Exam 48

Simulation Results

d-DAC errors Calibration results


Verification of ADC/DAC


*OPTIONAL

Outline


• BIST Architecture for Mixed-Signal Devices– Overview of Proposed Architecture– Test of DAC/ADC

– Calibration of DAC• Sigma-Delta Modulation• Polynomial Fitting Algorithm• ConclusionWei Jiang General Final Exam 51

Measuring ADC

• First-order single-bit sigma-delta ADC• Diagnosis performed before mixed-

signal test• In-band quantization noise moved up

due to oversampling and noise shaping

• Higher-order multiple-bit Sigma-Delta ADC can also be used


Sigma-Delta Modulator

• First-order single-bit

• Diagram

• Transfer function


zEzzXzzY 11 1

Oversampling and Noise shaping


H(s)

InputX(s)

OutputY(s)

Quantizer

ErrorE(s)

)()(1

1)(

)(1

)()( sE

sHsX

sH

sHsY

* F. F. Dai and C. E. Stroud, “ΣΔ Modulation for Factional-N Synthesis ” Chapter 9, p. 307 in System-on-Chip Test Architectures: Nanometer Design for Testability, Morgan Kaufmann, 2008.

Ou

tpu

t

Frequency

fin fs/2

H(s)

sf6

2

Quantization noise

Ou

tpu

t

Quantization noise

fin fs/2

H(s)

sf6

2

Oversampling without feedback

Oversampling with noise shaping feedback

1+H(s)

1

Frequency


• Oversampling Ratio• Signal-to-noise-distortion Ratio

• Signal-to-noise Ratio

• First-order


d

s

f

fOSR

2

OSRNSNDR 2log376.102.6

32102

010

32

220

8

3log10

8

1log10

3

OSRn

SNR

OSRen rms


• Second-order

• Higher order


5410

54

220

8

5log10

5

OSRSNR

OSRen rms

12210

122

220

8

12log10

12

nn

nn

rms

OSRn

SNR

OSRn

en

Select Proper Order


First-order

Second-order

Third-order

17-bit ENOB104.1LSB

Oversampling ratio (OSR)

Multiple Bits

• N: NOB of quantizer

• n: order of ΣΔ modulator


12log66.1log

2

12

12log10log12376.102.6

122

2

3log10

1212

1281

log10

12

2

102

2

102

2122

10

1222

2

10

122

220

nOSR

nNN

nOSRnN

nOSR

OSRn

SNR

OSRn

en

n

effective

n

nnN

nn

N

nn

rms

Outline




Polynomial Fitting

• Different order of fitting polynomial can be used for various applications– Linear fitting– Second-order fitting– Third-order fitting– Higher order fitting

• Computation complexity and hardware overhead increase exponentially


22

1NO

NNO

Linear Fitting


b

na

ndkys

bn

an

dkys

kbay

n

k

n k

k

82

822

2

01

20

20

14

1

4

2

0

2

011

010

Sn

b

Sn

a

bn

ssS

anssS

Second-order Fitting


cn

bn

an

dkys

cn

an

dkys

cn

bn

an

dkys

kckbay

n

n k

n

n k

n

n k

k

324

13

93

3243

324

13

93

322

6

2

36

2

1

326

2

0

2

Second-order Fitting


cn

sssS

bn

ssS

ansssS

27

22

9

2826

3

0123

2

021

0120

23

12

0

2

272

98

1

Sn

c

Sn

b

Sn

a

Third-order Fitting


34

23

312

20

01233

01232

01231

01230

32

3

128

163

443

41

33

Sn

d

Sn

c

SSn

b

SSn

a

ssssS

ssssS

ssssS

ssssS

dxcxbxay

Comparison of different orders


Higher-Order Fitting

• Possibly better fitting result• Impractical for hardware

implementation due to huge overhead• Expressions on calculation of

coefficients can be derived in the same way

• Usually third-order polynomial fitting is sufficient for the most applications


Adaptive Polynomial Fitting

• Dynamically choose polynomial degree• Low-order polynomial

– Simple to design and implement– Less area and performance overhead– Large fitting error

• High-order polynomial– Better fitting results– More coefficients to store– Much more complicated polynomial

evaluation circuitry design and heavy area and performance overhead


Implementation

• Analog Signal Generator (ASG)– A few transistors; low overhead

• Measuring ADC (m-ADC)– First-order 1-bit Sigma-Delta ADC; low

overhead

• Dithering DAC (d-DAC)– Low resolution DAC; low overhead

• Polynomial Evaluation Unit (HW)– Multiply-accumulate Logic; huge overhead


Truncation Error


•12-bit is sufficient for a10-bit DAC (above); 16-bit for 12-bit DAC (below)

Truncation Error (LSB)

LinearSecond-

orderThird-order

Higher

4-bit 64.296 77.474 84.6201 88.622

8-bit 3.2427 5.0105 5.8187 6.2390

12-bit 0 0.28352 0.37217 0.40544

16-bit 0 0.010821 0.023578 0.025812


LinearSecond-

orderThird-order

Higher

4-bit 255.30 309.60 337.97 354.91

8-bit 15.251 20.358 23.170 25.054

12-bit 0 1.2515 1.4993 1.6491

16-bit 0 0.070815 0.094711 0.10523

Truncation Error


LinearSecond-

orderThird-order

Higher

4-bit 1023.3 1237.9 1351.3 1419.5

8-bit 63.252 81.181 92.521 100.141

12-bit 3.2405 5.1244 5.9794 6.5742

16-bit 0 0.31280 0.37720 0.42131

20-bit 0 0.017700 0.023781 0.026617

24-bit 0 0.00067559 0.0014819 0.0016703


* 16-bit is sufficient for calibration of a14-bit DAC; 17-bit could be better

Hardware Overhead


Overhead (Gates/DFF

s)Linear

Second-order

Third-order

Higher

4-bit 216 38 495 87 866 153 1329 235

8-bit 357 63 863 152 1556 275 2334 430

12-bit 520 92 1281 226 2322 410 3642 643

16-bit 658 116 1646 291 3009 531 4743 837

20-bit 820 145 2064 364 3775 666 7218 1274

24-bit 959 169 2432 429 4464 788 8580 1514

* Synthesized with TSMC018 library; approximately in count of NAND2/DFFX1

Testing Time

• Variables– N: resolution of on-chip ADC/DAC– T: sample/conversion time of ADC/DAC– M: OSR for Sigma-Delta modulator– N’: resolution of d-DAC

• Example– 14-bit ADC/DAC with 10ns conversion

time– Oversampling ratio of ΣΔ is 2000– 6-bit d-DAC for calibration


Testing Time

• Diagnosis– ASG and m-ADC: Td1

– d-DAC and m-ADC: Td2

• Test of ADC: Tad

• Test of DAC: Tda

• Verification of ADC/DAC: Tv

• Total testing time:– Assume T=10ns, M=2000,N=14, N’=6– Total time = 657ms


TT

TMT

TT

TMT

TMT

Nv

Nda

Nad

Nd

Nd

2

2

2

2

2'

2

1

MTMTT NNtotal '

212 1

Outline




General Mixed-Signal Test

• Variation-tolerant design• Digital controlled BIST• Digitalized TPG/ORA• Self-testable measuring components• Characterization of device-under-test

by DSP• Faulty circuitry determined by

characterized parameters• Coefficients of output fix/correction

signals calculated by DSPWei Jiang General Final Exam 75

Conclusion

• A post-fabrication built-in test and calibration approach for mixed-signal devices is proposed

• This approach relies on digital circuitry and DSP for TPG/ORA and BIST control

• Digital circuitry is testable by conventional digital testing approaches and therefore guarantee the testability of analog circuitry

• On-chip ADC/DAC are tested separately and verified

• Calibration on mixed-signal devices will significantly reduce defects, improve die yield and lower manufacturing cost


Publications• W. Jiang and V. D. Agrawal, “Built-In Test and Calibration of

DAC/ADC Using A Low-Resolution Dithering DAC,” NATW’08, pp. 61-68.

• W. Jiang and V. D. Agrawal, “Built-in Self-Calibration of On-Chip DAC and ADC,” ITC’08, paper 32.2.

• W. Jiang and V. D. Agrawal, “Built-in Adaptive Test and Calibration of DAC,” NATW’09, pp. 3-8.

• W. Jiang and V. D. Agrawal, “Designing Variation-Tolerance in Mixed-Signal Components of a System-on-Chip,” ISCAS’09, pp. 126-129.

• W. Jiang and V.D. Agrawal, “A DSP-Based Ramp Test for On-Chip High-Resolution ADC,” ICIT’11

References• M. L. Bushnell and V. D. Agrawal, “Essentials of Testing for

Digital, Memory, & Mixed-Signal VLSI Circuits,” Boston: Springer, 2000

• F. F. Dai and C. E. Stroud, “Analog and Mixed-Signal Test Architecture,” Morgan kaufmann, 2008.

• S. Sunter and N. Nagi, “A Simplified Polynomial Fitting Algorithm for DAC and ADC BIST,” ITC’97, pp.389-395

• A. Roy, S. Sunter et al., “High Accuracy Stimulus Generation for A/D Converter BIST,” ITC’02, pp.1031-1039


THANK YOU


Documents

Built-In Self-Test and Calibration of Mixed-Signal Devices