BTU TPC Electronics WBS 1.1 - indico.bnl.gov · 6/23 to 6/24/ 2016 Annual BTU TCSM Review 1 BTU TPC Electronics WBS 1.1.2 C. L. Britton K. F. Read D. Simpson Oak Ridge National Laboratory

6/23to6/24/2016 AnnualBTUTCSMReview 1

BTUTPCElectronicsWBS1.1.2

C.L.BrittonK.F.ReadD.SimpsonOakRidgeNationalLaboratoryandUniversityofTennessee

Outlineofthetalk

• SAMPA– MPW1tests– MPW2plan– MPW2status

• FECDesign– Finalarchitecture– Prototypestages– Rev0status

26/23to6/24/2016 AnnualBTUTCSMReview

SAMPA


SAMPABlockDiagram


5

SAMPAReadoutASIC• Designedat

UniversityofSaoPaulo,Brazil

• Processis0.13umTSMC

• ThisisacommonASICtobeusedwithinALICEbybothTPCandMCH.

• Chiphas311pins.

• Finalpackagewillbea372-BallGridArray(BGA)

(80nspeakingremoved)


SAMPAMPW1Tests


ChipsfabricatedontheMPW1


8

MPW1Linearity


MPW1Linearity


MPW1Noise


Input Capacitance [pF]0 20 40 60 80 100 120

ENC

[e] -

fixe

d G

ain

0

500

1000

1500

2000

2500

SimulationBR3CH2 - Neg - 1.25VBR3CH3 - Neg - 1.25VBR3CH5 - Neg - 1.25VBR3CH5 - Neg - 1.25VDub_CH1 - Neg - 1.25VDub_CH2 - Neg - 1.25VDub_CH3 - Neg - 1.25VDub_CH4 - Neg - 1.25VDub_CH5 - Neg - 1.25VBer_CH1 - Neg - 1.25VBer_CH2 - Neg - 1.25VBer_CH3 - Neg - 1.25VBer_CH4 - Neg - 1.25VBer_CH5 - Neg - 1.25VOrsay_CH2 Neg - _ _Orsay_CH3 Neg - _ _Orsay_CH4 Neg - _ _Orsay_CH5 Neg - _ _

























SimulationBR3CH2 - Neg - 1.25VBR3CH3 - Neg - 1.25VBR3CH5 - Neg - 1.25VBR3CH5 - Neg - 1.25VDub_CH1 - Neg - 1.25VDub_CH2 - Neg - 1.25VDub_CH3 - Neg - 1.25VDub_CH4 - Neg - 1.25VDub_CH5 - Neg - 1.25VBer_CH1 - Neg - 1.25VBer_CH2 - Neg - 1.25VBer_CH3 - Neg - 1.25VBer_CH4 - Neg - 1.25VBer_CH5 - Neg - 1.25VOrsay_CH2 Neg - _ _Orsay_CH3 Neg - _ _Orsay_CH4 Neg - _ _Orsay_CH5 Neg - _ _18.5pF

20mV/fC (Neg)

TPCShapingtimemeasurement


12

SAMPAMPW2


SAMPAMPW2consistsofseveralASICs• Includesthefull32channelASIC• Testchip01– Fullshaper– SLVSTX/RX– Bias

• Testchip02– 32channelCSA/Shaper/buffer

• Testchip03– ADC

13

Diesize- 9533.6umx8943.6umPincount– 311,Ballcount- 372


Testchip01


Testchip02


Testchip03


SAMPASimulation• Afullsuiteof simulationsweredone invariousdomains• Duetocomputing limitations, theentirechipwasnotsimulatedasasingleentity• TheMPW2analogsectionhadextensiveoversightandrigorwithreviewand

monitoring byALICE,CERN,andORNLreviewers.– Appropriateduediligenceexercisedfordesign.– Extensive,superiorsimulationswereperformed.– Multipletestbenches usedtocheckdigitalcontrolfunctionality.


Front-endplusADCsimulations(cont.)(Neg pol.,20mV/fC,160ns)


Top-leveldigitaloutput.Fitincluded.

Mixed-signalSimulation.

Front-endplusADCsimulations(Neg pol.,30mV/fC,160ns)


Top-leveldigitaloutput.Fitincluded.

Mixed-signalSimulation.

NoiseSimulations


Thepreampnoisecanbeoptimizedatasingledetectorcapacitance

21

Iin

M1

M2

Cd

ToCascode

Improvesnoiseduetobothdrain-biastransistorandpower-supply


NoiseSimulation(cont.)


PSRRSimulations

23

TPCFECfilteringsimulation


Linearitysimulations(postlayout)


Crosstalksimulations

25

• Signalduetocrosstalkinadjacentchannellessthan~0.25%

• Nocrosstalkappearsinsecondchannels


FECDesign


TPCFECFinalReadoutArchitecture


TheexistingTPCboardisoursizetemplate


TheBeast


Theinterconnectblockdiagramisrelativelystraightforward

• Allclocks,resets,sync,controlcomefromGBTx0

• GBTx1isonlyareceiverofdata


Boardlayoutisproceeding• SAMPAlayoutand

connectorplacementhasbeentheprimaryfocus

• Thehigh-speedlineroutingispresentlyunderway

• An8-layersystemisourcurrentplan

• Mountingholesandcoolingtubeissameascurrentsystem

• Depthofboardwillincreaseby~0.6”

• Samepowerconnectorascurrent system

• Rev0willhavedetachable inputcables


PrototypingStages• Rev0– Theinitialdesign– Schematiccapture

• DoneinCadenceAllegro/Orcad 16.6• Designwasreviewedpriortolayout

– Layout• DannySimpson,OutsidelayoutengineerusedbyORNL.• UsingCadenceAllegrolayout• Layoutwillbereviewedbythecollaborationandrevised.• Rev.0rigid-onlyPCBhasthesebenefits:

– domesticonly(nocustoms)– fastestpossible turn-around– lowestcostfabforprototyping


Technicalapproach/challenges

• Rev0(cont.)– Layout(cont.)

• Wehadplannedtoutilizeflexcable forthedetectorinputsbutthecostandturnaroundwastoohigh

• WeareusingdetachablecableswithERNIconnectorsforthedetectorconnection

– Fabricate• Wewillfabricateupto20oftheboards• 15willbeusedfordetectortest• Thesewillbedistributedtocollaboratorsfortesting

• Rev1willrepeatthecycleaftertestresultshavebeenreceivedandreviewed

• Rev1awillbethefinalpre-productiondesign


Technicalapproach

• CERNrequiresHalogen-Freematerialfortheboards

• Ourregularassemblyhousecansupplythis


ProductionPlan&QA/QC(consistentwithtestingrequirementsandacceptance)

• AcceptancetestsoutlinedinALICEBarrelTrackingUpgradeProjectManagementPlan(DocumentBTU.1.v4)

• TeststandsusingCRUwillbedeveloped• Vendorevaluationhasstarted• Fiverunswillbeusedtoaccomplishtheproduction


36

• BTU.9HazardAnalysisDocument:• Describespotentialhazards

andmitigationforTPCFEC• Sealedlowvoltagepower

supplies• Soldering,leadsolder• Workershavetakenrequired

safetytraining (electricalsafety,chemicalsafety,PPE).

• Example:FEClabposting• BTU.8ES&HManagementPlan

• FollowsORNLES&Hpolicies• Periodicon-sitesafety

reviews

HazardAnalysis&Mitigation


NOTICENOTICENOTICENOTICEAUTHORIZED PERSONNEL ONLYAUTHORIZED PERSONNEL ONLYAUTHORIZED PERSONNEL ONLYAUTHORIZED PERSONNEL ONLY

See Access Requirements for DetailsSee Access Requirements for DetailsSee Access Requirements for DetailsSee Access Requirements for Details

Space Function BLDG/RMLaboratory 1, Dry 6000/211

HAZARD WARNINGS

Access RequirementsUnescorted access to Building 6000 is granted upon completion offacility specific access training.

Obey Radiological Postings.

PPE required for work with chemicals, power tools, soldering, orperforming work on or near electrical work.

Research Support Group Leader Charlie Havener, 574-4704, Bldg 6000Room 250A and Division Director David Dean 576-5229

CONTACTS NAME PHONE OFFICESpace ManagerSpace Group LeaderComplex Facility ManagerFacility Operations Manager

Kenneth Read Jr 574-5347 6000 Room 219Thomas Cormier 574-9998 6000 Room 213Richard Griffey 574-8907 5700 Room J103B Tatum 574-4759 6000 Room 203

LAST REVISION: 9/2/2015 (1)

Summary

• MPW1testingrevealedmanyissues• Test-campaigndeficienciesforMPW1havebeenwelladdressed

• MPW2appearstohavebeenwellsimulated(butnotcompletechip)

• TheRev0FEChaspresentedseveralchallenges,primarilycost


Backupslides


6/23to6/24/2016 39

FECTestStation

pulsegenerator

• TestingcriteriasummarizedinAppendixA.2ofBTU.1.v8.• Canpulsedifferentselectedpatternsofinputchannels.• WillinitiallyuseC-RORCFPGAboarduntilCRUbecomesavailableinlater2016.

• FECteststationdevelopedforAugust2016willbeimprovedandusedformassFECtestinginearly2019.

PCwithCRU(initiallyC-RORC)optical

fibers

FECchannelpatternboard


6/23to6/24/2016 40

FECTestingMatrix


Pulser SAMPA GTBx C-RORC

Link Check - RX/TX PG

Pattern from Ped.Mem (DSP) - TRIGGERED

Alignment Check by Peak-Matching - CONTINOUS

PC

Pulse Analysis - CONTINUOUS with Selection-Window (Pre-/Post-Samples)

Pattern from Ped.Mem (DSP) - TRIGGERED

Alignment Check by Peak-Matching - CONTINOUS

SlowControl Check (SCA)Check Fibre and GBTx

connectivity

Check SAMPA and GBTxconnectivity

Check Raw ADCAlignment

(Reset/Sync)

Full Validation ofCSA & Shaper

& Noise

Purpose

Documents

BTU TPC Electronics WBS 1.1 - indico.bnl.gov · 6/23 to 6/24/ 2016 Annual BTU TCSM Review 1 BTU TPC Electronics WBS 1.1.2 C. L. Britton K. F. Read D. Simpson Oak Ridge National Laboratory