BiCMOS

Combines Bipolar and CMOS transistors in a single integrated circuit. By retaining benefits of bipolar and CMOS, BiCMOS is able to achieve VLSI circuits with speed-power-density performance. The superiority of the BiCMOS gate lies in the high current drive capability of the bipolar output transistors, the zero static power dissipation, and the high input impedance provided by the MOSFET configuration.

(STUDY fabrication of BICMOS STRUCTURE FROM TEXT -BOTKAR)

COMPARISON B/W CMOS AND BIPOLAR TECHNOLOGIES

CMOS BIPOLARLow static power dissipation High static power dissipationHigh i/p impedance Low i/p impedanceHigh noise margin Low noise margin(low voltage swing logicHigh packing density Low packing densityHigh delay sensitivity to load Low delay sensitivity to loadLow output drive current High output drive currentLow gm(transconductance) Large gm(transconductance)Bidirectional capability unidirectional Nearly ideal switching device Non ideal switching deviceAdvantages of BiCMOS

BiCMOS devices offer high load current sinking and sourcing is required. The high current gain of the NPN transistor greatly improves the output drive capability of a conventional CMOS device.

Improved speed over purely-CMOS technology Lower power dissipation than purely-bipolar technology (simplifying packaging and board

requirements) Latchup immunity Flexible I/Os (i.e., TTL, CMOS or ECL compatible) BiCMOS technology is well suited for

I/O intensive applications. ECL, TTL and CMOS input and output levels can easily be generated

DISADVANTAGE

Costlier due to added Processing Complexity.Additional masking steps than in CMOS to fabricate bipolar structure along with CMOS

COMPARISON B/W CMOS BIPOLAR AND BiCMOS TECHNOLOGIES

CMOS BIPOLAR BiCMOSLow static power dissipation High static power dissipation Low static power dissipation

than BipolarLow speed(Slow switching) High speed Faster than CMOSLow o/p current drive High o/p current drive High o/p current driveHigh i/p impedance Low i/p impedance High i/p impedanceHigh noise margin(high o/p voltage swing)

Low noise margin High noise margin compared to bipolar

Fabrication process simpler compared to BiCMOS

Simpler fabrication Fabrication process is complex

BiCMOS Logic gates

Designed with MOS circuits to implement the logic and bipolar transistors to drive output loads.

Charactreristics of BiCMOS logic gates(write for inverter,nand and nor)

The o/p logic levels will be god nd will be close to rail voltages High i/p impedance Low o/p impedance High current drive capability,occupies relatives smaller area High noise margin

BiCMOS invereter

BiCMOS inverter circuit consists of two bipolartransistors T1 and T2 with one nMOS T3 and one pMOS transistor T4,both being enhancemnet mode devices.

OPERATION OF CIRCUIT

With Vin=0 volts(GND),T3 is off so that T1 will be non conductiong.but T4 is on and supplies current to base of T2 which will conduct and act as current source to charge load CL towards +5 VOLTS(VDD). The O/P of inverter rise +5 volts less base to emitter voltage VBEof T2.

With Vin=+5 volts(VDD),T4 is off so that T2 will be non conductiong.but T3 is on and supplies current to base of T1 which will conduct and act as current sink to disccharge load CL towards 0 VOLTS(GND). The O/P of inverter will fall to 0 volts plus saturation voltage VCEsat from collector to emitter of T1.

T1 AND T2 will present low impedances when turned on into saturation and load CL will be charged or discharged rapidly.

The o/p logic levels will be god nd will be close to rail voltages

Inverter has High i/p impedance

Inverter has Low o/p impedance

Inverter has High current drive capability,occupies relatives smaller area

Inverter has High noise margin

LIMITATIONS OF BASIC INVERETER CONFIGURATION

Owing to presence of DC path from VDD to GND through T3 and T1 ,this is not a ood arrangement to implement since there will be a significant static current flow whenever Vin=logic1.

Thre is no diharge path for current from base of either bipolar transistor when it is being turned off.This will slow down action of circuit.

An improved BiCMOS inverter WITH NO STATIC CURRENT FLOW

DC path through T3 and T1 is eliminated but o/p voltage swing is now reduced since output cannot fall below base to emitter voltage of T1.(this o/p volt is in effect base voltage of T1 in this arrangement.T1 wil turn off if o/p volt fall below VBE OF T1.)

Consider the simple BiCMOS inverter circuit shown in figure which consists of two MOS transistors and two' npn-type bipolar transistors which drive a large output capacitance Cload. The operation concept of this circuit can be very briefly summarized as follows.

The complementary pMOS and nMOS transistors MP and MN supply base currents to the bipolar transistors and thus act as "trigger" devices for the bipolar output stage. The bipolar transistor Q 1 can effectively pull up the output voltage in the presence of a large output capacitance, whereas Q2 pulls down the output voltage, similar to the well-known totem pole configuration. Depending on the logic level of the input voltage, either MN or MP can be turned on in steady state, therefore assuring a fully complementary pushpull operation mode for the two bipolar transistors. In this very simplistic configuration, two resistors are used to remove the base charge of the bipolar transistors when they are in cut-off mode. In this circuit resistors provide better improved o/p swing of voltage .

To reduce the turn-off times of the bipolar transistors during switching, two minimum-size nMOS transistors (MB 1 and MB2) are usually added to provide the necessary base discharge path, instead of the two resistors(resistors are space consuming). The resulting six-transistor inverter circuit, shown in Fig.,below is the most widely used conventional BiCMOS inverter configuration.

Conventional BiCMOS inverter.

BiCMOS NOR2

Figure shows the circuit diagram of a BiCMOS NOR2 gate. Here, the base of the bipolar pull-up transistor Q1 is being driven by two series-connected Pmos transistors. Therefore, the pull-up device can be turned on only if both of the inputs are logic-low. The base of the bipolar pull-down transistor Q2 is driven by two parallel-connected nMOS transistors. Therefore, the pull-down device can be turned on if either one or both of the inputs are logic-high. Also, the base charge of the pull-up device is removed by two minimum-size nMOS transistors connected in parallel between the base node and the ground. Notice that only one nMOS transistor, MB2, is being used for removing the base charge of Q2, when both inputs are logic-low.

BiCMOS NAND2

Figure shows the circuit diagram of a BiCMOS NAND2 gate. In this case, the base of the bipolar pull-up transistor Q I is being driven by two parallel-connected Pmos transistors. Hence, the pull-up device is turned on when either one or both of the inputs are logic-low. The bipolar pull-down transistor Q2, on the other hand, is driven by two series-connected nMOS transistors between the output node and the base. Therefore, the pull-down device can be turned on only if both of the inputs are logic-high. For the removal of the base charges of Q1 during turn-off, two series-connected nMOS transistors are used, whereas only one nMOS transistor is utilized for removing the base charge of Q2.