Ballistic Nano Transistors

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 9, SEPTEMBER 2003 1853

Theory of Ballistic NanotransistorsAnisur Rahman, Jing Guo, Supriyo Datta, Fellow, IEEE, and Mark S. Lundstrom, Fellow, IEEE

Invited Paper

Abstract—Numerical simulations are used to guide the devel-opment of a simple analytical theory for ballistic field-effect tran-sistors. When two-dimensional (2-D) electrostatic effects are small(and when the insulator capacitance is much less than the semi-conductor (quantum) capacitance), the model reduces to Natori’stheory of the ballistic MOSFET. The model also treats 2-D elec-trostatics and the quantum capacitance limit where the semicon-ductor quantum capacitance is much less than the insulator ca-pacitance. This new model provides insights into the performanceof MOSFETs near the scaling limit and a unified framework forassessing and comparing a variety of novel transistors.

Index Terms—Ballistic MOSFET, device simulation, double-gate MOSFETs, quantum effects, semiconductor device modeling,ultra-thin body.

I. INTRODUCTION

M OSFET channel lengths continue to shrink rapidlytoward the sub-10 nm dimensions called for by the

International Technology Roadmap for Semiconductors [1],[2]. Coupled with the use of high-mobility channel materials[3]–[9], nanoscale channel lengths open up the possibilityof near-ballistic MOSFET operation. As MOSFET scalingcontinues, molecular transistors that could replace them arealso being explored. Carbon nanotube transistors, for example,are especially interesting because their one-dimensional band-structure suppresses backscattering and makes near-ballisticoperation a possibility [10], [11]. Per unit width on-currentssignificantly higher than those of MOSFETs have already beenreported [10 ], [12]. For these reasons, it is important to under-stand ballistic operation—both in conventional MOSFETs andin unconventional transistors. Our objectives in this paper areto present a simple analytical theory for ballistic transistors andto explore its application to MOSFETS and to unconventionalfield-effect transistors.

The operation of MOSFETs in the ballistic regime hasrecently been explored by simple, analytical models [13]–[16]as well as by detailed numerical simulations [17]–[22]. InSection II, we review our understanding of the device physics

Manuscript received December 2, 2002. This work was supported by theSemiconductor Research Corporation, the National Science Foundation, aMicroelectronics Advanced Research Corporation Focus Center for Materials,Structures, and Devices, and the Army Research Office under a DefenseUniversity Research Initiative in Nanotechnology. The review of this paper wasarranged by Editor H. Sakaki.

The authors are with the School of Electrical and Computer Engi-neering, Purdue University, West Lafayette, IN 47907 USA (e-mail:[email protected]).

Digital Object Identifier 10.1109/TED.2003.815366

Fig. 1. Structure of the model device: a double-gate MOSFET. A bodythickness of 1.5 nm and an oxide thickness of 1.5 nm were assumed. Both thesource and drain regions were doped at 10/cm . The gate workfunction wasset to 4.25 eV, which produced an off-current of 1.6 nA/�m.

of ballistic MOSFETs as developed in previous publications[23]–[25]. In Section III, we present a simple, analytical model,and in Section IV, we show that it agrees with two-dimensional(2-D) numerical simulations of ballistic MOSFETs. In Sec-tion V, we apply the new model to ideal carbon nanotube FETsand discuss the interesting effects that occur in the quantumcapacitance limit [26]. Finally, in Section VI, we discusswhy the model developed here does not describe devices likeSchottky barrier FETs before concluding in Section VII.

II. DEVICE PHYSICS OFBALLISTIC MOSFETS

Numerical simulations provide detailed information on theoperation of nanoscale devices. Two transport models haveproven to be especially useful in our work. The first is a nu-merical solution of the ballistic Boltzmann equation [19], [25],and the second is the nonequilibrium Greens function (NEGF)formalism for quantum transport [27], [28]. Fig. 1 showsa model 10-nm MOSFET, and Fig. 2 shows the computedballistic distribution function within the device under on-stateconditions [25]. The results show that two distinct carrierpopulations exist: one due to source injection and another dueto drain injection (scattering would mix these two populations).Deep within the channel, the drain-injected population retainsa near-equilibrium shape, but the source-injected populationis strongly distorted. Fig. 3 is an NEGF simulation of theenergy-resolved electron density under on-state conditions.Although quantum interference effects are seen as well astunneling of carriers beneath the source-channel barrier,NEGF simulations of the terminal – characteristics ofwell-designed MOSFETs agree rather well with semi-classical

0018-9383/03$17.00 © 2003 IEEE

1854 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 9, SEPTEMBER 2003

Fig. 2. Ballistic distribution function within the model device under on-stateconditions as computed by solving the ballistic BTE. (From [25].)

(a)

(b)

Fig. 3. Energy-resolved (a) density-of-states versus position and (b) electrondensity versus positions with the model device as computed using the ballisticNEGF formalism.

simulations—even at the 10-nm scale (when the strong effectsof quantum confinement are included in both simulations) [18],

(a)

(b)

Fig. 4. Computed energy band diagrams under (a) low drain bias and (b) highdrain bias. The parameter is the gate voltage.

[19]. Both the quantum and classical simulations show rich,complex phenomena within the device, but it turns out that asimple description of the current versus voltage characteristicsis possible [24].

Fig. 4 shows the computed self-consistent potentials withinthe model nanoscale MOSFET under low and high drain biaswith gate voltage as a parameter. (What is plotted is actually thebottom of the first subband versus position.) At low gate volt-ages, the energy barrier between the source and drain is high,and the device is off. A high drain bias lowers the energy inthe drain, and when a high gate voltage lowers the potential en-ergy barrier, electrons flow from source to drain. This pictureof the MOSFET is essentially that of the bipolar transistor [29];transistor action occurs by modulating the height of an energybarrier. It is more common to think of MOSFETs in terms ofthe gate modulating the charge in the channel, but the chargein the channel is controlled by the height of the barrier. MOS-FETs and bipolar transistors operate by similar principles (bothbelow and above threshold); in the bipolar transistor, the heightof the energy barrier is controlled directly by the base-emittervoltage, whereas in the MOSFET, it is controlled indirectly bythe voltage on the gate [29]. As will be discussed in Section VI,not all transistors operate by this charge (or barrier height) mod-ulation principle.

Current is the product of charge and velocity, which we plotseparately in Fig. 5. In this figure, the gate voltage is high, and

RAHMAN et al.: THEORY OF BALLISTIC NANOTRANSISTORS 1855

(a)

(b)

Fig. 5. Computed behavior at the top of the source to channel barrier. (a)Electron chargeQ (0) at the top of the barrier versusV . (b) Average electronvelocity at the top of the barrier versusV .

we plot the two quantities as a function of . Fig. 5(a) showsthat the charge at the top of the barrier is nearly independentof for a well-designed MOSFET, and for operation abovethreshold, it is given by MOS electrostatics as

(1)

We will show in a later section that the initial dip in (0)and the subsequent rise can also be explained. Fig. 5(b) showsthat the average electron velocity at the top of the barrier in-creases with and then saturates. The saturated velocity atthe top of the barrier is simply the velocity of the thermal equi-librium hemi-Fermi–Dirac distribution shown in Fig. 2. (Notethat above threshold, the electron gas is degenerate, and themagnitude of this injection velocity depends on the gate voltage[13], [15].) It is interesting to note that velocity saturation oc-curs in a ballistic MOSFET, but it occurs at the top of the barrierwhere the field is zero rather than at the drain end where the fieldis high [24]

Because the top of the barrier has special significance, it is thestarting point for our analytical model. For a ballistic transistor,the states at the top of the barrier are filled from either the sourceor the drain. For a quantum transport model, the local density ofstates fillable by the source and drain can be evaluated directlyfrom the spectral function [27], [28]. In a semiclassical model,

Fig. 6. Illustration of how the k-states at the top of the barrier are filled by thetwo Fermi levels.

the local density of states is determined by the relationfor the semiconductor shifted by the self-consistent potential atthe top of the barrier. Fig. 6 shows how the states at the top ofthe barrier are filled for a simple bandstructure. The positivevelocity states are populated according to the Fermi level of thesource and the negative velocity states by the Fermi level ofthe drain. Our key task in developing an analytical model willbe to devise a simple approach to determine the self-consistentpotential at the top of the barrier.

Finally, we mention one subtle point. A careful examinationof Fig. 4(b) indicates that the conduction band in the sourceregion actually floats down by about 10 mV as the gate voltageincreases. This unfamiliar behavior is a consequence of trans-port at the ballistic limit. The source Fermi level is fixed at 0 eVand represents the Fermi level of the equilibrium source reser-voir/contact. Under low gate bias, most of the positive velocityelectrons injected from the contact reflect from the energy bar-rier so that both positive and negative velocity states in the sourceextension are filled. When the gate voltage is high, however,the barrier decreases, and fewer of the injected electrons reflectfrom the barrier so that it is mainly positive-velocity states in thesource that are occupied. To achieve space-charge neutrality inthe highly doped source extension, the conduction band mustfloat down so that more electrons are injected from the sourcecontact. When strong scattering is present inside the sourceextension, electrons occupy both positive and negative velocitystates, and this effect is absent. For a more complete discussionof boundary conditions for ballistic MOSFETs, see [30].

In the following section, we introduce a simple, analyticalmodel, and in Section IV, we show that it accurately describesthe physics of ballistic nanoscale MOSFETs.

III. M ODEL

A simple 2-D model for the ballistic MOSFET is shown inFig. 7. It consists of three capacitors, which represent the effectof the three terminals on the potential at the top of the barrier.As also indicated by the shaded region in Fig. 7, mobile chargecan be placed at the top of the barrier. The mobile charge is de-termined by the local density of states at the top of the barrier,the location of the source and drain Fermi levels and ,and by the self-consistent potential at the top of the barrier.


Fig. 7. Two-dimensional circuit model for ballistic transistors. The potential atthe top of the barrier,U , is controlled by the gate, drain, and source potentialsthrough the three capacitors shown. The mobile charge at the top of the barrieris determined byU and by the location of the two Fermi levels. The nonlinearsemiconductor (or quantum) capacitance is not shown explicitly but is implicitin the treatment of band filling.

Because there is a relation between the local potential and thecharge, this effect can be described by a nonlinear quantum ca-pacitance [26]. In equilibrium

(2)

which, since is sharply peaked about the Fermi en-ergy, is times the density of states near the Fermi energy.Solomonet al.have pointed out [31] that Natoris analytical bal-listic model [13] does not include this nongeometric, quantum(or degeneracy) capacitance. Neglecting the quantum capaci-tance is justified for thick gate insulators (i.e., when );however, it fails to describe gate electrostatics when the insu-lator capacitance is large compared with the quantum capaci-tance (i.e., when ( ), which occurs when the electricalthickness is small or when the quantum capacitance is small, asin a one-dimensional (1-D) conductor. Our model does not treatthe quantum capacitance explicitly; however, it is included natu-rally through the treatment of self-consistent gate electrostatics.

When the terminal biases are zero, the equilibrium electrondensity at the top of the barrier is

(3)

where is the local density of states at the top of the barrier,and is the equilibrium Fermi function. The function

is nonzero for positive values of its argument only, whichrepresents the minimum of the density of states and is specifiedas in equilibrium. When a bias is applied to the gate anddrain terminals (the source terminal is always grounded in thiswork), two things happen: i) The self-consistent potential at thetop of the barrier becomes , and ii) the states at the top ofthe barrier are now populated by two different Fermi levels. Thepositive velocity states are filled by the source, according to

(4a)

and the negative velocity states are filled by the drain accordingto

(4b)

where , and . A change ofvariables can be used to re-express these equations as

(5a)

(5b)

where

(6a)

and

(6b)

Given an arbitrary density of states and the location ofthe source and drain Fermi levels, we can evaluate the electrondensity at the top of the barrier if the self-con-sistent potential is known.

Finding the self-consistent potential involves solving the two-dimensional Poisson equation as represented by the three capac-itors in Fig. 7 with the bias induced charge

at their common terminal. We obtain the solution by super-position. First, ignoring the presence of the mobile charge in thechannel, we calculate the Laplace potential at the top of the bar-rier due to terminal biases, which is

(7a)

In this equation, the threes describe how the gate, drain, andsource control the Laplace solution and are given by

(7b)

where is the parallel combination of the three capacitors inFig. 7.

For a so-called, well-tempered MOSFET, the gate controlsthe potential, and and . The second partof the solution consists of grounding the three terminals andcomputing the potential due to the mobile charge, at the top ofthe barrier , from

(7c)

Physically, a positive bias applied to the drain and gate terminalspushes down the potential energy at the top of the barrier as de-scribed by , but because of the charge, the potential floats up,as described by . The complete solution is obtain by addingthe two contributions to obtain

(8a)where

(8b)

is the charging energy.


Equations (5) and (8a) represent two, coupled nonlinear equa-tions for the two unknowns and . These equations can besolved iteratively to find the carrier density and self-consistentpotential at the top of the barrier. Finally, the drain current isevaluated from

(9)

where is the “current-density-of-states” defined in the Ap-pendix.

In summary, the procedure for computing con-sists of the following steps.

i) Specify the semiconductor carrier and current-densi-ties-of-states and either analytically or bya numerical table.

ii) Specify , , , and .iii) Iteratively solve (5) and (8a) for and .iv) Evaluate the current from (9) for the assumed and

.

We have defined the model in terms of two densi-ties-of-states—one for the carrier density and onefor the current density —which can be determineddirectly from the semiconductor bandstructure. In general, theintegrals in (5) and (9) must be done numerically, but for simplebandstructures, they can be done analytically. In the Appendix,we evaluate these expression for 2-D carriers in a simple bandand discuss how to use more general bandstructures.

IV. A PPLICATION TO BALLISTIC MOSFETS

To illustrate the use of the model, we apply it to the doublegate MOSFET presented in Fig. 1 and compare the results to 2-Dnumerical simulations with nanoMOS 2.0 [22]. Although theexpressions for thes given in (7b) are exact, they are difficultto evaluate in practice because they depend on the 2-D structureof the device. We will, therefore, treat them as fitting parametersand present a step-by-step procedure for determining the threeparameters , , and . The results show that this simple,three-parameter model does a good job of fitting the simulated– characteristics over the full range of operation.

A. Parameters for the Analytical Model

The first step is to set the Fermi level for thecorrect threshold voltage, which is equivalent to setting the cor-rect gate work function. Alternatively, setting the Fermi level isequivalent to setting the correct equilibrium carrier density at thetop of the barrier as given by (3). For a well-designed MOSFETat low gate and drain bias, , , and are all small so

, and (3) for depends on a single parameter .In practice, we adjust the Fermi level in the analytical model sothat the current matches that of the simulator for and

mV.Next, after setting , we adjust the gate control param-

eter until the analytical model gives the same low sub-threshold swing as does the simulation. We do this for

(a)

(b)

Fig. 8. Comparison of the analytical model to numerical simulations for theballistic MOSFET of Fig. 1. (a) Transfer characteristics under both low and highdrain bias. (b) Output characteristics. In both cases, the solid lines are from theanalytical modes and the points are from nanoMOS simulations.

and for mV. The induced charge at the top of the bar-rier is very small so that the gate controls the position ofthe top of the barrier through . For complete gate con-trol ( ), the subthreshold swing is ideal, i.e.,mV/dec at room temperature. For our model device, we obtained

.Finally, having specified and , the drain control

parameter was obtained by horizontal shift of theversus characteristics in the subthreshold regime [i.e., bymatching the drain-induced barrier lowering (DIBL) of thesimple model to the detailed numerical model]. This parameterdescribes the additional change of the potential at the top of thebarrier due to the drain bias. For our model device, we found

.Fig. 8(a) and (b) compare the– characteristics from the

analytical to those obtained by numerical simulation. Fromthe versus plot of Fig. 8(a), we see that thesubthreshold characteristics match very well both for low andhigh . From the linear plot in the same figure, we also seethat at low and high , the characteristics match verywell. However, when both and are high, the matchis poor, and the analytical model underestimates . Thismismatch is also clear in the output characteristics presentedin Fig. 8(b), where we can see that for above threshold, the


Fig. 9. Comparison of the analytical model to numerical simulations for theballistic MOSFET of Fig. 1. In this case, the floating source potential wastreated. In addition to good agreement at low gate and drain biases and as lowgate and high drain biases, this plot shows that the agreement at high gate anddrain biases is also good.

drain current from the analytical model saturates at a lowervalue than numerical simulation. The reason for this mismatchunder high and and a way to treat it are discussed next.

B. Treatment of the Floating Source Potential

The discrepancy between the analytical and numericalmodels under high gate and drain biases is related to thefloating source potential, which was discussed briefly in Sec-tion II. This phenomenon, which is important only in ballisticdevices, is correctly implemented in the numerical simulatorbut has yet to be considered in our analytical model.

As discussed in Section II (and, at greater length, in [30]),for ballistic transport, a floating source potential is necessary tomaintain charge neutrality in the highly doped source and thedrain region under high bias conditions. As the gate voltage in-creases, fewer electrons are reflected from the barrier; the sourcepotential must drop, so that enough additional electrons are in-jected to restore space-charge neutrality in the source. When thesource potential decreases, so does at the top of the barrier.The result is that this floating source effect increases the carrierdensity at the top of the barrier, which explains the discrepancyobserved in Fig. 8 under high gate and drain biases.

With regard to the simulation procedure, the floating sourcepotential means that the source Fermi level cannotbe fixed at the beginning to produce a given since it is bothgate and drain bias dependent. As discussed in the Appendix,one can readily extend the iterative procedure so that the Fermilevel is iteratively adjusted to maintain space charge neutralityin the source under all bias conditions. Fig. 9 compares the

plots from the ballistic numerical simulation to the an-alytical model with the floating source treated, as discussed inthe Appendix. Fig. 9 shows that when the floating source effectis included, the analytical model reproduces the full, numericalsimulation quite well. The agreement is very good under high

and (where ignoring the floating source potential pro-duced serious errors) but not quite as good under highandlow , where the model without floating source correctionworked better.

(a)

(b)

Fig. 10. Behavior at the top of the source to channel barrier as obtained fromthe analytical model. (a) Electron chargeQ (0) at the top of the barrier versusV . (b) Average electron velocity at the top of the barrier versusV

C. Charge and Velocity at the Top of the Barrier

Finally, we examine the charge density

(10a)

and the carrier velocity

(10b)

at the top of the barrier. Recall that the nanoMOS simulation ofFig. 5 shows that these quantities had a simple behavior at thetop of the barrier. In Fig. 10(a) and (b), we plot these two quan-tities from the analytical model. Fig. 10(a) shows, in agreementwith Fig. 5(a), that the charge at the top of the barrier is nearlyindependent of the drain bias. The initial dip and subsequentrise are also seen, although not as pronounced as in the full, nu-merical model. (The simpler model, which ignores the floatingsources, actually does better in this regime.) The initial rise andsubsequent saturation of the velocity at the top of the barrieris well-described by the simple model. These results show thatNatoris assumption (and our own in subsequent publications),where (0) is independent of drain bias, is a good one for typ-ical MOSFETs. In Section V, however, we will discuss a case


for which the assumption of a constant charge at the top of thebarrier is not valid.

In practice, the model developed in this paper may be usefulto compare the measured characteristics of nanoscale MOS-FETs to their ballistic limits. From the measured electrical char-acteristic, the technique presented in this section can be used toextract the parameters needed for the model. Another use for themodel might be to compare the upper limit performance of de-vices that use novel channel materials to that of the conventionalsilicon MOSFET. (The model has been formulated to allow theuse of numerically tabulated bandstructures.) Finally, we notethat the ballistic model is not entirely academic. Comparisonswith experiments suggest that present-day MOSFETs operateat roughly 50% of the ballistic limit [16], [32], and much of theresearch on new channel materials is motivated by a desire toapproach the ballistic limit.

V. MOLECULAR TRANSISTORS

The model presented in Section III was expressed in terms ofa general density-of-states so that it could describe transistorsmade from different semiconducting materials, even singlemolecule transistors. Carbon nanotube field-effect transistors(CNTFETs) are a type of molecular transistor that has alreadydemonstrated high on-currents [10]–[12]. Carbon nanotubescan be thought of as a sheet of graphene rolled up into a tube;depending on how the tube is rolled up, the nanotube maybe either semiconducting or metallic. For semiconductingnanotubes, eV/ , where is the diameter of thenanotube in nanometers [33]. For typical nanotube diameters(1–3 nm), the bandgaps are suitable for electronic devices,and the 1-D bandstructure allows ballistic transport over longdistances [10]. CNTFET technology is at an early stage ofdevelopment; it is still not clear how CNTFETs operate oreven if they all operate in the same way. One possibility isthat the gate modulates the conductance of the channel asin a MOSFET, which is supported by the observations thatsome long channel CNTFETs obey the MOSFET square lawtheory (with inferred mobilities of several thousand) and thatambipolar behavior is not observed in these devices [12].Another possibility is that the gate modulates the transmissionthrough a Schottky barrier between the source metal and thenanotube channel, which is supported by the observation ofambipolar operation of some CNTFETs and the transitionfrom the p-type to the n-type operation after gas absorption[34]. Whether a CNTFET operates like a MOSFET or like aSBFET may depend on details of the processing and devicestructure that are still not fully understood at this time. Themaximum performance of a ballistic carbon nanotube FETshould, however, occur for MOSFET-like operation. AchievingMOSFET-like operation will require learning how to heavilydope nanotubes (both n- and p-type) or achieving small oreven negative Schottky barriers [35], [36]. Such devices wouldbehave much like ballistic MOSFETs with some differencesdue to the 1-D density of states. CNTFETs, however, also offerthe possibility of operation at the quantum capacitance limitwhere some interesting effects that do not occur in MOSFETsarise.

(a)

(b)

Fig. 11. (a) Normalized electron density at the beginning of the channel versusthe drain voltage atV = 0:4 V for three N-type, 3-nm-diameter CNTFETswith C = 0:4 pF/cm (dash-dot line), 5 pF/cm (dashed line), and 90 pF/cm(solid line). (b) Charge versus the gate voltage curves forC = 90 pF/cm.The power supply voltage specified by ITRS for the 2016 technology node [1](0.4 V) is assumed in the subsequent calculations.

The quantum capacitance limit occurs when the gate in-sulator capacitance is much larger than the semiconductor(or quantum) capacitance. For MOSFETs, it is unlikely thatoperation in the quantum capacitance limit will be achieved,but for CNTFETs, the situation is different. Operation in anaqueous environment and the absence of dangling bonds,which facilitates the use of high-gate dielectrics [12], providethe possibility to achieve large gate insulator capacitance, andthe relatively low density of states in 1-D conductors reducesthe quantum capacitance [recall (2)]. Consider, for example,an electrolytically gated CNTFET with the effective oxidethickness nm and dielectric constant [10].The quantum capacitance of the nanotube can be estimatedas 4 pF/cm, whereas that of the insulator is about 90 pF/cm;therefore, the total gate capacitance is approximately. Evenfor a recently reported 8-nm-thick ZrO-gated CNTFET [12],the insulator capacitance is about 5 pF/cm, which is larger thanthe quantum capacitance.

MOSFET-like CNTFETs can be treated with the analyticalmodel described in Section III if the appropriate is used[37]. Fig. 11(a) plots the charge density at the top of the bar-rier versus the drain voltage for three different gate capacitance


Fig. 12. Intrinsic device delay metric versus the on-off current ratio for a modelballistic MOSFET and for a MOSFET-like CNTFET. The solid line is for adouble gate Si MOSFET with channel lengthL = 10nm, gate oxide thicknesst = 1 nm, and dielectric constant� = 4, and the dashed line is for acoaxially gated CNTFET withL = 10 nm, t = 2 nm, and� = 25.The power supply voltageV = 0:4 V. By adjusting the gate work function,the� versusI =I characteristics was obtained.

values. When , the charge at the beginning of thechannel is nearly independent of the drain voltage, and the tran-sistor operates at the charge control limit typical for MOSFETs.On the other hand, when , the charge at the be-ginning of the channel decreases by a factor of two asin-creases. In the quantum capacitance limit, instead of holding thecharge constant, the gate holds the nanotube potential constantat the gate potential. In this sense, the device operates more like abipolar transistor [29]. Because the nanotube potential is pinnedby the gate voltage, increasing the drain bias suppresses theby half of the distribution function and reduces the charge den-sity by a factor of 2. At high , therefore, the gate capacitanceis only one half of its equilibrium value, as shown in Fig. 11(b).Operation in the quantum capacitance limit has some interestingimplications: The on-off ratio increases, and the channel con-ductance and transconductance approach the same value [38].

To explore the possible role of CNTFETs in future electronicsystems, it is important to compare the upper limit performanceof a ballistic CNTFET to that of a ballistic silicon MOSFET.We consider MOSFET-like CNTFETs because they should havea higher performance limit that a Schottky barrier FET. Di-rect comparison of the on-current is clouded by the need toconvert the CNTFET on-current to per unit width basis; it ispreferable to compare quantities that are dimensionless or thathave the same dimensions. A useful set of performance met-rics, which are independent of the channel dimensions, are 1)the device delay metric (on) and 2) the on-offcurrent ratio . For these comparisons, we considertwo devices: 1) a 10-nm channel length ballistic, double-gateMOSFET with nm and ; and 2) a 10-nm channellength, ballistic coaxial-gate CNTFET with nm and

. A high- dielectric is used for the CNTFETs becauseit has already been achieved [12].

Fig. 12 compares the on-off current ratio and the delay metricof MOS and CNT technologies. The power supply voltage wasfixed at 0.4 V, the workfunction was varied, and the resultingand plotted. The delay metric was evaluated usingthe simple, analytical model with and a constant gate

capacitance , which was extracted from the charge versusthe gate voltage relation above the threshold. On theversus

plane, operation in the lower right hand corner is pre-ferred, and the CNTFET shows a clear advantage. For a devicedelay of 0.05 ps, the CNTFET has an on-off ratio that is morethan 100 times that of the MOSFET. For an on-off ratio of 1000,the CNTFET operates at twice the speed of the MOSFET. Theadvantage arises from three factors. First, the nanotube band-structure delivers higher carrier velocities, which translates di-rectly to lower switching delays. Second, the use of high-gatedielectrics leads to higher induced charge in the channel, whichincreases the carrier velocity by pushing the Fermi level highinto the band where it is steep. Finally, the low quantum capac-itance coupled with the use of high-gate dielectrics facilitatesthe direct modulation of the barrier height by the gate voltage,without volt drops across the gate insulator. Although these areupper limit estimates for each device, they show a considerableperformance promise for the CNTFET—one that merits seriousstudy.

VI. DISCUSSION

The simple model we have developed does a rather good butnot perfect job of reproducing more detailed numerical simula-tions. The discrepancy under high gate and drain bias was re-solved by forcing the potential at the top of the barrier tofollow the floating source potential, but the high-gate, low-drainbias region is better described when is not allowed to followthe floating source potential. The reason for this behavior can beunderstood from Fig. 4. Under high gate and drain bias, the po-tential energy maximum is pushed up against the source; there-fore, it seems reasonable that follows the floating potentialin the source. Under low drain bias, it is not pushed as close tothe source, and therefore, is not as tightly coupled to thesource potential. Whether this physics can be captured in an an-alytically simple way is still under investigation.

The model that we have developed describes MOSFET-liketransistors in which the gate modulates the channel conductanceand the contacts are nearly ideal. Other types of transistors are,however, possible. One possibility is that the source-drain cur-rent is limited by a metal/semiconductor junction at the sourceend of the channel whose tunneling resistance is modulated bythe gate. The Schottky barrier MOSFET (SBFET), which re-places the heavily doped silicon source drain with a silicide, isone such example [39], [40]. The question of whether our modelapplies to SBFET-like transistors is the subject of this section.

Ballistic SBFETs can be simulated by NEGF techniques sim-ilar to those used for MOSFETS [35]. We simulate a 10-nmchannel length, double-gate, ultra-thin body SBFET with a sim-ilar device geometry to the MOSFET shown in Fig. 1. Fig. 13shows the versus characteristic compared with the re-sult of the simple, analytical model described in Section III. Itsclear that the simple model overestimates the on-current of thisdevice. Fig. 14, which plots the first conduction subband min-imum versus position at different gate voltages, explains whythe simple model fails for the SBFET. At low gate bias, a largebarrier limits the drain current. Gate modulation is achieved byreducing the barrier height, which is a mechanism similar to that


Fig. 13. I versusV characteristics of a ballistic SBFET as simulated bythe NEFG approach (dashed line) and the corresponding ballistic MOSFETcharacteristics as obtained by the analytical model (the solid line). Thedouble-gate SBFET has a gate and channel lengthL = L = 10 nm,silicon body thickness oft = 1:5 nm, gate oxide thickness oft = 1 nmwith � = 4, and an effective Schottky barrier height of� = 0:2 eV. Theoff current wasI = 1 �A/�m in both cases.

Fig. 14. First conduction subband energy versus position for the SBFET fromthe off-state (V = 0 andV = 0:4 V) to the on-state (V = V = 0:4 V).The shaded region is the silicide source (drain) with the Fermi levelE ,E .

of the MOSFETs, but at high gate voltages, a conduction bandspike, which appears near the source end of the channel, limitsthe current. The gate modulates the current by squeezing thebarrier width, which increases quantum mechanical tunnelingthrough the barrier. Because device operation is not governedby thermionic emission, we cannot identify a beginning-of-the-channel, where the charge density is nearly independent of thedrain voltage, and the average carrier injection velocity can becomputed by simple semiclassical carrier statistics. The analyt-ical model of Section III, as well as the semiclassical Boltz-mann transport equation, do not apply to this device. In the con-ventional MOSFET, transistor action occurs by modulating thecharge in the channel; in the SBFET, transistor action occurs bymodulating the transmission coefficient of the device. To simu-late typical SBFETs with a positive M/S barrier height, an ap-proach that treats the gate-modulated tunneling at the sourcecontact is needed.

VII. CONCLUSIONS

In this paper, we have developed a simple analytical model forballistic nanotransistors that operate by modulating the chargein the device (as opposed to modulating the current at the con-tact). For conditions typical of silicon MOSFETs and when 2-Deffects are small, this surface potential model reduces to Na-toris theory of the ballistic MOSFET. When the insulator ca-pacitance exceeds the quantum capacitance, however, some in-teresting new effects arise. This analytical model captures theessential physics of MOSFET-like ballistic nanotransistors andprovides a convenient way to assess and compare transistors atthe ballistic limit.

APPENDIX

Fig. 6 shows how the states at the top of the barrier are occu-pied for a simple relationship. As mentioned in Section III,the energy reference is the top of the barrier at zero terminal bias.We express the source Fermi level , drain Fermi level ,and potential at the top of the barrier for first subband withrespect to this reference. The positive-states are then occupiedaccording to the Fermi level of the source to find

where is a constant energy surface in-space, is anelemental area on this surface, and is the distancebetween the surfaces and [41]. Defining thedensity-of-states as

we finally have

(A1)

The last expression is valid for general bandstructure in 1-D,2-D, or 3-D. The density-of-states function is either analyticallyexpressed or is numerically tabulated. For a 2-D electron gaswith isotropic and parabolic relationship, we have

where is the 2-D density-of-states, when spindegeneracy and a valley degeneracy of two for the unprimedsubband in silicon are considered. In this case, the integral for

can be analytically evaluated as

(A2)

where is the effective 2-D den-sity-of-states, is the Fermi Dirac integral of order 0,and . A similar expression existsfor with replaced by .


In addition to the carrier density, we can also evaluate currentfor the positive population from

(A3)

where is the average value of over the constant en-ergy surface , which is expressed as

Now, defining the current-density-of-states as

(A4)

we have

(A5)

In general, this expression can be evaluated for either numeri-cally tabulated or analytically calculated bandstructures. For the2-D electron density considered here, we can analytically eval-uate to obtain

(A6)

where the factor appears because of averagingover allpossible values at energy . With this expression for

, we can analytically integrate (A5) to find

(A7)

Similar expression can be obtained for negative going carriers,with replaced by .

When the drain bias is large, only the states areoccupied, and we can evaluate the maximum velocity at the topof the barrier as

(A8)

The presence of the Fermi–Dirac integrals in this expressionexplains why the saturation injection velocities in Figs. 5(b) and10(b) are gate bias dependent. Below threshold voltage, the ratioof the Fermi–Dirac integrals is one, and the injection velocity

(a)

(b)

(c)

Fig. 15. Treating floating boundary condition. (a) Under lowV , chargeneutrality in source extension is maintained by onlyE . (b) WhenV isincreased, barrier lowers and charge neutrality is not maintainted. (c) RaisingE toE restores charge neutrality in source entension.

becomes constant. The injection velocity at the highest gate biasdetermines the maximum on-current that a transistor can deliver.


Finally, we will discuss the treatment of the floating boundarycondition in the analytical model. In Fig. 15(a), we see that atlow gate and high drain bias the barrier height is large, i.e.,

, and inside the source, both positive and nega-tive going states are at equilibrium with the source Fermi level.The charge neutrality condition demands

(A9)

where is the doping density in the source extension.When high gate bias is applied, we can see in Fig. 15(b) that

the barrier height becomes small, and there are three distinctgroups of carriers: i) carriers with energy lower than the bar-rier height and are reflected by the barrier, ii) carriers with en-ergy higher than the barrier and having positive velocity, and iii)carriers having energy above barrier and going in the negativedirection. Population groups i) and ii) are at equilibrium with

, and group iii) is in equilibrium with . Because thesum of the three populations in Fig. 15(b) is smaller than equi-librium carrier density in source, to maintain charge neutrality,we have to increase ( ). Physically, is fixed, and

floats down. Equivalently, as shown in Fig. 15(c), we cankeep fixed and float up. In our analytical model, wehave treated the floating boundary condition by fixing andfloating up to . Therefore, the charge neutrality condi-tion in the source is

(A10)

Equation (A10) is solved self consistently with (3)–(8), i.e.,for each , barrier height is computed to distinguish threecarrier populations, and charge neutrality in the source is en-sured.

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Anisur Rahman received the B.Sc. degree inelectrical and electronics engineering from theBangladesh University of Engineering and Tech-nology, Dhaka, Bangladesh, in 1997. In the Fall of1999, he joined the Purdue Nanotransistor ResearchGroup, Purdue University, West Lafayette, IN, wherehe is currently pursuing the Ph.D. degree.

His research interests are centered around thephysics of decananometer-scale MOSFET devicesand includes their designing, analytical modeling,and prospect of performance enhancement through

the use of novel-channel materials.

Jing Guo was born in China in 1976. He receivedthe B.S. degree in electronic engineering in 1998 andthe M.S. degree in microelectronics and solid-stateelectronics in 2000, both from Shanghai Jiao TongUniversity, Shanghai, China. He is currently pursuingthe Ph.D. degree in electrical engineering at PurdueUniversity, West Lafayette, IN.

His research interests include design, modeling,and simulation of the novel electronic devices at thenanometer scale.

Mr. Guo is a student member of American PhysicalSociety (APS).

Supriyo Datta (F’96) received the B.Tech. degreefrom the Indian Institute of Technology, Kharagpur,India, in 1975 and the Ph.D. degree from the Uni-veristy of Illinois at Urbana-Champaign in 1979.

In 1981, he joined Purdue University, WestLafayette, IN, where he is currently the ThomasDuncan Distinguished Professor with the School ofElectrical and Computer Engineering. His currentresearch interests are centered around the physics ofnanostructures and includes molecular electronics,nanoscale device physics, spin electronics, and

mesoscopic superconductivity. He has authored three books:Surface AcousticWave Devices(Englewood Cliffs, NJ: Prentice Hall, 1986),Quantum Phe-nomena(Reading, MA: Addison-Wesley, 1989), andElectronic Transport inMesoscopic Systems(Cambridge, U.K.: Cambridge University Press, 1995).

Dr. Datta received a NSF Presidential Young Investigator Award and a IEEECentennial Key to the Future Award in 1984, the Frederick Emmons TermanAward from the ASEE in 1994, and shared the SRC Technical Excellence Awardin 2001 and the IEEE Cledo Brunetti Award in 2002 with M. Lundstrom. He isa Fellow of the American Physical Society (APS) and the Institute of Physics(IOP) and

Mark S. Lundstrom (F’94) received the B.E.E. andM.S.E.E. degrees from the University of Minnesota,Minneapolis, in 1973 and 1974, respectively, andthe Ph.D. degree from Purdue University, WestLafayette, IN, in 1980.

He is the Scifres Distinguished Professor of Elec-trical and Computer Engineering at Purdue Univer-sity, where he also directs the NSF Network for Com-putational Nanotechnology. Before attending Purdue,he was with Hewlett-Packard Corporation, Loveland,CO, working on integrated circuit process develop-

ment and manufacturing. His current research interests center on the physicsof semiconductor devices, especially nanoscale transistors. His previous workincludes studies of heterostructure devices, solar cells, heterojunction bipolartransistors, and semiconductor lasers. During the course of his career at Purdue,he has served as Director of the Optoelectronics Research Center and AssistantDean of the Schools of Engineering.

Dr. Lundstrom is a Fellow of the American Physical Society and the recip-ient of several awards for teaching and research—most recently the 2002 IEEECledo Brunetti Award and the 2002 Semiconductor Research Corporation Tech-nical Achievement Award for his work with S. Datta on nanoscale electronics.

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Ballistic Nano Transistors