Back End Downconverter

EOVSA Preliminary Design Review 1

Back End Downconverter

Wes GrammerNRAO

March 15-17, 2012


Outline

• Design requirements• Block diagram and cascade analysis• Spurious analysis• Component selection• Module & rack-level packaging• Interfaces (mechanical and electronic)• Production assembly and test• Costing and schedule

March 15-17, 2012


Back End Downconverter Design Requirements and Specifications

• Convert selected 0.5 GHz-wide RF sub-band to baseband frequency (650 - 1150 MHz)

• SMF input w/mux’d dual lin. polarizations, 1-18 GHz RF• Overall Tsys < 400K, at ambient (~298K)• Gain stability < 1%, phase stability < 1°, over TBC sec.• Baseband output power: -2 dBm, nom., both channels• Spurious and harmonic suppression: -57 dBc, min.• Monitor and control:

– Serial I/O bus, RS-485 signaling, ~1.0-3.5 Mbps asynchronous transfer– 100 us max. overall latency for output level (step attenuator) control, including serial

data transfer delays• Rack-mountable unit, with high packing density• Environment: Indoor, temperature control• MTBF > 15 years

March 15-17, 2012


Downconverter Module Block Diagram

March 15-17, 2012

1st IF20-20.5 GHz

1st IF20-20.5 GHz

LO1 (21.5-38 GHz)

2nd IF0.65-1.15 GHz

2nd IF0.65-1.15 GHz

LO2 (21.15 GHz)

M&C I/O RS-485

V Out-2 dBm

H Out-2 dBm

LO1 In+2 dBm

LO2 In 0 dBm

O P T_ R X2

F O R e c e iv e rO p t i la bL R -3 0 +V

O U T

P A D 9

-3 dB

S A 3 01 5-0 3F a irv ie w

A 1 0

2 8 dB g a in+1 6 d B m P o _1 d B(M f g TB D )(M f g p / n TB D )

M 4

D o ub le -B a l. M ix e rM a rk iM 1 R -0 72 6 LS

R F

LO

I F

F I LT3

0 . 6 5 -1 . 1 5 G H z B P F<M an u f ac t u re r><M an u f ac t u re r p / n >

4 -B it D ig it a l A t t e nu a t o r

A TN 2

0 - 1 5d B a t te n .J F W 50 P -1 93 4

I N O U T

P A D 1 0

-3 dB

S A 3 01 5-0 3F a irv ie w

S P L1

10 -4 0 G H z S p lit t e rP 2 K 9AA TM

1

2

S

A 517 dB g a in , 6 dB N F+1 8 d B m P o _1 dBM ark i A - 18 44

A 2

3 0 d B g a in , 3 d B N F+1 0 dB m P o _1 d B(M f g TB D )(M f g p / n TB D )

U 3

E m b ed d ed M P U(p / n )(TB D )

O [ 1 . . 8 ]M B _ I

M B _O

A 1

3 0 d B g a in , 3 d B N F+1 0 dB m P o _1 d B(M f g TB D )(M f g p / n TB D )

V _P in

H _ P in

A 317 dB g a in , 6 dB N F+1 8 d B m P o _1 dBM ark i A -18 44

Downconverter Module Assembly Enclosure

P A D 4

-3 dB

B W -S 3 -2 W 2 63 +M in i-C k t s

D 4S c ho t t k y D e t e c t o rK ry t a r20 1 A P

RF

P A D 3

-3 dB

B W -S 3 -2 W 2 63 +M in i-C k t s

M 1

D o ub le -B a l. M ix e rM ark iM 9-0 9 42 L N

R F

LO

I F

A 7

2 8 d B g a in , 1 . 3 d B N F+10 . 5 d B m P o _1 d BTe le d y ne / C o ug a rA C -12 8 6C

F I LT4

0 . 6 5 -1 . 1 5 G H z B P F<M an u f ac t u re r><M an u f ac t u re r p / n >

P A D 2

-3 dB

B W -S 3 -2 W 2 6 3 +M in i-C k ts

4 -B it D ig it a l A t t e nu a t o r

A TN 1

0 - 1 5d B a t te n .J F W 50 P -1 93 4

I N O U T

I S O 2

2 0 -23 G H z I s o l.A Ti2 0 -23A TM

F I LT1

20 -2 0 .5 G H z B P F<M an u f a c t u re r><M an u f a c t u re r p / n >

Analog Fiber Input from Antenna FE

V Pol In1-18 GHz

F I LT2

20 -2 0 .5 G H z B P F<M an u f a c t u re r><M an u f a c t u re r p / n >

A 7

D u a l-d e t . p re a m p

E O V S AE O V S A -F E -2 M -D E T-A

O P T_ R X1

F O R e c e iv e rO p t i la bL R -3 0 +V

O U T

A 4

17 dB g a in , 6 dB N F+1 8 d B m P o _1 dBM ark i A -18 44 A 6

17 dB g a in , 6 dB N F+1 8 d B m P o _1 dBM ark i A - 18 44

A 8

2 8 d B g a in , 1 . 3 d B N F+10 . 5 d B m P o _1 d BTe le d y ne / C o ug a rA C -12 8 6C

M 3

D o ub le -B a l. M ix e rM a rk iM 1 R -0 72 6 LS

R F

LO

I F

D 1S c ho t t k y D e t e c t o rK ry t a r20 1 A P

RF

A 9

2 8 dB g a in+1 6 d B m P o _1 d B(M f g TB D )(M f g p / n TB D )

C P 2

20 d B C o up le rK ry t a r18 0 1 20

P A D 1

-3 dB

B W -S 3 -2 W 2 6 3 +M in i-C k ts

M 2

D o ub le -B a l. M ix e rM ark iM 9-0 9 42 L N

R F

LO

I F

P A D 7

-3 d B

S A 3 0 15 -0 3F a irv ie w

P A D 8

-3 d B

S A 3 0 15 -0 3F a irv ie w

C P 1

20 d B C o up le rK ry t a r18 0 1 20

S P L 2

2 -26 . 5 G H z S p lit t e r6 0 20 2 65K ry t a r

1

2

S

I S O 1

2 0 -23 G H z I s o l.A Ti2 0 -23A TM

W D M 1D ip le x e rO p t ila b L O 1

M B U S _ IN

S M F I n pu t

H _ O U T

V _ O U T

L O 2

M B U S _ O U T

H Pol In1-18 GHz

EOVSA Preliminary Design Review 5March 15-17, 2012


System Cascade Analysis• Key results, after optimization:

– Overall Tsys < 330K up to -50 dBm, but rises way over 400K for strongest input

• Extra attenuation for signal leveling in Front End, along with high link loss make Tsys sensitive to component loss in the Downconverter, esp. in 1st IF stage. An isolator is used for a low-loss signal match before 2nd mixer.

• Effect is greatly reduced by driving optical TX harder (+11 dBm). Overall Tsys is still slightly higher than spec, ~420K

• Increasing 1st amp gain helps, but limited by mixer P1dB• Alternatively, extra gain can be added between the mixers, but at significant

extra cost and added complexity.– 1st mixer is ~4 dB under P1dB in worst case

• Higher LO drive helps, but only 2-3 dB may be available over nom. +10 dBm, because of high loss in LO distribution at 38 GHz

March 15-17, 2012


Spurious Analysis• Excel document in archive contains detailed analysis of spurious

outputs and harmonics, and filter specs• Summary of key results:

– Neither mixer evaluated for the 1st conversion stage has required spurious suppression, but one (Marki M9-0942) comes close at all but lowest frequencies.

– Based on the RF-IF isolation of the 1st mixer, the 18 GHz LPF in the Front End need to have at least 53 dB of stopband rejection from 20-20.5 GHz.

– 1st LO leakage into the signal path is most serious at 22 GHz, where the resulting spur is in the 2nd IF passband. Almost 80 dB of filter rejection is needed at this frequency in the 1st IF BPF.

– 2nd IF filter needs to have 57 dB stopband rejection below 550 MHz and above 1250 MHz, to avoid distortion from aliasing

March 15-17, 2012


Component Selection Criteria• Flat frequency response, where possible• Good VSWR, where possible, to limit mismatch loss and gain ripple• Adequate P1dB in the amplifiers, to ensure good linearity• High-intercept mixers not feasible, due to high cost of required LO

drive power• Mixer LO drive configuration in Downconverter is tied closely to

design of LO Distribution module, to minimize total overall cost• Common bias voltages (e.g., +12V), where possible• Cost is critical: There are 30 of each Downconverter component

types in the array, an expensive item can have a large impact in the overall budget.

March 15-17, 2012


Module / rack layout considerations

• High-frequency paths (RF, IF1, LO1, LO2) should be as short and direct as possible, to minimize losses and added reflections.

• Single component layer desired, for ease of assembly and service, and is space-efficient. Module depth limited to ~1.25”

• Vertically-oriented slide-in rack modules with spaces between, to allow air flow for cooling

• Assuming 19” rack width, two rows of 8 modules each, 5U or 6U high would probably work

• Use shielding and filtering on digital boards, shielded cables, to limit EMI

March 15-17, 2012


Downconverter Rack Modules Conceptual Layout

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COTS module (Schroff 6U x 8HP)

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Downconverter Assembly Interfaces

• Hardware:– (1) SC/APC SM fiber connector, signal input– (1) 2.92mm male coax adapter, 1st LO (LO1) input– (1) SMA male coax adapter, 2nd LO (LO2) input– (2) SMA male coax adapter, baseband IF outputs– (2) DB-9 or 10-pin RJ-style connectors, M&C I/O– (1) MIL-DTL-26482 connector, DC power input

• Software:– Refer to table in following slide

March 15-17, 2012


Signal Name Dir. Type Mode Range Min Range Max Unit Connector Freq/Rate Precision

X / Y Pol from FE In RF on fiber Analog Fiber -30 -35 dBm SC/APC 1-18 GHz N/A

10 MHz Ref In RF CW Analog Elec (TBD) 16 dBm BNC 10 MHz N/A

50 Hz Sync In Pulse Analog Elec 0 5 V BNC 50 Hz 1 us

LO1 Sub A Mon/Ctrl I/O SCPI Data Digital Elec n/a n/a n/a Ethernet 50 Hz 10 us

LO1 Sub B Mon/Ctrl I/O SCPI Data Digital Elec n/a n/a n/a Ethernet 50 Hz 10 us

Subarray Setting In Integer Digital Elec 0 5 V RS-485 ~1/day 1 s

LO2 PLO Lock Alrm Mon Out Bool Digital Elec n/a n/a n/a RS-485 1 Hz 1 s

RX PwrOut Mon X-Pol Out Float Digital Elec -35 -15 dBm RS-485 50 Hz 1 ms

RX PwrOut Mon Y-Pol Out Float Digital Elec -35 -15 dBm RS-485 50 Hz 1 ms

Atten Ctrl X-Pol In Integer Digital Elec 0 15 dB RS-485 1 Hz 10 us

Atten Ctrl Y-Pol In Integer Digital Elec 0 15 dB RS-485 1 Hz 10 us

X Pol from DC Out IF Power Analog Elec -5 -2 dBm SMA650-1150 MHz N/A

Y Pol from DC Out IF Power Analog Elec -5 -2 dBm SMA650-1150 MHz N/A


Production Assembly, Testing

• Production process steps– Two-port VNA measurement of amplifiers, filters,

digital attenuators, couplers, mixers (port-port isolation), and optical link sets

– Mechanical assembly of Downconverter– Conversion loss measurement vs. frequency of

Downconverter RF chain, w/o optical RX– Verification of M&C functionality– Documentation: Test results, configuration (s/n) list

March 15-17, 2012


Component Costing, Delivery• All RF components except BPFs and 2 amplifiers have been

specified, price/delivery quotes received• Good estimates or preliminary pricing on most remaining

electronic components• Enclosure, connector and cable pricing are rough estimates,

final TBD• Gain equalizer spec is TBD: need to characterize actual

component cascade before specifying and ordering• Long lead times (over 12 weeks):

– Optical links, in production quantity. Small quantity are available out of stock

March 15-17, 2012



Important Schedule Dates for Downconverter Prototypes

• Have all RF components and COTS support electronics on order by end of April.• Complete mechanical CAD models and fabrication drawings by May 1, send out

for quotes, begin fab in mid-May• May 1 – June 30: Design, PCB fab and component ordering for custom support

electronic boards• July 1 – July 15: Order the rack(s), cables, connectors, wire, remaining

components for prototype unit construction and site installation• July 1 – August 1: RF component characterization• August – September: Assemble and test 3 prototypes• October 1: Ship 3 prototypes to California for installation• Downconverter embedded firmware and test software may need to be farmed

out, in the interest of saving time. This could happen during July and August, in parallel with module assembly.

March 15-17, 2012

Documents

Back End Downconverter