Advanced VLSI LaboratoryIIT Kharagpur

BackEnd Flow of Digital Design

Debdeep Mukhopadhyay

debdeep@vlsi.iitkgp.ernet.in

Advanced VLSI LaboratoryIIT Kharagpur

What is Backend?

• Physical Design:

1. FloorPlanning : Architect’s job

2. Placement : Builder’s job

3. Routing : Electrician’s job

Advanced VLSI LaboratoryIIT Kharagpur

Definitions:

• FloorPlanning : 1. Estimate the sizes and set the initial

relative locations of the various blocks in our ASIC.

2. Allocate space for clock and power wiring

3. Decide on the location of the I/O and power pads.

Advanced VLSI LaboratoryIIT Kharagpur

Definitions (contd.)

Placement

•Defines the location of logic cells.

•Sets space for the inter-connect to each logic cell.

•Assigns each logic cell to a position in a row.

Routing

•Makes the connections

between logic cells.

•Global routing : Determines where the inter-connections between the placed logic cells and blocks will be placed.

•Local Routing: Joins the logic

cells with interconnects.

Advanced VLSI LaboratoryIIT Kharagpur

CAD Tools

• Floorplanning: Goal: Calculate the sizes of all the blocks and assign them locations. Objectives: Keep the highly connected blocks close.• Placement: Goal: Assign the interconnect areas and the location of the logic cells. Objectives: Minimize the ASIC area and the interconnect density. • Global Routing: Goals: Determine the location of all the inter-connects. Objectives: Minimize the total interconnect area used.• Detailed Routing: Goals: Completely route all the interconnect on the chip. Objectives: Minimize the total interconnect length used.

Advanced VLSI LaboratoryIIT Kharagpur

Our Dear tool : Silicon Ensemble

• LEF: Cell boundaries, pins, routing layer (metal) spacing and connect rules.

• DEF: Contains netlist information, cell placement, cell orientation, physical connectivity.

• GCF: Top-level timing constraints handed down by the front end designer are handed to the SE, using PEARL.

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The Tutorial

Advanced VLSI LaboratoryIIT Kharagpur

The files required

• Pre-running file:

se.ini- initialization file for SE.

• Create the following directories:

lef, def, verilog (netlist) , gcf.

• Type seultra –m=300 &, opens SE in graphical mode.

Advanced VLSI LaboratoryIIT Kharagpur

Importing required files

• Import LEF (in the order given): header.lef, xlitecore.lef, c8d_40m_dio_00.lef• Import gcf file:• Import verilog netlist, xlite_core.v,

c8d_40m_dio_00.v, padded_netlist.v• Import the gcf file as system constraints

file.• Import the .def file for the floor-planning

Advanced VLSI LaboratoryIIT Kharagpur

Structure of a Die

• A Silicon die is mounted inside a chip package.• A die consists of a logic core inside a power ring.• Pad-limited die uses tall and thin pads which

maximises the pads used.• Special power pads are used for the VDD and

VSS.• One set of power pads supply one power ring that

supplies power to the I/O pads only: Dirty Power.• Another set of power pads supply power to the

logic core: Clean Power.

Advanced VLSI LaboratoryIIT Kharagpur

• Dirty Power: Supply large transient current to the output transistor.

• Avoids injecting noise into the internal logic circuitry.

• I/O Pads can protect against ESD as it has special circuit to protect against very short high voltage pulses.

Advanced VLSI LaboratoryIIT Kharagpur

Design Styles

• PAD limited design: The number of PADS around the outer edge of the die determines the die size , not the number of gates.

• Opposite to that we have a core-limited design.

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Concept of clock Tree

Main Branch

Clock Pad

Side Branches

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CLK

A1, B1, C1

D1, D2, E1

D3, E2, F1

Clock Spine

C1 C2 C3

An important result:

The delay through a chain of CMOS gates is minimized when the ratio between the input capacitance C1 and the load C2 is about 3.

CLOCK DRIVER

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Clock and the cells

A1

B1

B2

E1

E2

F1

D3

D1

D2

CLK

Advanced VLSI LaboratoryIIT Kharagpur

• All clocked elements are driven from one net with a clock spine, skew is caused by differing interconnect delays and loads (fanouts ?).

• If the clock driver delay is much larger than the inter-connect delay, a clock spline achieves minimum skew but with latency.

• Spread the power dissipation through the chip.

• Balance the rise and the fall time.

Advanced VLSI LaboratoryIIT Kharagpur

Placement• Row based ASICS.

• Interconnects run in horizontal and vertical directions.

• Channel Capacity: Maximum number of horizontal connections.

• Row Utilization

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Goals

• Arrange the logical cells within the flexible blocks.

• Minimize the critical net delay.• Chip as dense as possible• Minimize the power dissipation• Minimize cross talk• Very hard : minimize interconnect length, meet timing requirement for critical length and

minimize the interconnect congestion.

Advanced VLSI LaboratoryIIT Kharagpur

Timing Driven Placements

• Estimate delay for every net in every trial placement

• We may estimate length but layers and vias are not known.

• Hence estimate the RC values.

• But still the results are satisfactory.

Advanced VLSI LaboratoryIIT Kharagpur

Routing

• Minimize the interconnect length.

• Maximize the probability that the detailed router can completely finish the job.

• Minimize the critical path delay.

Advanced VLSI LaboratoryIIT Kharagpur

Conclusion: Our backend flow

1. Loading initial data.2. Floor-planning3. I/O Placing4. Planning the power routing : Adding Power rings , stripes5. Placing cells6. Placing the clock tree.7. Adding filler cells.8. Power routing : Connect the rings to the follow pins of the cells.9. Routing ( Global and final routing )10. Verify Connectivity, geometry and antenna violations.11. Physical verification (DRC and LVS check using Hercules).12. Best of luck in the Lab Thank You