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B. Todd AB/CO/MI BIS Audit 18th September 2006
Test and Monitor with the CIBT
LHC Beam Interlock System 2 of 25 [email protected]
Test and Monitor with the CIBT
2. CIBT Realisation- Serialiser / Deserialiser- BEAM_PERMIT_INFO- CIBTD Display Driver- Remarks
1. CIBT Overview- Location- SPS vs LHC Chassis
LHC Beam Interlock System 3 of 25 [email protected]
Overview
CIBT linked to each CIBM-TESTing CIBU
-MONITORing CIBU-Drives Beam Permit Info
For some CIBU
LHC Beam Interlock System 4 of 25 [email protected]
OverviewLHC Type Chassis SPS Type Chassis
LHC Beam Interlock System 5 of 25 [email protected]
Principle FunctionCIBT primarily acts as a SERialiser DESerilaiser (SERDES),
Or.. A fancy MUX / DEMUX of serially encoded signals
‘hot’ redundancy!
LHC Beam Interlock System 6 of 25 [email protected]
TEST and MONITORSimple signal paths
-automatically swaps between broken links inside the controller-appends internal status of the CIBT
LHC Beam Interlock System 7 of 25 [email protected]
Implementation
Implemented in Spartan 2 FPGAs5V compatible I/O
It has two other functions..-Drive BEAM_PERMIT_INFO
-Illuminate a small Display
Display driver is carried out
independantly!
LHC Beam Interlock System 8 of 25 [email protected]
BEAM_PERMIT_INFOSimple circuits, a pair of majority voters…
-Extra pins were available, used to increase availability
ZT
ZT
ZT
LHC Beam Interlock System 9 of 25 [email protected]
BEAM_PERMIT_INFO LHCSimple circuits, a pair of majority voters…
-B1 versus B2 Circuits exploit RS485 multidrop:
LHC Beam Interlock System 10 of 25 [email protected]
BEAM_PERMIT_INFO SPSSimple circuits, a pair of majority voters…
-LEFT & RIGHT Circuits exploit RS485 multidrop:
LHC Beam Interlock System 11 of 25 [email protected]
Display CIBTDSimple display, short circuit can risk only the display FPGA
LHC Beam Interlock System 12 of 25 [email protected]
Functions ExplainedTESTING
-CIBM writes a buffer to the CIBT, serialised comms, not VME-CIBT transmits this information to the CIBU devices twice per second
MONITORINGCIBT writes a buffer to the CIBM, serialised comms, not VME
CIBT writes around 16 bits which represent internal stateCIBM transmits this combined information to the CIBM twice per second
-N.B. increasing the rate to 1k or thereabouts is planned (DC balancing)
BEAM_PERMIT_INFO-CIBT receives two sets of BPI signals, each in TMR--if either is TRUE, it sets the internal BPI to TRUE
-RS485 multidrop is used to accommodate all the configurations
CIBTD-The data sent back to the CIBM is sent in parallel to the CIBTD
-LEDs illumate corresponding to data
-Simple board, not critical if it fails!
LHC Beam Interlock System 13 of 25 [email protected]
FIN