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© 2011 ANSYS, Inc. May 11, 20121
Automating The SI Design Flow For HFSSPart 1
Greg Pitner
© 2011 ANSYS, Inc. May 11, 20123
1. Extraction
2. Virtual System
3. Virtual Compliance
Virtual System Prototyping
© 2011 ANSYS, Inc. May 11, 20125
Extraction
• Layout Geometry
• Broadband S-Parameters
• Frequency Dependent
• Causal/Passive
• SPICE Compliant Models
© 2011 ANSYS, Inc. May 11, 20126
Layout Integration for Extraction
Layout Generated in ECAD System
AnsoftLinks
Q3D Extractor
3D CAD Model
Ansoft Designer
HFSS
SIwave
Layout
Stackup
3D View
Workbench
IntegratedHFSS Solver
Icepak
© 2011 ANSYS, Inc. May 11, 20127
3D Modeler Approach
To assign the same variable within HFSS
• Area select all objects above the layer
UNNAMED_4
• Click Edit > Arrange > Move
• Define a Z only distance
• Go into Object tree and highlight all the objects that have a ‘Move’ in the history
• Click on the X,Y,Z coordinates in the Properties window
• Change the Z dimension to $diel_thickness
• Define $diel_thickness to a value
• Go to select ‘face’ mode
• Highlight the top of the dielectric material, and the tops of all the through hole vias
• Right click and select Edit > Surface > Move Faces > Along vector
• Define a Z only distance
• Go into Object tree and highlight the top dielectric object and the vias that have a ‘Move’ in the history
• Define a variable for ‘Move
© 2011 ANSYS, Inc. May 11, 20128
HFSS Solver On Demand – Advantages
• Layout Methodology
• Layout, Stackup, and Padstack Editors
• Parametric Design Environment
• Automated Geometry Clipping
• Maintain Trace Characteristics and Nets from Layout
• Port Setup
• Hierarchical Design – Chip/Package/Board
• Layout Optimized HFSS Settings
• Integrated Platform
© 2011 ANSYS, Inc. May 11, 20129
PCB Layout
2D Layout ViewStackup Editor
© 2011 ANSYS, Inc. May 11, 201210
Create PCB Ports
Select Trace Edges in Layout
Automatically create coupled waveports
© 2011 ANSYS, Inc. May 11, 201211
Hierarchal Design - Package on PCB
Package layout is a sub-circuit of the board cutout
Package stackup is independent of the PCB
Package placement layer and position can be specified in the
Footprint
© 2011 ANSYS, Inc. May 11, 201212
Merged Package and PCB Cutouts
2D Layout View 3D Layout View
© 2011 ANSYS, Inc. May 11, 201213
Integrated Platform
Port1:PCIE_RX2P_T2 Port1:PCIE_RX2N_T2Port1:PCIE_RX3P_T2 Port1:PCIE_RX3N_T2 Port9:PCIE_TX2P_T2Port9:PCIE_TX2N_T2Port9:PCIE_TX3P_T2Port9:PCIE_TX3N_T2
MGTRXP0_BumpMGTTXP0_BumpMGTRXN0_BumpMGTTXN0_BumpMGTRXP1_BumpMGTTXP1_BumpMGTRXN1_BumpMGTTXN1_Bump
MGTRXP0_Bump MGTTXP0_BumpMGTRXN0_Bump MGTTXN0_Bump
MGTRXP1_Bump MGTTXP1_BumpMGTRXN1_Bump MGTTXN1_Bump
© 2011 ANSYS, Inc. May 11, 201214
HFSS Solver on Demand - Solve
© 2011 ANSYS, Inc. May 11, 201215
Export to 3D HFSS Model from Designer
Integrate 3D Components
with PCB/Package Designs
© 2011 ANSYS, Inc. May 11, 201216
HFSS in Cadence Enables More Robust 3D Investigation
• Today, we will show the advances that we have made in our Solver on Demand capabilities which enable
– The solving of larger 3D models to determine optimal performance
– The ability to add and solve manufacturing variations to the 3D model
+ =
© 2011 ANSYS, Inc. May 11, 201217
HFSS in Cadence – Automation and Ease of Use
• Select nets of interest
– Signal, Power and Ground
• Draw extents to export selected portions of package or pcb
• Create ports on signal nets
• Specify HFSS solution setup
• Specify HFSS airbox extents
© 2011 ANSYS, Inc. May 11, 201218
HFSS in Cadence Package - Select Nets and Determine Extents
© 2011 ANSYS, Inc. May 11, 201219
HFSS in CadencePackage - Automatic Port Creation
© 2011 ANSYS, Inc. May 11, 201220
HFSS in CadencePackage - Airbox Extents and HFSS Solution Setup
© 2011 ANSYS, Inc. May 11, 201222
Extraction
• Layout Geometry
• Broadband S-Parameters
• Frequency Dependent
• Causal/Passive
• SPICE Compliant Models
© 2011 ANSYS, Inc. May 11, 201223
Differential Insertion and Return Loss Insertion Loss
Return Loss
© 2011 ANSYS, Inc. May 11, 201224
Frequency Dependant Materials
1. Multipole Debye Model Input
– This lets you provide the measured data of relative permittivity and loss tangent versus frequency. Based on this data the software dynamically generates frequency dependent expressions for relative permittivity and loss tangent.
2. Djordjevic-Sarkar Method
– HFSS allows you to enter the relative permittivity and loss tangent at a single measurement frequency. You may optionally enter the relative permittivity and conductivity at DC.
– This is the best method if you don’t have measured data.
© 2011 ANSYS, Inc. May 11, 201225
Causality Enforcement: Interpolating Sweeps
© 2011 ANSYS, Inc. May 11, 201226
Macro-modeling Functionality
Circuit Simulation• Designer• Simplorer• Other• State-space fitting
• Passivity enforcement• Passivity checker• S-parameter visualization• S-matrix reduction• Macro-model generation
HFSS
SIwave
Q3D
Network Data Explorer
Designer
• State-space• Simplorer• Spectre• HSPICE• PSPICE
Measured Data
New functionality for Designer 7
© 2011 ANSYS, Inc. May 11, 201227
Network Data Explorer
© 2011 ANSYS, Inc. May 11, 201228
Network Data Explorer• The S-Parameter data can be converted to
a macro model for use with circuit simulation in multiple formats:
Advanced features
New!
Original Option (fast but memory intensive).
New default, IFPV. Much lower memory requirements. Effective for high port counts.
© 2011 ANSYS, Inc. May 11, 201229
1. Extraction
2. Virtual System
3. Virtual Compliance
Virtual System Prototyping
© 2011 ANSYS, Inc. May 11, 201230
IBIS AMI
AMI stands for Algorithmic Modeling Interface
It allows users to specify their own transmitter and receiver models as C-interface compiled libraries
• Designer supports Matlab as well as compiled DLLs
• faster signal processing algorithms
• intellectual property protection
Mainly used in convolution (fast) transient engines for channel simulation• Designed to be used with fixed time step data
Introduced in IBIS 5.0 specs• http://eda.org/pub/ibis/ver5.0/ver5_0.txt
• IBIS stand for “I/O Buffer Information Specification”; high-level buffer specification for circuit modeling
• In these specs the library is specified inside the IBIS wrapper and the interface is called IBIS-AMI
© 2011 ANSYS, Inc. May 11, 201231
New AMI Import Process
Import from .ibs file or specific .ami file directly
© 2011 ANSYS, Inc. May 11, 201232
New AMI Import Process
• Automatically fill out fields for .dll and .so models • Test button runs IBIS committee parser and reports pass/fail• Advanced option used to set up models with non-standard behavior
© 2011 ANSYS, Inc. May 11, 201233
Advanced Options Form (Optional)
Model parameter tree
Sample Parameters string
Test results details
© 2011 ANSYS, Inc. May 11, 201234
Imported Component
AMI model parameters can be sweep able component parameters upon import
0
00
50
R6
50
R9
AM
IS
ource
ID=26
AM
IP
robe
ID=32
Port1Port2Port3Port4Port5Port6Port7Port8
Port9Port10Port11Port12Port13Port14Port15Port16
50
R149
50
R150
50
R151
50
R152
50
R153
50
R154
50
R155
50
R156
50
R157
50
R158
50
R159
50
R160
1
2
AM
IS
ource
ID=192
Tx Rx
© 2011 ANSYS, Inc. May 11, 201235
Schematic and Setup for AMI Analysis
0
00
50
R6
50
R9
AM
IS
ource
ID=26
AM
IP
robe
ID=32
Port1
Port2Port3
Port4
Port5
Port6
Port7
Port8
Port9
Port10Port11
Port12
Port13
Port14
Port15
Port16
50
R149
50
R150
50
R151
50
R152
50
R153
50
R154
50
R155
50
R156
50
R157
50
R158
50
R159
50
R160
1
2
Pkg on PCB model from HFSS Solver on Demand
15 inches long striplinedifferential pair from Designer library
Makes use of GPU card
© 2011 ANSYS, Inc. May 11, 201236
Eye Opening Before Receiver
© 2011 ANSYS, Inc. May 11, 201237
Eye Opening After Receiver DFE
© 2011 ANSYS, Inc. May 11, 201238
Part 1: Summary
• HFSS in Designer and Cadence enables SI engineers to setup and solve package and pcb models in 3D using HFSS
• Designer provides a complete framework to – Import ready to solve models from third party layout
– Enables HFSS Solver on Demand to solve HFSS models
– Check for passivity and causality to determine quality of S parameters and W elements
– Enforce passivity and causality on S parameters and W elements
– Greatly simplify the reading and execution of AMI models for transmitter and receivers through the new AMI importer
– Validate channel performance with statistical eye diagrams and various eye measurements
• HFSS in Cadence (a Solver on Demand feature) greatly enhances productivity of an SI engineer
© 2011 ANSYS, Inc. May 11, 201239
Automating The SI Design Flow For HFSSPart 2
Greg Pitner
© 2011 ANSYS, Inc. May 11, 201241
Manufacturing Variations
• When you take the dimensions of the HFSS model to be fabricated, the ideal shape of the traces/pads/vias can become distorted because of the manufacturing process of etching copper
• It is critical to simulate these manufacturing variations in order to validate your design will work after the manufacturing processes
• This process has become automated
Image courtesy of EMPFImage courtesy of AMKOR
© 2011 ANSYS, Inc. May 11, 201242
HFSS Solver On Demand – Advantages
• Layout Methodology
• Layout, Stackup, and Padstack Editors
• Parametric Design Environment
• Automated Geometry Clipping
• Maintain Trace Characteristics and Nets from Layout
• Port Setup
• Hierarchical Design – Chip/Package/Board
• Layout Optimized HFSS Settings
• Integrated Platform
© 2011 ANSYS, Inc. May 11, 201243
Assigning Variables
• Trace Width
© 2011 ANSYS, Inc. May 11, 201244
Assigning Variables – Layout Approach
• Dielectric Thickness
© 2011 ANSYS, Inc. May 11, 201245
Assigning Variables
• Etching Factor
© 2011 ANSYS, Inc. May 11, 201246
Surface Roughness
• At high frequencies, currents follow small surface imperfections on conductor surfaces
• Increases loss
• Mathematical models approximate loss increase due to surface roughness
• Hammerstad
• Groisse
• Hemispherical
• These work well for modest levels of roughness, but tend to underpredict loss for very rough surfaces
• PCB manufacturing processes often process layers to make them rough in order to improve layer adhesion
© 2011 ANSYS, Inc. May 11, 201247
Huray Model
• Huray Model treats a conductor surface as if it were stacked with small spheres
• Approximates the effect of electrodepositing a surface layer of copper on a smooth copper foil for better adhesion
• Assumes more surface area than Groisse model; can better model significantly rough surfaces
© 2011 ANSYS, Inc. May 11, 201248
Huray Surface Roughness Model
• Improved surface roughness model for copper on laminates
© 2011 ANSYS, Inc. May 11, 201249
Geometry Clipping
• Name the Partitions
• Automatically creates lumped ports at splits
• Automatically creates gap ports on pins (solderball/solderbumps)
• Automatically creates RLC Boundaries across the Capacitor pads
Port1:TX3_NPort1:TX3_PPort1:TX2_NPort1:TX2_PPort5:RX2_P
Port5:RX2_NPort5:RX3_PPort5:RX3_N
U1.M1.PCIE_TX3_PU1.M2.PCIE_TX3_N
U1.K1.PCIE_TX2_PU1.K2.PCIE_TX2_NU1.N3.PCIE_RX3_PU1.N4.PCIE_RX3_NU1.L3.PCIE_RX2_PU1.L4.PCIE_RX2_N
U1BGA_end1
Port1:TX2_PPort1:TX2_N
Port3:TX3_NPort3:TX3_P
Port5:RX2_NPort5:RX2_P
Port7:RX3_NPort7:RX3_P
P1.B23.PCIE_RX2_PP1.B24.PCIE_RX2_NP1.B27.PCIE_RX3_PP1.B28.PCIE_RX3_NP1.B21.GNDP1.B22.GNDP1.B25.GNDP1.B26.GNDP1.B29.GNDP1.B32.GNDP1.A25.PCIE_TX2_C_PP1.A26.PCIE_TX2_C_NP1.A29.PCIE_TX3_C_PP1.A30.PCIE_TX3_C_NP1.A20.GNDP1.A23.GNDP1.A24.GNDP1.A27.GNDP1.A28.GNDP1.A31.GND
C17.2.PCIE_TX2_P1C17.1.PCIE_TX2_C_PC18.2.PCIE_TX2_N1C18.1.PCIE_TX2_C_NC19.2.PCIE_TX3_P1C19.1.PCIE_TX3_C_PC20.1.PCIE_TX3_C_NC20.2.PCIE_TX3_N1
U2connector_with_caps1
U3traces1
Cadence DesignerSI Layout
HFSS – BGA End
HFSS – Connector End
© 2011 ANSYS, Inc. May 11, 201250
Divide and Conquer
• Why divide the model if we have the technology/hardware to solve it end-to-end?
• Smaller models enable quicker investigation of:
• 3D Discontinuities
– Ground return paths
– Over/Under Etching
– Stackup
– Via Performance
Focus and Optimize
© 2011 ANSYS, Inc. May 11, 201251
HPC Productivity Enhancements
High Performance Computing (HPC)• HPC enables increased productivity and higher fidelity simulation - including more geometric
detail and larger systems.
• Using HPC you can make your engineering staff, and your product development process, more productive and efficient. Faster turnaround and larger models all mean better designs in less time.
Bigger
Faster
Higher Fidelity
© 2011 ANSYS, Inc. May 11, 201252
High Performance Computing (HPC) License
HPC Capabilities
Domain
Decomposition
(DDM)
Multi-ProcessingDistributed Solver
Technology
Mesh BasedHFSS FEM
Matrix BasedHFSS-IE
SpectralFrequency Sweep
HFSS
Q3D Extractor
Designer
SIwave
Maxwell
Q3DExtractorDC RL/AC RL/CG
HFSSDDM with IE Domains
HFSS-TransientDistributed Excitations
© 2011 ANSYS, Inc. May 11, 201253
Spectral Domain Decomposition Distributed Frequency Sweeps
#pts Clock Time Delta to Reference
Reference 301 34h 1x
DSO Interpolating
301 3h15m 10x
15xFaster
HFSS – BGA End
#pts Clock Time Delta to Reference
Reference 301 16h30m 1x
DSO Interpolating
301 1h47m 15x
10xFaster
HFSS – Connector End
© 2011 ANSYS, Inc. May 11, 201254
Distributed Solve Option (DSO) License
DSO Capabilities
Distributed Design Variations(Optimetrics)
HFSS
Q3D Extractor
Designer
Simplorer
Maxwell
…
© 2011 ANSYS, Inc. May 11, 201255
Design Variations – Study 8 VariationsDistributed Solve
#Variations Clock Time Delta to Reference
Reference 8 83h 1x
DSO Variations 8 11h 7.5x
6xFaster
#Variations Clock Time Delta to Reference
Reference 8 72h 1x
DSO Variations 8 13h 6x
7.5xFaster
HFSS – BGA End
HFSS – Connector End
© 2011 ANSYS, Inc. May 11, 201256
Hardware Utilization
• Hardware• 9 Dell R610 – 12 Cores, with 64GB RAM
• Windows Server 2008 R2
• Nodes
• 18 Nodes
– 2 Frequencies or Variations per Machine
– HPC for MP used to consume all cores on each Machine
© 2011 ANSYS, Inc. May 11, 201257
Parametric W-Element Models
• Distributed Solve for 2D Transmission Lines
• Same variables used for the transmission lines
© 2011 ANSYS, Inc. May 11, 201258
Parametric Variations for Virtual System
• Circuit Schematic for System
• A parametric sweep is used to characterize the system response to manufacturing variations
© 2011 ANSYS, Inc. May 11, 201259
Parametric Sweep Results
0.00 2.50 5.00 7.50 10.00 12.50 15.00 17.50 20.00F [GHz]
-60.00
-50.00
-40.00
-30.00
-20.00
-10.00
0.00
Y1
Circuit1XY Plot 4 ANSOFT
Curve InfodB(S(Port1,Port1))
LinearFrequency$brd_trace_w idth='3.2mil' $diel_thickness='3.6mil' $trace_etch='0'
dB(S(Port1,Port1))LinearFrequency$brd_trace_w idth='4mil' $diel_thickness='3.6mil' $trace_etch='0'
dB(S(Port1,Port1))LinearFrequency$brd_trace_w idth='3.2mil' $diel_thickness='4.6mil' $trace_etch='0'
dB(S(Port1,Port1))LinearFrequency$brd_trace_w idth='4mil' $diel_thickness='4.6mil' $trace_etch='0'
dB(S(Port1,Port1))LinearFrequency$brd_trace_w idth='3.2mil' $diel_thickness='3.6mil' $trace_etch='3'
dB(S(Port1,Port1))LinearFrequency$brd_trace_w idth='4mil' $diel_thickness='3.6mil' $trace_etch='3'
dB(S(Port1,Port1))LinearFrequency$brd_trace_w idth='3.2mil' $diel_thickness='4.6mil' $trace_etch='3'
dB(S(Port1,Port1))LinearFrequency$brd_trace_w idth='4mil' $diel_thickness='4.6mil' $trace_etch='3'
dB(S(Port1,Port3))LinearFrequency$brd_trace_w idth='3.2mil' $diel_thickness='3.6mil' $trace_etch='0'
dB(S(Port1,Port3))
© 2011 ANSYS, Inc. May 11, 201260
DSO
DesignXplorer Integration
Design Points
Solv
e
Response Surface
Results
De
sign
fo
r Si
x Si
gma
Ansoft Desktop DesignXplorer
Candidate Designs
Design for Manufacturing
Variable Sensitivity
© 2011 ANSYS, Inc. May 11, 201261
Conclusion
• HFSS
• Advanced Layout Capabilities– Improved Extraction
– Enhanced Frequency Sweep techniques
– New Broadband SPICE model generation
• Ansoft Designer
• Advanced Simulation Technology– IBIS AMI
– Full Channel for Compliance
• Productivity Enhancements
• HPC for Speed
• Distributed Solve for Design Space Characterization
