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Automatic Model Refinement of GmC Integrators for High-Level Simulations
of Continuous-Time Sigma-Delta Modulators
Michel VasilevskiHassan Aboushady, Marie-Minerve Louërat
Laboratory LIP6 University Pierre and Marie Curie, Paris 6, France
May 2009
M. Vasilevski Laboratory LIP6, University Paris6 2
1.Motivations
2.GmC Model Refinement
3.Characterization Flow
4.Results and Application
5.Conclusion
Outline
M. Vasilevski Laboratory LIP6, University Paris6 3
1.Motivations
2.GmC Model Refinement
3.Characterization Flow
4.Results and Application
5.Conclusion
Outline
M. Vasilevski Laboratory LIP6, University Paris6 4
Cir
cuit
-C
ircu
it-
Lev
elL
evel
Sys
tem
-S
yste
m-
Lev
elL
evel
Motivations : Analog Design FlowSystem-LevelSystem-LevelSpecificationsSpecifications
Modify Modify ParametersParameters
SimulationSimulation
PerformancePerformanceanalysisanalysis
OKOKCircuitCircuit
TopologyTopologyCircuit-LevelCircuit-Level
SpecificationsSpecifications
Circuit OKCircuit OK
Sized NetlistSized Netlist
Sizing : Manual Sizing : Manual
Modify Modify ParametersParameters
SimulationSimulation
PerformancePerformanceanalysisanalysis
Model Model RefinementRefinement
M. Vasilevski Laboratory LIP6, University Paris6 5
DAC
+- -
+TsAint
1/T
With Accurate Integrators ModelWith Ideal Integrators Model
Continuous-Time Modulator
TsAint
)...2p/s1)(1p/s1()...2z/s1)(1z/s1(
K)s(H
sT
A)s(H int
M. Vasilevski Laboratory LIP6, University Paris6 6
1.Motivations
2.GmC Model Refinement
3.Characterization Flow
4.Results and Application
5.Conclusion
Outline
M. Vasilevski Laboratory LIP6, University Paris6 7
GmC Model Refinement
BCV
DDV
SSV
ii iioi oi
C C
BIASV
CPV
sCGm
TsA
)s(H int
GmC idealTransfer Function:
M. Vasilevski Laboratory LIP6, University Paris6 8
GmC Integrator Design Results
I0 7.6 μA
Desired fT 1.36 MHz
Simulated fT 1.29 MHz
C 3.6 pF
ΣΔ Specifications
BW 200 kHz
OSR 64
Aint (Integrator Gain) 1/3
AΣΔ (Input Amplitude) -5dB
GmC Non-Idealities
CMOS Process:0.13 μm
M. Vasilevski Laboratory LIP6, University Paris6 9
Simplified GmC Model
DDV0I 0I 0I 0I 0I 0I
SSV
ii iioi oi
C Cgd
ds1
gd
ds1
ds
ds
C2
ggmz
C4C
g2p
g2
ggmK
1p/s11z/s1
K)s(H
Simplified models are not sufficiently accurate
[Zele,Allstot,JSSC’96][Zele,Allstot,JSSC’96]
M. Vasilevski Laboratory LIP6, University Paris6 10
DDV0I 0I 0I 0I 0I 0I
BCV
SSV
ii iioi oi
C C
Accurate Cascoded GmC Model
)2p/s1)(1p/s1()2z/s1)(1z/s1(
K)s(H
M. Vasilevski Laboratory LIP6, University Paris6 11
1.Motivations
2.GmC Model Refinement
3.Characterization Flow
4.Results and Application
5.Conclusion
Outline
M. Vasilevski Laboratory LIP6, University Paris6 12
Cir
cuit
-C
ircu
it-
Lev
elL
evel
Sys
tem
-S
yste
m-
Lev
elL
evel
Characterization Flow : Conventional methodSystem-Level System-Level
Specifications : SNR, BWSpecifications : SNR, BW
Modify Modify Aint, OSRAint, OSR
SimulationSimulation
SNR analysisSNR analysisscalingscaling
OKOKGmCGmC
TopologyTopologyGmC SpecificationsGmC Specifications
Sized NetlistSized Netlist
Sizing : Manual Sizing : Manual
Modify Modify ParametersParameters
SimulationSimulation
PerformancePerformanceanalysisanalysis
Circuit OKCircuit OK
GmC ModelGmC Model
Zeros/PolesZeros/PolesExtractionExtraction
)2p/s1)(1p/s1()2z/s1)(1z/s1(
K
TsAint
M. Vasilevski Laboratory LIP6, University Paris6 13
SystemC-AMS C++ based tool. Fixed step discrete-time System-Level simulator. Adapted to mixed analog-digital systems modeling. Ongoing standardization (extension SystemC).
CAIRO+: C++ based tool. Exact Bsim3v3 models are used for transistor sizing. Small-Signal parameters extraction. Suited for technology migration.
Full interoperability.
Characterization Flow : Full Automation
M. Vasilevski Laboratory LIP6, University Paris6 14
C+
C+
++C
AIR
O+
CA
IRO
+S
yste
mC
-S
yste
mC
-A
MS
AM
SC
AIR
OC
AIR
O++
Sys
tem
C-
Sys
tem
C-
AM
SA
MS
System-Level System-Level Specifications : SNR, BWSpecifications : SNR, BW
Modify Modify Aint, OSRAint, OSR
SimulationSimulation
SNR analysisSNR analysisscalingscaling
GmCGmCTopologyTopology
OKOK
GmC SpecificationsGmC Specifications
GmC ModelGmC Model
s
fA sint
Sized NetlistSized Netlist
Sizing : SynthesisSizing : Synthesis
Small-Signal ParametersSmall-Signal Parameters
Symbolic Symbolic expressionexpression
Zeros/PolesZeros/Poles
Characterization Flow : Proposed Method
)2p/s1)(1p/s1()2z/s1)(1z/s1(
K
M. Vasilevski Laboratory LIP6, University Paris6 15
Characterization Flow : Full Automation
Conventional method Proposed methodDifficult Interoperability System/Circuit Level: Manual interventions for transfer function characterization.
Fully compatible system to circuit level interface: C++ based tools, SystemC-AMS/CAIRO+.
Simulation-Aided transistor sizing: Time consuming.
« Knowledge » based sizing: Using CAIRO+ for accurate transistor sizing, suited for technology migration.
M. Vasilevski Laboratory LIP6, University Paris6 16
1.Motivations
2.GmC Model Refinement
3.Characterization Flow
4.Results and Application
5.Conclusion
Outline
M. Vasilevski Laboratory LIP6, University Paris6 17
2nd order CT in a 0.13 m CMOS
Specifications: SNR= 60 dB, OSR = 64, BW = 200 kHz
output Power Spectral DensityGmC Frequency Response
SNR=47dBSNR=47dB
SNR=68dBSNR=68dB
Transistors length: L1=10μm, L3=9 μm
M. Vasilevski Laboratory LIP6, University Paris6 18
SNR=68dBSNR=68dB
SNR=68dBSNR=68dB
2nd order CT in a 0.13 mm CMOS
Specifications: SNR= 60 dB, OSR = 64, BW = 200 kHz
output Power Spectral DensityGmC Frequency Response
Transistors length: L1=3 μm, L3=0.18 μm
M. Vasilevski Laboratory LIP6, University Paris6 19
Technology migration : 0.25 μm / 0.13 μm
0.25 μm 0.13 μm
BW=200kHz 68.2dB 68.4dB
BW=10MHz 52.1dB 67.3dB
Specifications: SNR= 60 dB, OSR = 64, BW = 200 kHz/10MHz
SNR=52dBSNR=52dB
SNR~68dBSNR~68dB
M. Vasilevski Laboratory LIP6, University Paris6 20
5 - Conclusion
• Automatic refinement of high-level system models based on:
• Exact symbolic expressions for small signal analysis
• Accurate BSIM3v3 transistor models
• Homogeneous Environment (C++):
• High-Level Simulation => SystemC-AMS
• Circuit synthesis and characterization => CAIRO+
• Proposed method illustrated on the GmC integrator of a 2nd order modulator.