Georgia Institute of Technology

School of Electrical and Computer Engineering

ECE 4006 Senior Design

IEEE 1394b:Technology for the Future

Luke Starnes Aparna Trimurty

Jeff Schlipf

Supervisor: Dr. Nan Marie Jokerst

This report is an extension to the background report submitted on the 29th of

January and explains a considerable number of design and implementation details that

have been determined since then. This paper presents a cursory technical description of

the project followed by details of the cards, evaluation kits, and equipment that are to be

used and finally, a budget and implementation plan.

1394b is a relatively new technology that has not yet been deployed in the

consumer market. However, this technology is believed to revolutionize digital

communications between audiovisual equipment, as we know it. Since the major

consumer market of AV equipment is the average household, cost and convenience are

important parameters to be considered during development. As 1394b Receiver group 7,

cost is indeed a major criterion in our design, and we deal with the transimpedance

amplifier (TIA) and the limiting amplifier of the Opto-electronics (OE) receiver module

seen in Figure 1. The OE module, besides being the focus of our design is the more

expensive component on the card. An optical receiver converts modulated light from the

optical fiber back into the original signal that was applied to the transmitter. Since the

amount of light in optical fibers is small, high gain amplifiers are needed. The TIA

converts the small current from the PIN diode to a voltage in the millivolt range and the

limiting amplifier provides post-amplification of low-level signals, which raises the

signal to the desired output level. The first step in our project plan was to replace the OE

module from a working TI 1394b card and getting it to function correctly outside the

card. If the OE part of the TI card is an Agilent Technologies HFBR-53D5 OE module

(as this certain module is slowly becoming a standard) then we would have to change the

single ended signals from the coaxial inputs to differential signals which is supposed to

remove noise and magnify the original signal by a factor of 2 for convenience. Since the

cards have not arrived yet, we have decided to start work on the second item of the

project plan, which involves MAXIM evaluation kits. MAX3266, which is the TIA, and

MAX3264, the limiting amp, are going to be tested in conjunction with the photo detector

to provide a working receiver module, which will then be interfaced with the transmitter

part to hopefully provide a fully functional 1394b implementation. The final part of the

design is to emulate the functionality of the MAXIM evaluation kits by designing a cost-

efficient evaluation kit for the RX module.

The MAX3266 chipset was used for the TIA. This is a Maxtor chip designed for

Gigabit Ethernet applications at 1.25 Gbps. Not only does it include a TIA, but also 4

other stages, as can be seen in Figure 2. These additional stages include a voltage

amplifier, an output buffer, an output filter, and a DC cancellation circuit.

Stage 1, the TIA, is a high gain amplifier that converts an input current from the

PD to an output voltage using the resistor RF setup in a shunt feedback network. The pair

of diodes is used to clamp any input currents above 1mA. This means that if the input

signal is above 1mA the receiver will not perform properly. Once the TIA has converted

the signal into a voltage it is sent to the voltage amplifier. This stage converts the single-

Figure 1. Optical Receiver Block Diagram

Figure 2. MAX3266 Functional Diagram

ended signal into a differential one. The output buffer at stage 3 is designed a 100

differential load (as seen in Figure 4) between OUT+ and OUT-. The two 50 resistors

between the output buffer and filter are used to reduce the signal by a factor of 2 through

voltage division. The output filter of stage 4 is simply a single pole low pass filter that is

used to limit the circuit’s bandwidth and improve noise performance. Finally, a DC

cancellation circuit is used to center the signal around zero. This is done through low

frequency feedback. The result can be seen in Figure 3. By grounding the Filter input

(pin 4) this circuit will be bypassed.

We will be using the MAX3266 evaluation kit, which greatly helps in using this

chip especially in how it will interface with the PD and the post-amp. The schematic for

this evaluation kit is shown in Figure 4. All of the regions outlined with colored boxes

will not be used for this project. The red box includes a circuit to emulate a PD output

signal and is useless since we will be interfacing with a real PD via J1. By removing R4

we will create an open circuit between the PD emulator and the real input. The region in

green makes up the calibration network. In blue are two circuits to be used if a PD wants

to be added directly to the board. Again, we are interfacing to a PD so this is not

necessary. The green and blue regions do not touch the part we are using so we can just

leave them be.

Figure 3. DC Cancellation Effect.

We will be hooking J1 straight to the PD provided by the OE group (G6). In

order for the OE group to determine the needed power of their detector it is very

important for us to determine the how weak the current sent to J1 can and still supply the

needed current to pin 3 of the 3266. This is important in allowing for an open eye to be

supplied to the limiting amplifier and thus to the TI 1394b PC card as well as to maintain

a BER < 10-12. To calculate this needed input, the sensitivity of the MAX3266 chip needs

to be evaluated.

The sensitivity is most influenced by the noise created by the opto-to-electrical

conversion performed by the PD and the TIA. However, it can be assumed that all noise

will be provided by the TIA. The sensitivity can be given as the Optical Modulation

Amplitude (OMA), which is the minimum peak-to-peak swing of the optical power

signal. In Figure 5 this would be P1-P0.

Figure 4. MAX3266 Evaluation Kit Schematic

The formula for this is given in Eq. 1 and has the units Wp-p.

(Eq. 1)

The inherent noise in the amplifier, in, is specified for the MAX3266 to be

200nArms according to the specification sheet for the chip. The Signal-to-Noise Ratio

(SNR), peak-to-peak signal to rms noise, is based on the needed for BER. For 1394b a

BER < 10-12 is needed, as according to the 1394b draft standard, equating to a SNR of

14.1. SNR. The typical transimpedance gain, ZTIA, of the MAX3266 is around 2.8k.

The absolute lowest input voltage needed to drive the limiting amplifier, Vth, is specified

for the MAX3264 to be 5mVp-p according to the MAX3264 specification sheet. The

responsivity, , is the conversion efficiency of the PD. For a conservative measure a

value of 0.5 A/W is used. Based on these values, OMAmin=9.2Wp-p.

It can be seen by looking back at Figure 1 that OMAmin is the needed power

presented to the front-end of the PD. In order to determine the needed current into the

TIM we can multiply the OMAmin by to give us 4.6Ap-p. Since it is always best to be

conservative, a value of 10Ap-p will be used from here on it. It can be shown in Figure 6

that this value seems to be a good threshold.

Figure 5. Optical Power

Figure 1 shows that this current going into the TIA is the same coming out of the PD;

however, this is not the case due to the circuitry at the front-end of MAX3266 on the

evaluation board. On this note it is important to determine the needed current into J1 on

the evaluation kit.

Figure 7 shows a simplified diagram of how the resistors lay out. In this figure,

IPD refers to the current emitted by PD and the output resistance of the PD is shown as

RPD. We know RPD to equal 50. Using current division we can determine IPD based

solely on Rin and ITIA, since everything else is known. This can be seen in Eq. 3.

(Eq. 2)

As stated before, the conservative estimation of ITIA = 10Ap-p will be used. We

can assume here that Rin = 200, although this will need to be verified with an Ohmmeter

during operation. Based on these values, the PD needs to deliver 340Ap-p. This value

may be a little high. In order to reduce IPD changes can be made to the circuit between

the PD and the chip.

The PD and the evaluation board will be connected via an SMA 50 cable. If we

can make the impedance seen looking into J1 also equal 50 then it will be a matched

load and there will be no reflection. In order to do this we need to remove R1, R2, and R3

from the evaluation board and replace them with a new R1 that when put in parallel with

Figure 6. Eye diagram for MAX3266

Figure 7. Simplified Diagram before board changes

Rin, resistance as seen looking into the MAX3266 chip, will equal 50. An equation for

R1 based on Rin is given in Eq. 3.

(Eq. 3)

A new diagram is shown in Figure 8 to relay this change in circuitry.

Again, using current division IPD can be found based solely on Rin and ITIA, since the only

other unknown, R1, is dependant only on Rin.

(Eq. 4)

Using the same values for ITIA and Rin as above the PD only needs to deliver 80Ap-p. The

OE groups believe that this value is entirely reasonable. A value of 200 for Rin would

cause R1 to be 66.7

Figure 9 shows the simplified MAX3266 evaluation kit schematic. It should be

noted that simply applying a jumper across JU2 would bypass the DC cancellation

circuit.

The function of the limiting amplifier, as the next stage of reception, is to create a

voltage output large enough for the TI PC board to use. The limiting amplifier being

Figure 8. Simplified Diagram after board changes

Figure 9. Simplified MAX3266 Evaluation Ket Schematic.

used for this project is the MAX3264, which was also designed for 1.25Gbps Gigabit

Ethernet optical reception systems. The amplifiers accept a wide range of input voltages

and provide constant-level output voltages with controlled edge speeds. The typical

operating circuit for the chip is seen in Figure 10.

Figure 10. Typical Limiting Amplifier Circuit

As can be seen above the limiting amplifier receives its input from the receiver

the MAX3266 in this case. In taking a closer look at the picture it looks like a typical

operational amplifier, but now we will probe deeper into exactly what is going on within

the chip. This detailed idea can be seen below in Figure 11.

Figure 11. Detailed look at Limiting Amplifier Chip

In looking at the figure above, we see that the input is taken from the

transimpedance amplifier through an input buffer and drives this multistage limiting

amplifier and an RMS power detection circuit. In one stage the input passes through the

offset correction and low pass filtering portion of the chip. The capacitor connected

between CAZ1 and CAZ2 will determine the time constant of the offset-correction

circuit. The offset correction circuit requires an average data-input mark density of 50%

to prevent an increase in duty cycle distortion and to ensure low deterministic jitter. In

other words, this stage will reduce phase shift between the input and output of the chip.

The chip can also select the gain stage. The chip provides approximately 55db of

gain. This large gain makes the amplifier susceptible to small DC offsets in the input

signal. DC offsets as low as 1mV will reduce the accuracy of the power detection circuit

and may cause deterministic jitter. This low-frequency feedback loop is integrated into

the limiting amplifier to reduce input offset, typical to less than 100V. Simply put, this

portion of the chip helps offset the big gain that the chip produces to make the signal as

optimal as possible.

Another stage of the chip is the RMS power detector with loss-of-signal (LOS)

indicator. The power detector here looks at the signal from the input buffer and compares

it to a threshold set by the TH resistor, which can be 2.5k, 7k or 20k depending on

if you want low, medium or high LOS levels. The signal-detect information is provided

to the LOS outputs, which are internally terminated with a 16k pull up resistors (RLOS).

The LOS outputs meet TTL (Transistor-Transistor Logic) voltage specifics when loaded

with a resistor = 4.7k.

The output buffer of the chip produces a limited output signal. The MAX3264

chip produces a CML (Current Mode Logic) output. This may present a problem. The TI

1394b card is assumingly designed for the PECL (Positive Emitter Coupled Logic) output

of the Agilent OE module. So if it is our intention to remove this module and replace it

with one of our own, we must ask ourselves the question of whether or not CML can

drive a PECL input. It seems that it could be done but through the process of ac-coupling.

Several examples of ac-coupling between CML and LVPECL or low voltage PECL

(when the power supply is 3.3V) and how to do so can be found at our reference page at

number 6. Since we do not have the card and we are assuming that the card is designed

for a PECL input, this process must be postponed until we know how the TI 1394b card

is designed. Of course, if the case does arrive that the 1394b card is expecting a PECL

input and cannot be sidestepped we can chose one of two solutions; first and most

probable is to design for ac-coupling between the CML driver and PECL receiver or as a

second option we can look into using the MAX3268 Limiting Amplifier which is

designed for a PECL output rather than the MAX3254 CML output.

The Limiting amplifier circuit provides high tolerance to impedance mismatches

and inductive connectors. The output buffer also has a control module with two pins for

Level and Squelch. The output current can be set to two levels. When the Level pin is left

unconnected, the output current is approximately 16mA, while connecting Level to

ground sets the output current to approximately 20mA. The Level pin helps the user

control current being outputted by the chip. The Squelch pin is activated when connected

to TTL-high level or connected to Vcc. What this function does is hold out+ and out- at a

static voltage whenever the input signal power drops below the LOS threshold. The

Squelch operation is described below in Figure 9.

Figure 9. Squelch Characteristics

To test this chip we will be using the MAX3264 evaluation kit, which will

evaluate our MAX3264 chip. The kit will allow easy programming of the LOS signal

threshold and provide layout options for alternate termination configurations. The

evaluation kit will also allow for a user supplied preamplifier and photodiode pair. This is

the basis for our design project.

As can be seen above, the Transimpedance Preamplifiers and the Limiting

Amplifier play vital roles in a Gigabit Ethernet application. In order to build technology

like this a certain understanding of how the components work is necessary. Discussed

above are the Maxim chips that will be implemented and the kits that will be used to test

them. These components along with other minor pieces such as power supplies, SMA

connectors, and cable will be used eventually to replace the matching components on a

working 1394b Ethernet Card to see what other options can be used in the OE module for

the experimental technology. A successful 1394 test bed depends on a number of factors

that involves scheduling a reasonable timeline for the three parts of the project; ordering

cost-efficient parts and, if possible, sample parts for trial and error purposes; eliminating

sources of error such as improper wiring, static effects and soldering defects.

Reference Page

1) http://pdfserv.maxim-ic.com/arpdf/AppNotes/4hfan300x.pdf

2) http://pdfserv.maxim-ic.com/arpdf/MAX3264-MAX3765.pdf

3) http://pdfserv.maxim-ic.com/arpdf/MAX3264EVKIT-MAX3269EVKIT.pdf

4) http://pdfserv.maxim-ic.com/arpdf/MAX3266-MAX3267.pdf

5) http://pdfserv.maxim-ic.com/arpdf/MAX3266EVKIT-MAX3267EVKIT.pdf

6) http://www.planetanalog.com/story/signalprocessing/OEG20000705S0001