Application of through-silicon-via (TSV) technology to making of high-resolution CMOS image sensors

Name: Qian YUStudent ID: 20221416

Outline

Why TSV?

TSV process?

Application in image sensors?

Why a TSV?

Scaling conventional wires

More scattering at wire surfaces

Resistivity increases as cross-sectional dimensions scale down

Interconnect length dose not scale down with transistors 3D is can effective way to scale

W. Steinhögl, et al., “Size dependent resistivity of metallic wires in the mesoscopic range,” Physical Rev. B vol. 66, 075414 (2002)

Size Effects due to Electron

Scattering

Surface and gain

boundariesGain

boundaries

surface

TSV

Better electrical performanceLower power consumption Wider data widthHigher densitySmaller form factor Lighter weight

John H. Lau, “Overview and Outlook of Three-Dimensional Integrated Circuit Packaging, Three-Dimensional Si Integration, and Three-Dimensional Integrated Circuit Integration” Electronic Packaging, Vol.136, 040801 (2014)

1)

2)

Why TSV?

Small Form factorFaster interconnects & reduced power consumptionHeterogenous Integration & high density integration

From IMEC 2011

3D integration key technology

Ko, C. T., and Chen, K. N., “Wafer-Level Bonding/Stacking Technology for 3D Integration,” Microelectron. Reliab., 50(4), pp. 481–488 (2010).

An increasing number of companies, such as IBM, Xilinx, Samsung and Bosch, are taking 3D through-silicon-via (TSV) technology to the commercialization phase

The global 3D TSV semiconductors packaging, assembly and test market will reach the $8B business value by 2017

From Yole Development Company, 2012

ITRI (Taiwan) tapes our 3D-IC stack with TSVs using Cadence design system in 2012

http://www.cadence.com/cadence/newsroom/press_releases/Pages/pr.aspx?xml=101512_ITRI

TSV trend

Categories: • Via first/FEOL (front-end-of-line):

Bumping

Si-substrate

IC

Clean Wafer

Si-substrate

TSV making and filling

Si-substrate

Wafer process

Si-substrate

IC

Wafer thinning

• Via last/BEOL (Back-end-of-line):

Si-substrate Si-substrate

IC

Si-substrate Si-substrate

IC

TSV makingWafer process

Si-substrate Si-substrate

IC

Wafer thinning

Metal plating

Si-substrate

IC

Bumping

Poly-Si

Fabricate vias in blank wafer Fabricate CMOS circuitry Grind to thickness ， Used in high brightness LED package

Fabricate CMOS circuitry Fabricate vias in blank waferGrind to thickness ， Thermal budget limitation

Souriau, J. C., Sillon, N., Brun, J., Boutry, H., Hilt, T., Henry, D., and Poupon, G., 2011, “System-on-Wafer: 2D and 3D Technologies for Heterogeneous Systems,” IEEE Trans. Compon. Packag. Manuf. Technol., 1(6), pp. 813–824.

TSV process

PR

Si-substrate

Handle wafer

Inter-player

Adhesive

Passivation layer

Etching Sputter

SiO2

Ta/TaN/Au

Sputter

CVD

Conductive paste

CMP

Bonding pad

Backside lithography

Deep Si etching

SiO2 etching

Side wall insulation

Conductive material filling (Cu)

TSV process flow• Etching: make high aspect ratio via.• Sputtering: insulation material between TSV and substrate; seed layer.• CVD: conductive material (Poly-Si, Cu, W) deposition into the via.• CMP: Remove extra material deposited by CVD; wafer thinning.

TSV application in image sensors for smart imaging systems

2 imager roadmaps with different methods:

Traditional: scaling to smaller pixels:- Equal chip size- Higher resolution

-lower sensitivity

Integration/ packaging method:-3D integration with backside illuminated image sensor-Enables advanced imaging systems

Advantage of TSV technology in image sensor

Main advantage is to reduce the size of the image sensors

Advantages:Smaller footprintReduced capacitance leads to faster & lower power interconnectButtability with minimal area loss

Applications:Consumer imagersLarge area tiled imagersendoscopes

Makoto Motoyoshi, “ Through-silicon-via,” Proceedings of the IEEE , Vol. 97, No. 1, January 2009.

System architecture of an imaging system on a chip-stack

Stacking of multiple layers:Detection layer + Read out IC layers- Example: passive photodetector layer + analog Readout IC + digital image processor

Advantages:General: optimization of CMOS technology for different layers

Imager system: -Vertical parallel readout chain allows higher speed-Larger area per pixel allows complex electronics per pixel-Low capacitance interconnect to digital image processor allows high speed and low power

From IMEC 2011

The top layer of Sony’s stacked images sensor is a BSI sense layer stacked on the readout/image processing. Large TSVs are used to create vertical interconnects to the peripheral electronics. (Image courtesy of imec and Sony)

One stacking package of back-illuminated (BI) CMOS image sensor by SONY company

Shunichi Sukegawa, “A 1/4-inch 8Mpixel Back-Illuminated Stacked CMOS Image Sensor” IEEE International solid-state Ciruits Conference, 978-1, 2013