2008/10/9

3DIC Wafer Level Packaging forCMOS Sensor and Logic IC’s

Wei-Ming Chen, Ph.D.

Vice President, R&D, Xintec Inc.

WMC, Xintec R&D 2

What does a front-end guy do in the packaging world?

WMC, Xintec R&D 3

Outline

� More than Moore� Challenge of Moore’s law

� Arrival of 3DIC era

� Existing techniques that can be extended to 3DIC� Sensor package

� Image sensor (light sensor)

� Voice sensor (MEMS)

� Critical techniques

� Logic IC package� Fan-in WLCSP

� Fan-out WLCSP

� Critical techniques

� The true 3DIC era: Heterogeneous integration� Examples: Image sensor and logic devices

� Value chain will change, but who can be the winner?

� Summary

WMC, Xintec R&D 4

Moore’s law and more than Moore

� Advancement in package world has been lagging behind IC shrink pace.� Further shrinking the IC device might not help the overall miniaturization if

packaging or system level integration does not improve

Source: R. Tummala, Georgia Tech

Source: Prismark

IC’s (not including package) only account for a small portion of the overall board space

WMC, Xintec R&D 5

Limitation of Moore’s law in Memory

� Samsung predicts that NAND Flash memory cost won’t come down past 64Gbit by conventional shrink path

� Samsung believes that 3DIC technology will make it possible to maintain the current pace of cost reduction

Source: Yole

WMC, Xintec R&D 6

Facing both technical and financial following Moore’s law

� Development cost CAGR is 12.5% (2004-2010), while Semiconductor revenue growth CAGR (2004-2010) is only 6%**

� Product design cost (>$ 1B below 45nm ) and fab cost are both getting higher (> $2B below 45nm)

� Fewer and fewer players (product company or wafer Fab’s) can follow the shrink path to next node of technology

Sales**

Technology node

R&D cost in $B*

1.2

1.0

0.8

0

0.6

0.4

0.2

Technology node

Fab cost in $B*

•source: Neugold, ATMI** souce; Bailey, IBM

WMC, Xintec R&D 7

What do people do during the transition to 3DIC?

� The IC world is facing more uncertainty in R&D return due to higher development and design cost following the IC Moore’s law

� Package cost per unit will be increased from 15% (2005) to 20% (2012)*

� Investment in the package technology seems to be rewarding, however going from in a 40% gross margin business (wafer) to a 20% gross margin world (packaging) needs justification� IDM and wafer fab’s will extend their facility for some Via-Last approaches

but will eventually go for the Via-First approach (Via size 1-10um)

� The package houses see the opportunity, but new products require them to equip themselves more like a Si fab than before� Package houses continue as mush as possible the exiting packaging

solutions (MCP, PiP, POP, stacked die, EPS/EDS) then eventually go to Via-last TSV (via size 10-100um)

Traditional SiP (wirebond, substrate) -> Via Last 3DIC -> Via First 3DIC

*Source: Jim Walker, Gartner Dataquest

WMC, Xintec R&D 8

3DIC, TSV, and wafer level process

� The 1st ingredient of 3DIC is “TSV”

� TSV is like an elevator inside a modern building. The exiting solutions: wirebond stacked die, T-contact, etc are like staircases built outside a building

� TSV provides better performance and smaller form factors. The wafer level packaging process further gives a lower cost per unit

Wirebond stacked die TSV stacked die

Current 3DIC solution Future 3DIC solution

WMC, Xintec R&D 9

Source: Yole

� The industry will gain its 3DIC product experience fist from Memory and CMOS image sensors

� The IDM’s are the earliest to adopt TSV in production

WMC, Xintec R&D 10

The world of CMOS image sensor packaging

WMC, Xintec R&D 11

Chip On Board (COB) packaging

� Form factor is large� Require class 10 clean room environment, because die is

not protected during packaging.

� Yield is lower for finer pixel products

Source: Tessera

WMC, Xintec R&D 12

COB vs. WLP Module Yield

� Particle contamination decreases yield of COB in higher resolution products� Wafer level package (WLP) yield is not impacted by finer pixel

Source: Tessera

WMC, Xintec R&D 13

CIS Wafer Level Packaging (WLP)(T-contact)

� CIS WLP is a particle free packing process, because the whole wafer is encapsulated by glass at the very beginning

� Smaller form factor in x, y ,and z dimensions� Greater than 150um scribe line is needed for T-contact formation� Standard SMT assembly

T-contact

WMC, Xintec R&D 14

Source: Beyne, IMEC

CIS Wafer Level Packaging (WLP)(TSV, Toshiba example)

� TSV eliminates scribe line penalty that occurred in T-contact technology

� Area contact (TSV) instead of side wall contact (T-contact) also improves reliability

� The TSV techniques used in CIS can be extended to Via-last 3DIC integration

WMC, Xintec R&D 15

The world of MEMS packaging

WMC, Xintec R&D 16

Traditional MEMS microphone package

� Use wire bond to connect MEMS diaphragm and active circuit. Form factor is large.

� Die size is small. Non-wafer-level process cost is higher per unit.

Source: Mark Bachman

WMC, Xintec R&D 17

Traditional MEMS hermetic sealing

� Need a hermetic cap to protect the MEMS part from damage

� Use wire bond and metal pin or lead frame for electrical connection to PCB

� Non wafer level process is time consuming and has large package size

Source: kyocera

Source: NovasensorMetal pin

Lead frame

Cap

WMC, Xintec R&D 18

Wafer-level MEMS packaging

Source: IMEC

� Wafer level bonding hermetic sealing results lower cost per unit� Use TSV, backside RDL and solder bumps for electrical connection to PCB.� Smaller package size and lower cost

Wafer bonding MEMS

TSVSolder bump

RDL

WMC, Xintec R&D 19

CIS/MEMS packaging techniques that can be extended to 3DIC integration

� Wafer to wafer bonding

(Hermetic seal)

� Wafer thinning

� TSV

� RDL

� Bumping

� Wafer dicing

Glass wafer

RDLSolder bump

Cavity

CIS

Cavity

Cap wafer

TSVSolder bump

MEMS

Source: IMEC

WMC, Xintec R&D 20

The world of logic device (PM, BT, Amplifier, etc.)

wafer level CSP

WMC, Xintec R&D 21

Wafer level package options

� Fan-in structure is suitable for die with low IO counts (<100) and low IO density (<6/mm2)

� Fan-out structure is suitable for die with high IO counts (>100) and high IO density (>6/mm2)

PCB

ChipChip

Filler layer

Fan-in WLCSPFan-out WLCSP

FBGA

WMC, Xintec R&D 22

Fan-in WLCSP

Source: ASE

RDL

Bumping

� Use RDL process to enlarge pad pitch (45um to 400-800um).

� Solder bump size can be enlarged from 100um to 300-500um. The die can be assembled directly on PCB without interposer.

WMC, Xintec R&D 23

FSL’s wafer level packaging (Fan-out)

Source: FSL, ECTC 2007

Integratedpassives

Temporarybonding

� Temporary bonding was used for die placement� Filler material (encapsulation) was used to fill up the space between dies� RDL and BGA balls were formed both on top of dies and filler areas� An effective way to bridge the high IO density on chip(~10/mm2) to low IO density in the package (~5/mm2)

Chip area

WMC, Xintec R&D 24

� Connecting dies with RDL

� Die to wafer bonding and encapsulating dies to enlarge the area available for

bumping by filler materials

� Forming IPD (integrated passives

device)

WLCSP techniques that can be extended to 3DIC integration

Die

RDLSolder bump

Two RDL layers to form an inductor

Two RDL layers to form a capacitor

Source: IZM

Source: FSL

WMC, Xintec R&D 25

Heterogeneous Integration

WMC, Xintec R&D 26

Advantages of heterogeneous Integration

� Chips from different technologies can be connected

through packaging

� (0.18um Analog/RF, 0.35um MEMS, 90nm logic,

etc)

� SIP provides a more flexible, cost saving, and faster

time-to-market solution than SOC

� Higher level of integration at system level by package

helps to accelerate the overall miniaturization

� TSV based 3DIC gives possibility of many new

product design (e.g. Si interposer)

Source: Synopsys, Semcon Taiwan’08

WMC, Xintec R&D 27

CIS packaging trend

� By adding micro-bump and Si interposer, CIS with TSV can be extended to a 3DIC module.

Source: EMC-3D

Micro-bump

WMC, Xintec R&D 28

Logic IC packaging trend

� The trend is: smaller die, smaller package size, higher density of IO, more and more multiple chip module

� Wafer level process is the answer to smaller size, higher performance, and lower cost

Wirebond stacked die

TSV stacked die

Fan-out WLCSP

Integration density increased

Package size reduced

Wafer level process

Fan-in WLCSP

GSM i.275edgeradio in a chip

Freescale

WMC, Xintec R&D 29

3DIC development trend

Source: IMEC

IC foundry technology

Traditional interconnect packaging technology

Wafer level packaging(via last)

� Via last (3D-WLP) will happen first because of time to market and flexibility, but with a trend toward via first (3D-SIC) later due to smaller form factor and performance

(via first)

WMC, Xintec R&D 30

3D stacking era

Inte

gra

tio

n d

en

sit

y

IC package trend

City building trend

� In human’s world, when population increases, 2D single function houses become 3D multiple function skyscrapers

� In Chip’s world, single chips become 3D multiple chip stacks. New opportunities rise

WMC, Xintec R&D 31

From Front-end to back-end & vice versa

� The 3DIC era opens up new opportunity not only for package

houses and OSAT’s but also for IDM and Si foundry

� The front-end equipment and material also see the opportunities in the 3DIC

� Front end IC manufacturers, equipment and material suppliers might have dealt with smaller dimension and higher

aspect ratio, but need to deal with the lower cost and lower process temperature requirements in 3DIC package

� Back end players need to develop FEOL-like wafer level processing techniques, but maintain low cost

WMC, Xintec R&D 32

Who is the best builder?

3D IC-TSVThin chipChip stackingRDL……

IC fab (IDM/Foundry)-DRIECVDHigh AR PVDStepper……

MEMS fab-DRIESpray coaterAlignerWafer bonder……

Substrate-LaserElectroplaterPolymer materials……

Package house-Wafer thinningPVDElectroplaterDie bonderTesting……

WMC, Xintec R&D 33

Who owns more 3DIC techniques now?

� 3D IC will be a wafer level package process and need to adopt a lot of techniques that are used in CMOS technology. IDM and foundry might be able to find 3DIC a good market to revamp their matured technology and old facility.

WMC, Xintec R&D 34

Will the added value distribution shift?

SystemDesign

IC DesignAssembly

& TestPackageHouse

Si Fab

� There is no doubt that package value will be increased. However, will Si fab(IDM/Foundry), package house, or OSAT gain more value in the 3DIC reshuffling?

Current

Scenario A

Scenario B

WMC, Xintec R&D 35

Summary

� Continue to follow Moore’s law by conventional path will be more challenging and requiring huge capital

� Package provides another path of “more than Moore”. The investment is relatively smaller

� Adoption of TSV opens up a new era of 3DIC integration, and a possible supply chain value change to all players

� 3DIC will be a wafer level package process therefore IDM and foundry might have some advantage in process experience and fab facility.

� However on the low cost and materials part package houses and OSAT might have more advantages in building the 3DIC

� IDM, MEMS manufacturer, wafer foundry, package houses, and OSAT all poised to take on more values in the new era, but at the same time new investment and learning will be needed for all players.

� Image sensor and memory will be the first two segments to adopt TSV. Some essential techniques are already practiced in CIS, MEMS andWLCSP. It is a matter of integrating these techniques to win the 3DIC opportunity

WMC, Xintec R&D 36

Thank you!

A professional company in wafer level package manufacturing servicewww.xintec.com.tw