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The Pennsylvania State University
The Graduate School
Department of Electrical Engineering
ANALYSIS OF DC-TO-DC CONVERTERS
AS DISCRETE-TIME PIECEWISE AFFINE SYSTEMS
A Thesis in
Electrical Engineering
by
Zhengbang Wang
2014 Zhengbang Wang
Submitted in Partial Fulfillment
of the Requirements
for the Degree of
Master of Science
August 2014
The thesis of Zhengbang Wang was reviewed and approved* by the following:
Jeffrey Mayer
Associate Professor of Electrical Engineering
Thesis Advisor
Constantino Lagoa
Professor of Electrical Engineering
Kultegin Aydin
Professor of Electrical Engineering and Department Head
*Signatures are on file in the Graduate School
III
ABSTRACT
A boost dc-to-dc power converter has been among the application examples in several
recent publications on stability analysis of piecewise affine systems (PAS). While those
publications point to a great potential for PAS modeling and stability analysis of switch-mode
power converters, the examples use a PAS model that is based on an incomplete generalized state
space (GSS) model of the boost converter (here GSS refers to a piecewise-LTI state space model
and an accompanying set of state-, input-, and time-dependent switching surfaces that determine
the LTI model at any instant). In particular, the GSS model does not include the converter
topology associated with discontinuous conduction mode (DCM) wherein the diode blocks
reverse current while the switch is also off. The purpose of this thesis project is to re-examine the
application of PAS modeling and stability analysis to power converters. To this end, the
converter modeling in the publications has been reproduced and then augmented to account for
DCM. The state-space partitioning algorithm central to PAS stability analysis has also been
impended in MATLAB and applied to the original and augmented models.
Key words: piecewise affine system, stability analysis, state-space partition
IV
TABLE OF CONTENTS
List of Figures .......................................................................................................................... VI
Acknowledgements .................................................................................................................. IX
Chapter 1 Introduction ............................................................................................................. 1
1.1 Motivation .................................................................................................................. 1 1.2 Contribution ............................................................................................................... 2 1.3 Organization ............................................................................................................... 3
Chapter 2 Conventional Models of dc-to-dc Converters ......................................................... 4
2.1 Single–Switch dc-to-dc Converters ............................................................................ 4 2.1.1 Step-Down (Buck) Converter .......................................................................... 4 2.1.2 Step-Up (Boost) Converter .............................................................................. 5 2.1.3 Buck-Boost Converter ..................................................................................... 6
2.2 Periodic Steady State Analysis ................................................................................... 6 2.2.1 Continuous Conduction Mode ........................................................................ 7 2.2.2 Discontinuous Conduction Mode .................................................................... 8
2.3 Generalized State Space Modeling ............................................................................ 8 2.3.1 Form of Generalized State Space Model ......................................................... 9 2.3.2 Continuous Conduction Mode ........................................................................ 9 Example 1: ............................................................................................................... 11 2.3.3 Discontinuous Conduction Mode .................................................................... 13 Example 2: ............................................................................................................... 14
2.4 Small Signal Modeling ............................................................................................... 15 2.4.1 Analog Control of dc-to-dc Converters ........................................................... 15 2.4.2 State Space Averaging .................................................................................... 17 2.4.3 Circuit Averaging ............................................................................................ 18 2.4.4 Controller Design ............................................................................................ 19 Example 3: ............................................................................................................... 19
Chapter 3 Discrete-Time Piecewise Affine Systems ............................................................... 24
3.1 Discrete-Time Piecewise Affine Systems Modeling ................................................. 24 3.1.1 Discrete-Time Piecewise Affine System Representation ................................ 24 3.1.2 Discrete-Time Piecewise Affine System Model Construction ........................ 25
3.2 Definition of State Space Partition ............................................................................. 27 3.3 Algorithm to Obtain a State Space Partition .............................................................. 28
3.3.1 State Space Partition without Disturbance ...................................................... 28 Example 4: ............................................................................................................... 29 3.3.2 State Space Partition with Disturbance ........................................................... 32 Example 5: ............................................................................................................... 32
Chapter 4 Piecewise Affine System Models of dc-to-dc Converters ....................................... 35
4.1 Derivation of Discrete-Time System Model .............................................................. 35
V
4.1.1 Continuous-Conduction Mode ........................................................................ 36 4.1.2 Discontinuous-Conduction Mode.................................................................... 37
4.2 Linearization of Discrete-Time Nonlinear Model ...................................................... 39 4.2.1 Jacobian Matrix ............................................................................................... 39 4.2.2 Linearization of Discrete-Time Equivalent System ........................................ 40
4.3 Piecewise Affine System Model of Boost Converter ................................................. 41 4.3.1 Piecewise Affine Model with Incomplete Diode Model ................................. 41 4.3.2 Piecewise Affine System Model with Complete Diode Model ....................... 43
4.4 Piecewise Affine System Modeling Guidelines ......................................................... 45 4.4.1 Selection of Domains ...................................................................................... 45 4.4.2 Selection of Operating Points .......................................................................... 46
4.5 Piecewise Affine System Controller Design .............................................................. 46 Example 6: ............................................................................................................... 48
4.6 State Space Partition for Boost Converter with Incomplete Diode Model ................ 52 4.7 State Space Partition for Boost Converter with Complete Diode Model ................... 55
4.8 State Space Partition for Boost Converter with Disturbance ..................................... 59
4.9 Piecewise Affine System Analysis on Boost Converter Operating in DCM ............. 63
Chapter 5 Conclusion ............................................................................................................... 70
5.1 Summary .................................................................................................................... 70 5.2 Future Work ............................................................................................................... 70
Appendix .................................................................................................................................. 71
Test file ..................................................................................................................... 71 partition_state_space ................................................................................................ 74 partition_piecewise_affine_system_with_disturbance ............................................. 76 inequality_function_solver_R2_bounded ................................................................ 80 simplify_vertex ........................................................................................................ 81 polygon2inequalities ................................................................................................ 83 minterms_finder ....................................................................................................... 84 find_complementary................................................................................................. 89 M_generator ............................................................................................................. 92 plot_figure ................................................................................................................ 94
VI
LIST OF FIGURES Figure 2-1. Schematic diagram of the buck converter. ............................................................... 5
Figure 2-2. Schematic diagram of the boost converter. .............................................................. 6
Figure 2-3. Schematic diagram of the buck-boost converter. ..................................................... 6
Figure 2-4. Typically inductor current waveform for a converter operating in CCM. ............... 7
Figure 2-5. Typically inductor current waveform for a boost converter operating in DCM. ...... 8
Figure 2-6. Circuit topology of boost converter while switch is on. ........................................... 9
Figure 2-7. .... Circuit topology of boost converter while switch is off and converter is operating in
CCM. ..................................................................................................................................... 10
Figure 2-8. Transient response of boost converter using GSSM without diode reverse current
blocking. ............................................................................................................................... 12
Figure 2-9. Transient response of boost converter using GSSM without diode reverse current
blocking relative to steady state. ............................................................................................ 12
Figure 2-10. Circuit topology for boost converter while switch is off and the converter is
operating in DCM. ................................................................................................................. 13
Figure 2-11. Transient response of GSSM with diode modeled completely. ............................. 14
Figure 2-12. Transient response of GSSM with diode modeled properly relative to steady state
15
Figure 2-13. Schematic of boost dc-to-dc converter with voltage regulation. .......................... 16
Figure 2-14. PWM controller. (a) Block diagram showing compensator amplifier and
comparator. (b) Comparator signals. ...................................................................................... 17
Figure 2-15. Bode plot of small signal model of closed-loop boost converter system. ............ 20
Figure 2-16. Step response of small signal model of closed-loop boost converter system. ...... 21
Figure 2-17. Step response of discrete time small signal model of closed-loop boost converter
system. 21
VII
Figure 2-18. Transient response of small signal modeling digital PWM boost converter. ....... 22
Figure 2-19. Transient response relative to steady state operating point. ................................. 22
Figure 2-20. PWM duty ratio response. .................................................................................... 23
Figure 3-1. State space partitions 𝓓𝟎 and 𝓓𝟏. ....................................................................... 31
Figure 3-2. State-Space Partitions 𝓓𝟑. ................................................................................... 31
Figure 3-3. Polytope of disturbance W for Example 5. ........................................................... 33
Figure 3-4. 𝓓𝟎 and 𝑫𝟏 for Example 5. ................................................................................. 34
Figure 3-5. 𝓓𝟏 for Example 5. .............................................................................................. 34
Figure 4-1. Schematic of boost converter when operating in DCM. (a) Switch-on interval. (b)
Switch-off interval. (c) Switch-off and diode-off interval. .................................................... 37
Figure 4-2. Transient response of piecewise affine model without diode reverse current
blocking. 42
Figure 4-3. Transient response of piecewise affine model without diode reverse current
blocking relative to steady state. (b) Enlarged view around steady state operating point. .... 42
Figure 4-4. Transient response of piecewise affine model with complete diode model. .......... 44
Figure 4-5. (a) Transient response of piecewise affine modeling with diode modeled properly
relative to steady state (b) Enlarged view of domain 3. ......................................................... 44
Figure 4-6. State space switching sequence for PAS model with complete diode model. ............ 45
Figure 4-7. Operating points for linearization. .......................................................................... 49
Figure 4-8. Transient response of piecewise affine system model. ........................................... 50
Figure 4-9. Transient response of boost converter generalized state space model with complete
diode model. ........................................................................................................................... 51
Figure 4-10. Transient response of piecewise affine system model............................................ 51
Figure 4-11. Transient response of boost converter generalized state space model with complete
diode model. ........................................................................................................................... 52
VIII
Figure 4-12. State space partitions of boost converter CCM. ............................................. 54
Figure 4-13. State space partitions of piecewise affine system model with complete diode
model. 58
Figure 4-14. Transient simulation of piecewise affine system model and generalized state space
model. 59
Figure 4-15. Voltage error and current error between piecewise affine system model and
generalized state space model. ............................................................................................... 60
Figure 4-16. Several partitions and refinements of piecewise affine system. ................................ 62
Figure 4-17. Transient response of GSSM with complete diode model operating in DCM. ......... 63
Figure 4-18. Steady state response of GSSM with complete diode model operating on DCM. .... 64
Figure 4-19. Transient response of piecewise affine system model with complete diode
model. 65
Figure 4-20. Transient response of piecewise affine system model with diode modeled
completely relative to steady state. ........................................................................................ 66
Figure 4-21. State space partitions of boost converter DCM. ............................................. 69
IX
ACKNOWLEDGEMENTS
I would like to thank Dr. Jeffrey Mayer who have helped and inspired me through the
duration of my studies at the Pennsylvania State University.
1
Chapter 1
Introduction
1.1 Motivation
Switch-mode power converters are widely used in consumer products as well as in
industrial, medical, and aerospace equipment due to their high efficiency, low volume and
weight, fast dynamic response, and low cost when compared to other methods for converting
voltage and current levels between source networks and loads [1]. In the future they are also
expected to be used extensively in electric vehicles and solar energy systems [2].
Although switch-mode power converters are inherently non-linear, hybrid dynamical
systems due to the switching process, power converter control design has relied mainly on well-
established methods from continuous-time linear systems theory, particularly s-domain transfer
functions. To apply these analog control methods, small-signal models of a converter are derived
using specialized linearization techniques such as state space averaging [3] or switch averaging
[4]. In recent years, digital control of power converters has been of growing interest, because it
offers greater programmability and robustness for the converter system, and because automated
design tools tend to neutralize an important advantage of the conventional methods, namely the
facility with which most electrical engineers can applying them [5].
The discrete-time models of power converters required for digital control design are
usually derived in a two-step process. First, the converter is modeled as a set of continuous-time
piecewise LTI systems with state-, input-, and time-dependent switching functions that determine
whether a particular LTI model is appropriate or there should be a transition to a different LTI
2
model. Second, state-transition matrices are used to map the state at the beginning of a switching
period to the state at the end of the switching period. Owing to the form of the state transition
matrices and the expressions for the switching functions, the resulting discrete-time model is non-
linear.
A piecewise affine system (PAS) model has been proposed as a means to handle the non-
linear discrete-time model of power converters [6][7]. A PAS is a kind of hybrid dynamical
system [8][9], as it is comprised of difference equations and discrete events. One approach to
stability analysis for a PAS involves partitioning the state and input spaces into a finite number of
non-overlapping convex polytopes, each of which corresponds to the domain for a linear or affine
difference equation [9][10]. Piecewise affine system (PAS) can be used to simplify the
simulation process of nonlinear systems by switching among several linearized subsystems for
different operating regions [11]. Therefore, a simpler controller can be applied for the regulation
of nonlinear system [12].
1.2 Contribution
We have reproduced the piecewise affine system modeling and stability analysis for a
boost converter in [7]. In so doing, we have identified a limitation of the model in [7] and in an
earlier paper [6] on which [7] is based. In particular, the original model does not account for
diode reverse current blocking that arises in discontinuous conduction mode and during large
transients. We have augmented the original model accordingly.
We provide comparisons of the transient response of the boost converter using
conventional small-signal models and generalized state space models as well as piecewise affine
3
system models. These comparisons are used to select the magnitude of the disturbance that is
included in the piecewise affine system stability analysis.
All of our results have been obtained using MATLAB codes that we have developed and
included in Appendix A.
1.3 Organization
The reminder of the thesis is organized as follows. Chapter 2 reviews conventional
modeling techniques used for single-switch power converters, such as small signal modeling and
generalized state space modeling. Examples of each type of model are presented. Chapter 3
summarizes the definition, construction process, and sufficient conditions for stability of
piecewise affine system symbolic models originally presented by Mirzazad-Barijough in [7]. The
construction process and stability analysis are demonstrated using MATLAB codes developed
independently in this project. Chapter 4 reproduces the PAS modeling of a boost converter as in
[7]. Furthermore, the PAS model is made more complete/accurate by including a circuit topology
that was not modeled previously. Again, results are demonstrated using MATLAB codes
developed independently in this project. Chapter 5 spells out conclusions and recommendations
for future work.
4
Chapter 2
Conventional Models of dc-to-dc Converters
This chapter introduces several common power electronic converters and conventional
modeling methods used for them, such as small signal modeling and generalized state space
modeling. The use of small signal models in conventional analog controller design is also
demonstrated. A generalized state space model of a boost converter in which the diode is
modeled completely is described.
2.1 Single–Switch dc-to-dc Converters
Single-switch dc-to-dc converters are widely used in regulated switch-mode dc power
supplies and in dc motor drive applications [13]. They belong to a class of power converters for
which a source of direct current is converted from one voltage level to another. There are three
common types of single-switch dc-to-dc converters: step-down (buck) converter, step-up (boost)
converter, and step-down/step-up (buck-boost) converter.
2.1.1 Step-Down (Buck) Converter
As the name implies, a step-down or buck converter (Figure 2-1) provides a lower
average output voltage 𝑉𝑜 = ⟨ 𝑣𝑜⟩ than its dc input voltage 𝑉𝑑. For instance, buck converters are
5
used in computer power supplies to convert the 12-V main voltage down to the 0.8 − 1.8 V
needed by the microprocessor, with an energy efficiency approaching 95%.
Vd
L
C Ro vo(t)
S
D
Figure 2-1. Schematic diagram of the buck converter.
While the switch is on, the diode is reverse biased by the dc voltage source, and the
inductor absorbs energy from the source, as 𝑉𝑑 > 𝑣𝑜; some of this energy is stored in the inductor
and the rest is passed onto the load. When the switch is turned off, the diode turns on
automatically to conduct the inductor current. While the diode is on, some of the energy stored in
the inductor is delivered to the load. The capacitor is used to reduce ripple in the output voltage,
so that 𝑣𝑜 ≈ 𝑉𝑜. The voltage conversion ratio 𝑉𝑜/𝑉𝑑 depends on the duty ratio of the switch 𝐷 =
𝑇𝑜𝑛/𝑇𝑠 where 𝑇𝑠 is the switching period and 𝑇𝑜𝑛 is on-time of the switch. An expression for the
voltage conversion ratio is derived in Section 2.2.
2.1.2 Step-Up (Boost) Converter
A step-up or boost converter (Figure 2-2) provides a higher average output voltage than
its dc input voltage. When the switch is on, the diode is reverse biased by the capacitor, and the
inductor absorbs energy from the dc voltage source 𝑉𝑑. When the switch is turned off, the diode
turns on automatically to conduct the inductor current. While the diode is on, some of the energy
6
stored in the inductor current is transferred to the load. The capacitor is used to reduce ripple in
the output voltage.
Vd
L
C Ro vo(t)S
D
Figure 2-2. Schematic diagram of the boost converter.
2.1.3 Buck-Boost Converter
A buck–boost converter (Figure 2-3) provides an average output voltage that may be
lower than or higher than the dc input voltage. Its topology can be obtained by simplifying the
cascade connection of a buck converter and a boost converter.
Vd
L C Ro vo(t)
DS
Figure 2-3. Schematic diagram of the buck-boost converter.
2.2 Periodic Steady State Analysis
Periodic steady state analysis of a single-switch dc-to-dc converter is used to derive the
voltage conversion ratio of the converter as a function of the switch duty cycle, and possibly, the
7
load current or resistance. Based on the form of the inductor current 𝑖𝐿, a single-switch dc-to-dc
converter can operate in two distinct modes: (1) continuous-conduction mode (CCM) and (2)
discontinuous-conduction mode (DCM).
2.2.1 Continuous Conduction Mode
t
iL
IL
Ts
ton toff
Figure 2-4. Typically inductor current waveform for a converter operating in CCM.
Figure 2-4 shows a typical periodic steady-state inductor current waveform for
continuous-conduction mode where 𝑖𝐿 > 0 for all time. In the periodic steady state, the average
inductor voltage must be zero. This also means that the energy into the inductor is equal to the
energy out of the inductor over one period. The boost operating in CCM the voltage conversion
ratio can be derived since in steady state the time integral of the inductor voltage in one period
must be zero,
𝑉𝑑𝑡𝑜𝑛 + (𝑉𝑑 − 𝑉𝑜)𝑡𝑜𝑓𝑓 = 0
dividing both sides by 𝑇𝑠 the voltage conversion ratio can be represented as,
𝑉𝑜𝑉𝑑=
𝑇𝑠𝑡𝑜𝑓𝑓
=1
1 − 𝐷
8
2.2.2 Discontinuous Conduction Mode
A converter operates in discontinuous-conduction mode (DCM) when the diode blocks
reverse current under light loading conditions. A typical DCM inductor current waveform is
shown in Figure 2-5. In this mode, the average inductor current 𝐼𝐿 < ∆𝐼𝐿 2⁄ , where ∆𝐼𝐿 is the
maximum instantaneous inductor current.
t
iL
IL
Ts
tonΔ1Ts Δ2Ts
Figure 2-5. Typically inductor current waveform for a boost converter operating in DCM.
Based on the truth that integral of inductor voltage over one time period equal zero when
operating in steady state
𝑉𝑑𝐷𝑇𝑠 + (𝑉𝑑 − 𝑉𝑜)Δ1𝑇𝑠 = 0
where Δ1𝑇𝑠 means the time from switch off to current blocked. The voltage conversion ration can
be expressed as,
𝑉𝑜𝑉𝑑=Δ1 + 𝐷
Δ1
2.3 Generalized State Space Modeling
This section describes generalized state space modeling and applies it to the boost
converter as an example. The model is also refined by adding a circuit topology corresponding to
diode reverse current blocking.
9
2.3.1 Form of Generalized State Space Model
The nonlinear dynamics of a power converter system can be represented by several linear
time invariant (LTI) systems along with switching functions that define transitions from one LTI
system to another. Each of the LTI systems corresponds to a circuit topology imposed by the
conduction state of the switch and diode. Each of the switching functions is comprised of a linear
combination of the state vector, input vector, and time. Assuming M circuit topologies, the LTI
model, switching surface, and state vector map from topology 𝑚 ∈ {1, . . , 𝑀} to topology 𝑛 ∈
{1, . . , 𝑀}:
�̇�𝑚 = 𝐀𝑚𝐱𝑚 + 𝐁𝑚𝐮𝐲 = 𝐂𝑚𝐱𝑚 + 𝐃𝑚𝐮
𝛔𝑚(𝐱𝑚, 𝐮, 𝑑) = 𝛔𝑥𝑚𝐱𝑚 + 𝛔𝑢𝑚𝐮 + 𝛔𝑑𝑚𝑑 + 𝛔𝑐𝑚
𝐱𝑛 = 𝐑𝑛𝑚𝐱𝑚
2.3.2 Continuous Conduction Mode
In CCM, there are only two circuit topologies to consider: switch on and switch off. The
switch-on topology is shown in Figure 2-6.
Vd
L RL
CRo vo(t)
vL(t) iC(t)
iL(t)
RC
Figure 2-6. Circuit topology of boost converter while switch is on.
10
A state-space representation of switch on topology can be derived by applying basic
circuit analysis. The result is
[
𝑑𝑣𝐶𝑑𝑡𝑑𝑖𝐿𝑑𝑡
] =
[
−1
(𝑅𝑜 + 𝑅𝐶)𝐶0
0−𝑅𝐿𝐿 ] [𝑣𝐶𝑖𝐿] + [
01
𝐿
] 𝑉𝑑
Thus,
𝐀1 =
[
−1
(𝑅𝑜 + 𝑅𝐶)𝐶0
0−𝑅𝐿𝐿 ]
𝐁1 = [01
𝐿
]
The switch-off topology is shown in Figure 2-7.
Vd
L RL
C
Ro
vL(t) iC(t)
vo(t)
iL(t)
RC
Figure 2-7. Circuit topology of boost converter while switch is off and converter is operating in
CCM.
The state-space representation is,
[
𝑑𝑣𝐶𝑑𝑡𝑑𝑖𝐿𝑑𝑡
] =
[
−1
(𝑅𝑜 + 𝑅𝐶)𝐶
𝑅𝑜(𝑅𝑜 + 𝑅𝐶)𝐶
−𝑅𝑜𝐿(𝑅𝑜 + 𝑅𝐶)
−1
𝐿(𝑅𝐿 +
𝑅𝐶𝑅𝑜𝐿((𝑅𝑜 + 𝑅𝐶)
)]
[𝑣𝐶𝑖𝐿] + [
01
𝐿
] 𝑣𝑑
Thus,
11
𝐀2 =
[
−1
(𝑅𝑜 + 𝑅𝐶)𝐶
𝑅𝑜(𝑅𝑜 + 𝑅𝐶)𝐶
−𝑅𝑜𝐿(𝑅𝑜 + 𝑅𝐶)
−1
𝐿(𝑅𝐿 +
𝑅𝐶𝑅𝑜𝐿((𝑅𝑜 + 𝑅𝐶)
)]
𝐁2 = [01
𝐿
]
Example 1:
Consider a boost converter as in [6], 𝐿 = 10 μH, 𝐶 = 50 μF, 𝑅𝐿 = 1 μΩ, 𝑅𝑜 =
30 Ω, 𝑉𝑑 = 1 V, 𝑉𝑜 = 5 V, 𝑇 = 20 μs and apply the feedback control law as in [6],
𝐅 = [−0.0291 − 0.0356]
The duty ratio in the 𝑘𝑡ℎ switching period is represented as
𝑑𝑘 = 𝐷 + 𝐅[ 𝐱(𝑘𝑇𝑠) − 𝐱∗ ]
where 𝐷 = 1 − 𝑉𝑑/𝑉𝑜, 𝐱( 𝑘𝑇𝑠 ) is the state vector at the start of the 𝑘𝑡ℎ switching period (end of
the last switching period), and 𝐱∗ is the steady state operating point of the system.
𝜎1(𝐱1, 𝐮, 𝑑) = −𝑑 + (𝐷 + 𝐅[ 𝐱(𝑘𝑇𝑠) − 𝐱∗ ])
The switching surface for Topology 2 is
𝜎2(𝐱2, 𝐮, 𝑑) = −𝑑 + (𝐷 + 𝐅[ 𝐱(𝑘𝑇𝑠) − 𝐱∗ ])
The state vector maps are simply
𝐑12 = 𝐑21 = 𝐈
The transient response of the generalized state space model of the boost converter
without diode reverse current blocking is shown in the Figure 2-8.
12
Figure 2-8. Transient response of boost converter using GSSM without diode reverse current
blocking.
The transient response relative to the steady state operating point is shown in Figure 2-9
and indicates that the system is stable.
Figure 2-9. Transient response of boost converter using GSSM without diode reverse current
blocking relative to steady state.
The inductor current in Figure 2-8 and Figure 2-9 goes below zero as a result of
incomplete modeling of the diode, which should block reverse current.
-5
0
5
10Transient Response of Boost Converter Generalized State Space Modeling without Diode Reverse Current Blocking
vC
(V)
0 0.5 1 1.5 2 2.5 3 3.5 4
x 10-3
-5
0
5
10
d
iL (A)
-10 -8 -6 -4 -2 0 2 4 6 8-5
0
5
10Transient Response Relative to Steady State Generalized State Space Modeling without Diode Reverse Current Blocking
iL - i
L
*
vC
- vC
*
13
2.3.3 Discontinuous Conduction Mode
In DCM, there is a third circuit topology in which both the switch and the diode are off.
This topology is shown in Figure 2-10.
Vd
L RL
C
Ro
vL(t) iC(t)
vo(t)
iL(t)
RC
Figure 2-10. Circuit topology for boost converter while switch is off and the converter is operating in
DCM.
The state-space representation is,
[𝑑𝑣𝐶𝑑𝑡] = [
−1
(𝑅𝑜 + 𝑅𝐶)𝐶] [𝑣𝐶] + [0]𝐸
Thus,
𝐀3 = [−1
(𝑅𝑜 + 𝑅𝐶)𝐶]
𝐁3 = [0]
𝑖𝐿(𝑡) = 0
The switching surface for Topology 2 must be modified and a switching surface for
Topology 3 must be defined:
𝜎2(𝐱2, 𝐮, 𝑑) = −𝑑 + (𝐷 + 𝐅[ 𝐱(𝑘𝑇𝑠) − 𝐱∗ ])
𝜎3(𝐱3, 𝐮, 𝑑) = −𝑑 + (𝐷 + 𝐅[ 𝐱(𝑘𝑇𝑠) − 𝐱∗ ])
The additional state vector maps are
14
𝐑32 = [1 0]
𝐑13 =[10]
Example 2:
When modeling the converter with a diode reverse current blocking, the transient
response of the boost converter is simulated in Figure 2-11.
Figure 2-11. Transient response of GSSM with diode modeled completely.
The simulated transient response relative to steady state in Figure 2-12 indicates the
system is stable. We can find the current will not drop below zero in Figure 2-11 and Figure 2-12
by modeling the diode properly. It is a more accurate modeling approach than the model in [6]
and [7].
-5
0
5
10
vC
(V)
Transient Response of Boost Converter Generalized State Space Modeling with Diode Modeled Properly
0 0.002 0.004 0.006 0.008 0.01 0.012-5
0
5
10
15
iL (A)
t
15
Figure 2-12. Transient response of GSSM with diode modeled properly relative to steady state.
2.4 Small Signal Modeling
Small signal analysis has appeared in the power electronics literature in various forms
[14]: state space averaging, switch averaging, and dynamic phasors. The main purpose of small
signal models is to permit the use of well-established control design methods for linear systems.
Small signal analysis is the study of deviations from an operating point for a system
subjected to small disturbances [15]. The prerequisite condition of this method is that the
disturbances are small enough that the deviation of the system can be described linearly.
2.4.1 Analog Control of dc-to-dc Converters
In most dc-to-dc converter applications, the average output voltage must be regulated
(Figure 2-13) to a desired level in spite of disturbances in the input voltage Vd or output load Ro.
-10 -8 -6 -4 -2 0 2 4 6 8-2
0
2
4
6
8
10
12
14
Transient Response Relative to Steady State Generalized State Space Modeling with Diode Modeled Properly
iL - i
L
*
vC
- vC
*
16
Vd
L RL
C Ro vo(t)
iL(t)
vL(t) iC(t)
Controller
PWM
Vo_ref
Figure 2-13. Schematic of boost dc-to-dc converter with voltage regulation.
In a single-switch dc-to-dc converter, the average output voltage is controlled by
controlling the switch on and off time. The most common method of regulation utilizes pulse-
width modulation (PWM) in which the switch is turned on periodically, but the duration of the
on-time each period (i.e., the duty cycle) may change from period to period.
The PWM control signal is usually generated by comparing a control voltage 𝑣𝑐𝑜𝑛𝑡𝑟𝑜𝑙 to
a sawtooth waveform as shown in Figure 2-14.
17
Comparator Amplifier
vcontrolVref
Vo Sawtooth PWM
(a)
vcontrolSawtooth Waveform
On
Off
(b)
Figure 2-14. PWM controller. (a) Block diagram showing compensator amplifier and comparator.
(b) Comparator signals.
The 𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙 signal is generated by the compensator amplifier which is designed based on
the small signal model of power converter.
2.4.2 State Space Averaging
The State Space Averaging method was the first formal method for small signal modeling
of power converters [3]. The averaged state space model is obtained by a weighted summation of
the state matrices. The weight of each matrix is determined by the PWM switch on and off time:
18
�̇� = (𝑑𝐀1 + 𝑑′𝐀2)𝐱 + ( 𝑑𝐛1 + 𝑑
′𝐛2)𝑉𝑑 (2.1)
𝐲 = (𝑑𝐜1𝑇 + 𝑑′𝐜2
𝑇)𝐱
where 𝑑 = 𝑇𝑜𝑛/𝑇𝑠 , 𝑑′ = 𝑇𝑜𝑓𝑓/𝑇𝑠 , 𝑇𝑜𝑛 and 𝑇𝑜𝑓𝑓 are switch time intervals, and 𝑇𝑠 is the switching
period.
The system described by (2.1) can be perturbed, by introducing a perturbation of input
voltage 𝑉𝑑 and/or duty ratio 𝑑. Then the dc and ac solutions are obtained in following form [3]:
𝐗 = −[𝑫𝐀𝟏 + (𝟏 − 𝑫)𝐀𝟐]−𝟏[𝑫𝐛𝟏 + (𝟏 − 𝑫)𝐛𝟐]𝑽𝒅
𝐘 = [𝑫𝐜𝟏 + (𝟏 − 𝑫)𝐜𝟐
]𝐗
�̇̂� = [𝑫𝐀𝟏 + (𝟏 − 𝑫)𝐀𝟐]�̂� + [𝑫𝐛𝟏 + (𝟏 − 𝑫)𝐛𝟐]�̂�𝒅 + [(𝐀𝟏 − 𝐀𝟐)𝐗 + (𝐛𝟏 − 𝐛𝟐)𝑽𝒅]�̂�
�̂� = [𝑫𝐜𝟏 + (𝟏 − 𝑫)𝐜𝟐
]�̂� + [(𝐀𝟏 − 𝐀𝟐)𝐗 + (𝐛𝟏 − 𝐛𝟐)𝑽𝒅]�̂�
Although the State Space Averaging method allows us to extend standard dc and ac
circuit analysis techniques to switching circuits and transient analyses can also be run much faster
by using State Space Averaging models. However by applying State Space Averaging, we ignore
the cycle-by-cycle switching and looking at the average characteristics of the circuit at
frequencies below half the switching frequency. We lose the ability to see switching ripple or
actual switching waveforms.
2.4.3 Circuit Averaging
Circuit averaging is an approach that relate average voltages and currents at two ports
associated with a transistor-diode pole used to implement any of the basic dc-to-dc converters.
The small signal transfer function for boost converter can be derived as [16],
19
�̃�𝑜
�̃�=
𝑣𝑑( 1 − 𝐷 )2
( 𝑠𝑅𝐿𝐶 + 1)( −𝑠
𝐿𝑒𝑞𝑅𝑜
+ 1)
𝑠2𝐿𝑒𝑞𝐶 + 𝑠 ( 𝑅𝐿𝐶 + 𝐿𝑒𝑞𝑅 ) + 1
𝐿𝑒𝑞 = 1
(1+𝐷 )2 𝐿.
Zeroes of the plant transfer function are 𝜔𝑧1 = − 1
𝑅𝐿𝐶, 𝜔𝑧2 =
𝑅𝑜
𝐿𝑒𝑞. Notice that 𝜔𝑧1 is in the
right half plane (RHP). The complex-conjugate poles of the plant transfer function have
frequence 𝜔𝑜 = √1
𝐿𝑒𝑞𝐶.
2.4.4 Controller Design
A voltage-mode controlled boost converter operating in continuous conduction mode
(CCM) should be designed concerning the boost converter’s inherent RHP zero.
Example 3:
Consider a boost converter as in [6] in Example 1. We set compensator zeroes and poles,
𝜔𝑧1𝑐 = 𝜔𝑧2𝑐 = 0.6 𝜔𝑝1, 𝜔𝑝1𝑐 = 𝜔𝑧2 (cancel RHP pole), 𝜔𝑝2𝑐 = 𝜔𝑝1𝑐. Small signal modeling
voltage compensator for boost converter operating on CCM.
𝑇𝑐𝑜𝑚𝑝𝑒𝑛𝑠𝑎𝑡𝑜𝑟(𝑠) = 5.756 ∙ 104𝑠2 + ( 𝜔𝑧1𝑐 + 𝜔𝑧2𝑐 )𝑠 + 𝜔𝑧1𝑐𝜔𝑧2𝑐
𝑠3 + ( 𝜔𝑝1𝑐 + 𝜔𝑝2𝑐)𝑠2 + 𝜔𝑝1𝑐𝜔𝑝2𝑐
= 5.756 ∙ 104𝑆2 − 2.302 ∙ 107𝑠 + 1.658 ∙ 1012
𝑠3 + 2.4 ∙ 105 + 1.44 ∙ 1010
The closed-loop transfer function for the system is
20
𝐻(𝑠) = −5.996 ∙ 10−10𝑠4 − 11.99𝑠3 + 1.444 ∙ 106𝑠2 + 9.21 ∙ 108𝑠 + 4.144 ∙ 1013
1.25 ∙ 10−8𝑠5 + 0.003008𝑠4+ 171𝑠3 + 1.804 ∙ 106𝑠2 + 1.348 ∙ 1010𝑠 + 4.144 ∙ 1013
The Bode plot of the compensated boost converter is shown in Figure 2-15. The corner
frequency is seen to be 𝜔𝑐 = 2 ∙ 104 Hz and the phase margin is 63°, which should be adequate to
ensure stability even in the presence of disturbances.
Figure 2-15. Bode plot of small signal model of closed-loop boost converter system.
The step response of the compensated boost converter is shown in Figure 2-16. The
system has overshoot of 30% and setting time of 1.2 ms, which satisfies the common
performance requirement.
-150
-100
-50
0
50
Magnitude (
dB
)
102
103
104
105
106
107
0
90
180
270
360
Phase (
deg)
Boost CCM: Bode Plot of Tp, T
c, T
ol, and T
cl
Frequency (Hz)
21
Figure 2-16. Step response of small signal model of closed-loop boost converter system.
Zero-order hold equivalent discrete compensator transfer function can be represented as,
𝑇𝑐𝑜𝑚𝑝𝑒𝑛𝑠𝑎𝑡𝑜𝑟_𝑑 = 0.1041𝑧2 − 0.2069𝑧 + 0.1047
𝑧3 − 1.181𝑧2 + 0.1897𝑧 − 0.00823
The step response of the discrete-time model is shown in Figure 2-17, which demonstrates that
the controller is also stable in discrete time domain with a sample time of 𝑇𝑠 = 20 ∙ 10−6 𝑠.
Figure 2-17. Step response of discrete time small signal model of closed-loop boost converter system.
0 1 2 3 4 5 6 7 8
x 10-4
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
1.4Step Response for Continuous Model
Time (seconds)
Am
plit
ude
0 1 2 3 4 5 6
x 10-4
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
1.4Step Response for Discrete Model
Time (seconds)
Am
plit
ude
22
The simulation of the small signal modeling controller and boost converter is developed
with the parameters in last section (shown in Figure 2-18). It operates in the steady state
with 𝑉𝑜 = 5 V when the reference output voltage steps by 0.5 V to 5.5 V the system can have a
right response to 5.47 V.
Figure 2-18. Transient response of small signal modeling digital PWM boost converter.
The transient response relative to the steady state operating point is shown in Figure 2-19
and indicates that the system is asymptotically stable.
Figure 2-19. Transient response relative to steady state operating point.
4.5
5
5.5
6
vC
(V)
Transient Response of Converter over Several Periods
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
0
2
4
6
8
iL (A)
s
y transitions
y waveform
-0.1 0 0.1 0.2 0.3 0.4 0.5 0.6
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
Transient Response of Converter over Several Periods
iL (A)
vC
(V)
y transitions
23
Figure 2-20 shows the PWM duty ratio response by the voltage regulation which
illustrates that the controller is stable.
Figure 2-20. PWM duty ratio response.
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.020.795
0.8
0.805
0.81
0.815
0.82PMW duty ratio
t(s)
d
24
Chapter 3
Discrete-Time Piecewise Affine Systems
This chapter summarizes the definition of discrete-time piecewise affine systems and the
stability analysis of such systems as presented in [7]. Several of the examples in [7] are
reproduced using independently developed MATLAB codes. These codes will be used to analyze
the stability of a dc-to-dc boost converter in the next chapter.
3.1 Discrete-Time Piecewise Affine Systems Modeling
This section echos the definition of a discrete-time piecewise affine system and a
corresponding symbolic model used for stability analysis from [7] and [错误!未定义书签。].
3.1.1 Discrete-Time Piecewise Affine System Representation
A discrete-time piecewise affine system (without disturbances) can be defined as follows
[17]. Suppose 𝑛,𝑚, 𝑙, 𝑁 ∈ ℕ are given,
𝒮 = {(𝐀1, 𝐁1, 𝐛1, 𝐂1, 𝐃1, 𝐝1, ), … , (𝐀𝑁 , 𝐁𝑁 , 𝐛𝑁 , 𝐂𝑁 , 𝐃𝑁 , 𝐝𝑁)} (3.1)
where 𝐀1, … , 𝐀𝑁 ∈ ℝ𝑛×𝑛, 𝐁1, … , 𝐁𝑁 ∈ ℝ
𝑛×𝑚, 𝐛1, … , 𝐛𝑁 ∈ ℝ𝑛, 𝐂1, … , 𝐂𝑁 ∈ ℝ
𝑙×𝑛,
𝐃1, … , 𝐃𝑁 ∈ ℝ𝑙×𝑚 and 𝐝1, … , 𝐝𝑁 ∈ ℝ
𝑙. Let
𝒟 = {𝐷1, … , 𝐷𝑁} (3.2)
25
be a partition of ℝ𝑛 into 𝑁 nonempty cells such that ∪𝑖=1𝑁 𝐷𝑖 = ℝ
𝑛 and 𝐷𝑖 ∩ 𝐷𝑗 = ∅ whenever
𝑖 ≠ 𝑗. Then the pair (𝒮, 𝒟) defines the discrete-time piecewise affine system represented by
𝐱[𝑘 + 1] = 𝐀𝜃[𝑘]𝐱[𝑘] + 𝐁𝜃[𝑘]𝐮[𝑘] + 𝐛𝜃[𝑘], 𝑘 ∈ ℕ𝑜 (3.3)
𝐲[𝑘] = 𝐂𝜃[𝑘]𝐱[𝑘] + 𝐃𝜃[𝑘]𝐮[𝑘] + 𝐝𝜃[𝑘], 𝑘 ∈ ℕ𝑜
for any initial state 𝐱[0] ∈ ℝ𝑛, where the switching sequence is 𝜃 = (𝜃(0), 𝜃(1), … ) is such that
𝜃[𝑘] = 𝑖 whenever 𝐱[𝑘] ∈ 𝐷𝑖.
3.1.2 Discrete-Time Piecewise Affine System Model Construction
The main purpose of introducing symbolic model construction is to abstract the behavior
of the continuous, infinite piecewise affine system by a discrete, finite model. The symbolic
model can then be used for stability analysis via a partition of the state space. In particular, if the
partitioning process leads to an invariant subdomain with a corresponding stable linear (not
affine) difference equation, the system is stable according to the Theorem 3 of [7].
In the case of power converters, the piecewise affine system is obtained via linearization
of a nonlinear model at selected operating points. Consequently, the piecewise affine system is
an approximate model of original system. We consider this to be a source of modeling error and
treat it as a disturbance in the piecewise affine system model. To incorporate the disturbance in
the partitioning process, we rely on the definition of Minkowski sum of two sets 𝐴 and 𝐵:
𝐴 ⨁𝐵 = {𝑎 + 𝑏: 𝑎 ∈ 𝐴, 𝑏 ∈ 𝐵}
The first symbolic model 𝒮1 is defined as follows: Let 𝒟0 be the original state space
partition and define a vertex set of the state space partition as 𝑉0 = {1, … ,𝑁} where 𝑁 is the
number of subdomains in 𝒟0. Now for each (𝑖, 𝑗) ∈ 𝑉02, the refinement of 𝒟0 can be derived by
26
�̃�(𝑖,𝑗) = {𝐱 ∈ 𝐷𝑖: 𝐀𝑖𝐱 + 𝐛𝑖 ∈ 𝐷𝑗 ⨁ (−𝐁𝑗𝑊)} (3.4)
In other words, �̃�(𝑖,𝑗) is the set of all states 𝐱[𝑘] in subdomain 𝐷𝑖 that map into states
𝐱[𝑘 + 1] that are in subdomain 𝐷𝑗 with disturbance 𝑤(𝑡) ∈ 𝑊. A reverse search technique
[18] can be used to compute each nonempty set �̃�(𝑖,𝑗) where (𝑖, 𝑗) ∈ 𝑉02.
Now, define an edge set of the state space partition as 𝐸0 = {(𝑖, 𝑗) ∈ 𝑉02 ∶ �̃�(𝑖,𝑗) ≠ ∅}
and directed graph as 𝐺0 = (𝑉0, 𝐸0). Also, define the switching sequence 𝑀𝑖 = {𝑖} for each 𝑖 ∈
𝑉0 and the set ℳ0 = {𝑀𝑖: 𝑖 ∈ 𝑉0}. Then 𝑆0 = (𝐷0, 𝐺0, 𝑀0) is constructed as the initial
symbolic model of the piecewise affine system (𝒮, 𝒟). With 𝑆0 and the refinement of 𝐷0, �̃�1 =
{�̃�(𝑖,𝑗) ∶ (𝑖, 𝑗) ∈ 𝐸0} we can construct the next symbolic model.
Supposing �̃�𝐿+1 is a refinement of the partition 𝒟𝐿 with disturbance 𝑊, the subdomains
in �̃�𝐿+1 may overlap each other. To obtain a valid non-overlapping partition 𝒟𝐿+1, a minterm-
based method can be used to obtain the coarsest, convex polyhedral partition that is compatible
with �̃�𝐿. The set of switching sequences represented by the serial number of the original partition
𝒟0 to each 𝑖 ∈ 𝑉𝐿+1 can be represented by
𝑀𝑖 = {(𝑖0, … , 𝑖𝐿+1) ∈ 𝑉0𝐿+2: (𝑖0, … , 𝑖𝐿) ∈ 𝑀𝑗 , (𝑖1, … , 𝑖𝐿+1) ∈ 𝑀𝑘 , 𝐷𝑖 ⊂ �̃�(𝑗,𝑘), (𝑗, 𝑘) ∈ 𝐸𝐿} (3.5)
with ℳ𝐿+1 = {𝑀𝑖 ∶ 𝑖 ∈ 𝑉𝐿+1} and 𝐺𝐿+1 = (𝑉𝐿+1, 𝐸𝐿+1). The symbolic model
𝒮𝐿+1 = {𝒟𝐿+1, 𝐺𝐿+1, 𝑀𝐿+1}
is thus obtained.
The algorithm for constructing a symbolic model can be summarized as follows:
1. Let 𝐿 = 0, 𝒟0 = {𝐷1, … , 𝐷𝑁}, 𝑉0 = {𝑖: 𝐷𝑖 ∈ 𝒟0}, 𝑀𝑖 = {𝑖} for each 𝑖 ∈ 𝑉0 and ℳ0 = {𝑀𝑖: 𝑖 ∈ 𝑉0}.
2. For each (𝑖, 𝑗) ∈ 𝑉𝐿2, construct �̃�(𝑖,𝑗) as function (3.4). Let 𝐸𝐿 = {(𝑖, 𝑗): �̃�(𝑖,𝑗) ≠ ∅}
and 𝒟𝐿+1 = {�̃�(𝑖,𝑗): (𝑖, 𝑗) ∈ 𝐸𝐿 }.
27
3. Output 𝒮𝐿 = {𝒟𝐿 , 𝐺𝐿 , 𝑀𝐿} and �̃�𝐿+1.
4. Obtain the coarsest partition of �̃�𝐿+1.
5. Let 𝑉𝐿+1 = {𝑚𝑎𝑥𝑉𝐿 + 1,… ,𝑚𝑎𝑥𝑉𝐿 + | �̃�𝐿+1|}.
6. For each 𝑖 ∈ 𝑉𝐿+1 obtain 𝑀𝑖 as in (3.5) and let ℳ𝐿+1 = {𝑀𝑖: 𝑖 ∈ 𝑉𝐿+1}.
7. Increment 𝐿 to 𝐿 + 1 and go to Step 1.
3.2 Definition of State Space Partition
In mathematics, space partitioning is the process of dividing a space into two or more
disjoint subsets. This section describes a procedure for recursively refining the state-space
partition while representing the switching sequence of the domain specified by the initial partition
of the state space. If a piecewise affine system is stable, the partition procedure will terminate
after a finite number of steps when the partition keeps identical with unique subdomain switching
sequence. At the same time, the affine term of the unique subdomain should be all zeroes [7].
Let 𝒮 and 𝒟 be as in (3.1) and (3.2), so the symbolic model (𝒮, 𝒟) defines a piecewise
affine system of the form (3.3). Define
𝐷𝑖(𝑄) = 𝑄 ∩ 𝐷𝑖 for 𝑖 ∈ {1, … , 𝑁}
and
𝐷(𝑖0,…,𝑖𝐿)(𝑄) = {𝐱 ∈ 𝐷(𝑖0,…,𝑖𝐿−1)(𝑄): 𝐀𝑖0𝐱 + 𝐛𝑖0 ∈ 𝐷(𝑖1,…,𝑖𝐿)(𝑄)} (3.6)
recursively for 𝐿 ∈ ℕ and (𝑖0, … , 𝑖𝐿) ∈ {1, … , 𝑁}𝐿+1, so that 𝐷(𝑖0,…,𝑖𝐿)(𝑄) is the set of all states
in 𝐷(𝑖0,…,𝑖𝐿−1)(𝑄) ⊂ 𝑄 that will jump into the region 𝐷(𝑖1,…,𝑖𝐿)(𝑄) ⊂ 𝑄 in one step.
Using this approach, the initial state space partition of Q is
𝒟0(𝑄) = {𝐷1(𝑄), … , 𝐷𝑁(𝑄)},
For each 𝐿 ∈ ℕ0, the state space partition
28
𝒟𝐿(𝑄) = {𝐷(𝑖0,…,𝑖𝐿)(𝑄): (𝑖0, … , 𝑖𝐿) ∈ {1, … ,𝑁}𝐿+1}
contains all 𝐷(𝑖0,…,𝑖𝐿)(𝑄) that are nonempty and can be call 𝐿 − 𝑝𝑎𝑡ℎ 𝑝𝑎𝑟𝑡𝑖𝑡𝑖𝑜𝑛 𝑜𝑓 𝑄.
3.3 Algorithm to Obtain a State Space Partition
3.3.1 State Space Partition without Disturbance
Considering there is no disturbance 𝑊, a nonempty partition polyhedron set 𝐷(𝑖0,…,𝑖𝐿+1)
that belongs to 𝐿 + 1 − 𝑝𝑎𝑡ℎ 𝑝𝑎𝑟𝑡𝑖𝑡𝑖𝑜𝑛 by the definition (3.4), can be interpreted as a set of
inequality functions
[𝐑(𝑖0,…,𝑖𝐿)
𝐑(𝑖1,…,𝑖𝐿+1)𝐀𝑖0] 𝐱 + [
𝐫(𝑖0,…,𝑖𝐿)𝐑(𝑖1,…,𝑖𝐿+1)𝐛𝑖0 + 𝐫(𝑖1,…,𝑖𝐿+1)
] < 𝟎 (3.7)
The first inequality functions 𝐑(𝑖0,…,𝑖𝐿)𝐱 + 𝐫(𝑖0,…,𝑖𝐿) < 𝟎 represent the state vector that
belongs a region of the state space of 𝐿 − 𝑝𝑎𝑡ℎ 𝑝𝑎𝑟𝑡𝑖𝑡𝑖𝑜𝑛 with switching sequence(𝑖0, … , 𝑖𝐿).
The second inequality functions 𝐑(𝑖1,…,𝑖𝐿+1)(𝐀𝑖0𝐱 + 𝐛𝒊𝟎) + 𝐫(𝑖1,…,𝑖𝐿+1) < 𝟎 indicate that the state
vector 𝐱 in both domain 𝑖0 and 𝐷(𝑖0,…,𝑖𝐿) can switch into the area of 𝐿 − 𝑝𝑎𝑡ℎ with switch
sequence(𝑖𝑖 , … , 𝑖𝐿+1). Therefore, by solving the combined inequality functions (3.7), we can get
the subdomain of state space belongs to 𝐿 + 1 − 𝑝𝑎𝑡ℎ with switching sequence(𝑖0, … , 𝑖𝐿+1).
Each non-empty domain of the state space partition can be represented by polytope
whose vertices can be determined by solving the inequality functions (3.7). In the case of ℝ2, the
polytope is actually just a polygon that can be determined by the following algorithm:
1. Treat each inequality function entry as an equation that can be represented as a line in
the state space plane.
2. Calculate all intersections of the lines.
3. Keep all the intersections that satisfy the inequality functions of (3.7).
29
As in [19], we can draw a conclusion that 𝒟𝐿(𝑄) is invariant if partition pattern is the
same as 𝒟𝐿+1(𝑄).
Example 4:
Consider the system (𝒮,𝒟) of Example 5 in [7] with 𝑁 = 3, where 𝒮 is defined by,
𝐀1 = [−1
40
−1 −1
4
], 𝐛1 = [00]
𝐀2 = [0 0
−1
4−1
2
], 𝐛2 = [00]
𝐀3 = [
5
2−1
21
2−5
2
], 𝐛3 = [10]
and 𝒟 is
𝐷1 = {[𝑥1 𝑥2]𝑇 ∈ ℝ2 ∶ 𝑥1 − 𝑥2 < 2, 𝑥1 + 𝑥2 ≥ 0},
𝐷2 = {[𝑥1 𝑥2]𝑇 ∈ ℝ2 ∶ 𝑥1 + 𝑥2 < 0, 𝑥1 < 1},
𝐷3 = {[𝑥1 𝑥2]𝑇 ∈ ℝ2 ∶ 𝑥1 − 𝑥2 ≥ 2, 𝑥1 ≥ 1}.
The original domains above can be represented by translating the definition of 𝒟 into
inequality functions as,
𝐷𝑖: 𝐑𝑖𝐱 < 𝐤𝑖, 𝑖 ∈ {1,2,3}
𝐑1 = [1 −1−1 −1
] , 𝐤1 = [20]
𝐑2 = [1 11 0
] , 𝐤2 = [01]
30
𝐑3 = [−1 1−1 0
] , 𝐤3 = [−2−1]
Then the partition 𝐷(𝑖,𝑗) polygon can be obtained by solving the inequality functions
𝐷(𝑖,𝑗) = {𝐱 ∈ 𝐷𝑖: 𝐀𝑖𝐱 + 𝐛𝑖 ∈ 𝐷𝑗}
which is also
{𝐑𝑖𝐱 < 𝐤𝑖
𝐑𝑗(𝐀𝑖𝐱 + 𝐛𝑖) < 𝐤𝑗
with the algorithm given above.
𝐷(𝑖,𝑗) indicates an action in which state vector [𝑥1 𝑥2]𝑇 ∈ ℝ2 switches from subdomain
𝐷𝑖 to subdomain 𝐷𝑗 in one step from the initial partition of state space. The Figure 3-1
demonstrates the 1 − 𝑝𝑎𝑡ℎ 𝑝𝑎𝑟𝑡𝑖𝑡𝑖𝑜𝑛 that indicates the switching sequence. For example,
subdomain 𝐷11 is the area that includes state vectors that switch from subdomain 𝐷1 to (the same)
subdomain 𝐷1, while 𝐷12 is the area that includes state vectors that switch from subdomain 𝐷1
to subdomain 𝐷2. In this particular system, the state vector cannot switch from subdmain 𝐷1 to
subdomain 𝐷3, so there is no subdomain 𝐷13 in Figure 3-1.
31
(a) 𝒟0 (b) 𝒟1
Figure 3-1. State space partitions 𝓓𝟎 and 𝓓𝟏.
Similarly, the state space partition 𝐷𝑖𝑗𝑘 of 2 − 𝑝𝑎𝑡ℎ 𝑝𝑎𝑟𝑡𝑖𝑡𝑖𝑜𝑛 𝑜𝑓 𝑄 can be calculated by
solving inequality functions,
{𝐑𝑖𝑗𝐱 < 𝐤𝑖𝑗
𝐑𝑗𝑘(𝐀𝑖𝐱 + 𝐛𝑖) < 𝐤𝑗𝑘
Figure 3-2. State-Space Partitions 𝓓𝟑.
-4 -2 0 2 4-4
-3
-2
-1
0
1
2
3
4
D11
D12
D21
D22
D31
D33
D1
-4 -2 0 2 4-4
-3
-2
-1
0
1
2
3
4
D112
D121
D212
D221
D312
D333
D2
32
For example, in Figure 3-2 𝐷112 is the area that includes a state vector that can switch
from subdomain 𝐷1 to subdomain 𝐷1 and then to subdomain 𝐷2 in a 2 − 𝑝𝑎𝑡ℎ. The state space
partition is identical to the result of Example 5 in [7] indicating that the state space partitioning
algorithm has been implemented correctly
3.3.2 State Space Partition with Disturbance
Suppose disturbance 𝑊 is represented as the vertices of a polytope, by the definition of
Minkowski sum the subdomains can be derived from (3.7) by enlarging the domains which
process is demonstrated in the Example 5.
Example 5:
Given a system (𝒮,𝒟) of Example 4 in [7] with 𝑁 = 3, where 𝒮 and 𝒟 is defined by,
𝐀1 = [−1
20
−3
2−1
2
], 𝐛1 = [00]
𝐀2 = [−1
41
01
2
], 𝐛2 = [00]
𝐀3 = [2 −10 3
], 𝐛3 = [11]
𝐁1 = 𝐁2 = 𝐁3 = [1 00 1
]
and
𝐷1 = {[𝑥1 𝑥2]𝑇 ∈ ℝ2 ∶ 𝑥1 ≤ −1},
33
𝐷2 = {[𝑥1 𝑥2]𝑇 ∈ ℝ2 ∶ −1 < 𝑥1 < 1},
𝐷3 = {[𝑥1 𝑥2]𝑇 ∈ ℝ2 ∶ 1 < 𝑥1}.
The boundary 𝑄 is represented by a polygon with vertices [4 2]𝑇, [−4 2]𝑇, [−4 − 2]𝑇
and [4 − 2]𝑇. The disturbance 𝑊 is represented by polygon with vertices [2 2]𝑇, [−2 2]𝑇, [−2 −
2]𝑇 and [2 − 2]𝑇.
Figure 3-3. Polytope of disturbance W for Example 5.
To approach the reverse search method we can simplify the influence of the disturbance
by enlarging the subdomains,
𝐷1′ = {[𝑥1 𝑥2]
𝑇 ∈ ℝ2 ∶ 𝑥1 ≤ −1 + 2},
𝐷2′ = {[𝑥1 𝑥2]
𝑇 ∈ ℝ2 ∶ −1 − 2 < 𝑥1 < 1 + 2},
𝐷3′ = {[𝑥1 𝑥2]
𝑇 ∈ ℝ2 ∶ 1 − 2 < 𝑥1}.
Then the original domain and state space partition are shown in Figure 3-4. In Figure 3-
4, �̃�1 is a refinement of 𝒟0 which means that initial states in a particular domain of �̃�1 transition
to a particular domain in the original partition 𝒟0. For example, the initial states in subdomain
𝐷12 transition from subdomain 𝐷1 to subdomain 𝐷2 in one period. 𝒟1 is derived by finding all
-4 -3 -2 -1 0 1 2 3 4-3
-2
-1
0
1
2
3Disturbance
i L -
iL*
vC
- vC
*
34
the minterms of �̃�1. For example, in Figure 3-5 subdomain 𝐷6 is the overlap area of 𝐷23, 𝐷22,
𝐷21. It indicates that initial state vectors in subdomain 𝐷6 can switch from 𝐷2 to 𝐷3, 𝐷2 or 𝐷1
because the disturbance. The state space partition result is slightly different from Example 5 in
[7] result in 𝐷1 and 𝐷3 due to the partition boundary 𝑄 for exhibition briefly. However the 𝐷2
region is the same with Example 4.
(a) 𝒟0 (b) �̃�1
Figure 3-4. 𝓓𝟎 and �̃�𝟏 for Example 5.
Figure 3-5. 𝓓𝟏 for Example 5.
Chapter 4
Piecewise Affine System Models of dc-to-dc Converters
The stability analysis of dc-to-dc converters modeled as piecewise affine systems is
presented in this chapter. The model construction and state space partitioning procedure
described in [7] are reproduced. Those results are then extended to a model of the converter that
includes diode reverse current blocking in the discontinuous-conduction mode. State space
partitions are generated to analyze the stability of the original model and of the more complete
model. Finally, the approximation error of the piecewise affine system model relative to the
generalized state space model is used to select the extent of the disturbance to include in a
regeneration of the state space partition.
4.1 Derivation of Discrete-Time System Model
This section presents the derivation of two non-linear discrete-time state space models for
the boost converter. The first model matches [7] but is based on an incomplete modeling of the
diode in discontinuous conduction mode. The second model includes the proper behavior of the
diode during reverse blocking but utilizes a Taylor series approximation for determining the start
of the reverse blocking interval.
36
4.1.1 Continuous-Conduction Mode
Using 𝐱(𝑘𝑇𝑠) to represent the initial state in the 𝑘𝑡ℎ switching period and 𝐱((𝑘 + 𝑑𝑘)𝑇𝑠)
to describe the intermediate state when the switch turns off during that switching period, the
response of the system operating in continuous-conduction mode (CCM) can be expressed as
𝐱((𝑘 + 𝑑𝑘)𝑇𝑠) = �̂�1(𝑑𝑘)𝐱(𝑘𝑇𝑠) + �̂�1(𝑑𝑘)
𝐱((𝑘 + 1)𝑇𝑠) = �̂�2(𝑑𝑘)𝐱((𝑘 + 𝑑𝑘)𝑇𝑠) + �̂�2(𝑑𝑘)
where expressions for �̂�1, �̂�2, �̂�1 and �̂�2 can be derived from the appropriate continuous-time
state space representation as the sum of the zero-input response and zero-state response.
𝐱((𝑘 + 1)𝑇𝑠) = 𝑒𝐀𝑇𝑠𝐱(𝑘𝑇𝑠) + ∫ 𝑒𝐀((𝑘 + 1)𝑇𝑠−𝜏)𝐁𝑢(𝜏)𝑑𝜏
(𝑘 + 1)𝑇𝑠
𝑘𝑇𝑠
In particular,
�̂�1(𝑑𝑘) = 𝑒𝐀1𝑑𝑘𝑇𝑠
�̂�1(𝑑𝑘) = ∫ 𝑒𝐀1(𝑡− 𝜏)𝐁1𝑢(𝜏)𝑑𝜏𝑑𝑘𝑇𝑠
0
�̂�2(𝑑𝑘) = 𝑒𝐀2(1− 𝑑𝑘)𝑇𝑠
�̂�2(𝑑𝑘) = ∫ 𝑒𝐀2(𝑡− 𝜏)𝐁2𝑢(𝜏)𝑑𝜏(1−𝑑𝑘 )𝑇𝑠
0
From these, a non-linear discrete-time state space representation can be written as
𝐱[𝑘 + 1] = �̂�(𝑑𝑘)𝐱[𝑘] + �̂�(𝑑𝑘)
where
�̂�(𝑑𝑘) = �̂�2(𝑑𝑘)�̂�1(𝑑𝑘)
�̂� (𝑑𝑘) = �̂�2(𝑑𝑘)�̂�1 (𝑑𝑘) + �̂�2 (𝑑𝑘)
37
A control law to determine 𝑑𝑘 based on the value of the state vector at the end of the previous
switching period will be introduced later.
4.1.2 Discontinuous-Conduction Mode
In discontinuous-conduction mode (DCM), the inductor current 𝑖𝐿 ramps down to 0
during the switch-off interval, but the diode prevents the current from going negative. That is, the
diode turns off, so there is a third circuit topology as shown in Figure 4-1. The output capacitor
continues to discharge though the load resistance.
The state space representation is more complicated for discontinuous-conduction model,
because the switching period is comprised of three intervals instead of two, and the transition
between the Interval 2 and Interval 3 is state dependent.
Vd
L RL
CRo vo(t)
vL(t) iC(t)
iL(t)
RC
Vd
L RL
C
Ro
vL(t) iC(t)
vo(t)
iL(t)
RC
(a) (b)
Vd
L RL
C
Ro
vL(t) iC(t)
vo(t)
iL(t)
RC
(c)
Figure 4-1. Schematic of boost converter when operating in DCM. (a) Switch-on interval. (b) Switch-
off interval. (c) Switch-off and diode-off interval.
38
The circuit topology during Interval 1 is shown in Figure 4-1-(a). The response during
this interval is already known to be
𝐱((𝑘 + 𝑑𝑘)𝑇𝑠) = 𝑒𝐀1𝑑𝑘𝑇𝑠𝐱(𝑘𝑇) + ∫ 𝑒𝐀1(𝑡− 𝜏)𝐁𝟏𝑢(𝜏)𝑑𝜏
𝑑𝑘𝑇𝑠
0
where 𝑑𝑘 is based on the value the state vector at the end of the previous switching period.
During Interval 2 (Figure 4-1-(b)), the switch is off, the diode is on, and the inductor
current ramps down. The response can be represented as
𝐱((𝑘 + 𝑑𝑘 + 𝜎)𝑇𝑠) = 𝑒A2𝜎𝑇𝑠𝐱((𝑘 + 𝑑𝑘)𝑇𝑠) + ∫ 𝑒𝐀2(𝜎𝑇𝑠− 𝜏)𝐁2𝑢(𝜏)𝑑𝜏
𝜎𝑇𝑠0
(4.1)
where 𝜎 < 1 − 𝑑𝑘 indicates the duration time of Interval 2.
The system enters Interval 3 when the inductor current reaches zero and the diode turns
off to block reverse current. The time 𝜎 and capacitor voltage 𝑣𝐶((+𝑑𝑘 + 𝜎)𝑇𝑠), at the end of
Interval 2 can be solved for from (4.1) given 𝑖𝐿((𝑘 + 𝑑𝑘 + 𝜎)𝑇𝑠) = 0. Equation (4.1) is a
transcendental equation in 𝜎, so we utilize a Taylor series expansion about point 𝜎𝑜 =1
2(1 − 𝑑𝑘).
During Interval 3, the inductor current 𝑖𝐿 remains at zero and the capacitor continues to
discharge through the load resistor. With the resulting 𝜎 and the capacitor voltage 𝑣𝐶((𝑘 + 𝑑𝑘 +
𝜎)𝑇) at the end of Interval 2, the state at the end of switching period can be expressed as
𝑣𝐶((𝑘 + 1)𝑇𝑠) = exp (−1
𝑅𝐶(1 − 𝑑𝑘 − 𝜎)𝑇𝑠) 𝑣𝐶((𝑘 + 𝑑𝑘 + 𝜎)𝑇𝑠)
𝑖𝐿((𝑘 + 1)𝑇𝑠) = 0
39
4.2 Linearization of Discrete-Time Nonlinear Model
In mathematics, linearization means to find a linear approximation to a function at a
given point. In the study of dynamical systems, linearization is a method for assessing the local
stability of an equilibrium point of a system of nonlinear differential equations or discrete
dynamical systems [20].
With the state-space representation of both CCM and DCM discrete-time nonlinear
model, the approach of linearization is shown in this section.
4.2.1 Jacobian Matrix
The Jacobian matrix is an important matrix of analysis nonlinear system. If the function
𝐅(𝐱) is differentiable at a point 𝑝 = ( 𝑥1, … , 𝑥𝑛), then the Jacobian matrix defines a linear
map ℝ𝑛 → ℝ𝑛, which is the linear approximation of the function 𝐅(𝐱) near the point p.
The Jacobian matrix is defined as
𝐽𝐹( 𝑥1, 𝑥2 , … , 𝑥𝑛) = 𝜕𝐅
𝜕𝐱|𝐱𝑜
=
[ ∂𝐅1∂𝑥1
∂𝐅1∂𝑥2
…∂𝐅1∂𝑥𝑛
∂𝐅2∂𝑥1
∂𝐅2∂𝑥2
…∂𝐅2∂𝑥𝑛
⋮ ⋮ ⋱ ⋮∂𝐅𝑛∂𝑥1
∂𝐅𝑛∂𝑥2
…∂𝐅𝑛∂𝑥𝑛]
|
|
𝐱 = 𝐱𝑜
𝐅(x) ≈ 𝐅(𝐱𝑜) + 𝐉𝐅(𝐱𝑜)(𝐱 − 𝐱𝑜) + 𝑜(‖𝐱 − 𝐱𝑜 ‖)
With the Jacobian matrix, the nonlinear model of boost converter can be linearized at
operating points of interest.
40
4.2.2 Linearization of Discrete-Time Equivalent System
The linearization approach can be represented by following steps, where 𝐅(𝐱) is the state space
representation of boost converter, 𝐱 is the state vector of last operating period.
𝐲 = 𝐅(𝐱)
≈ 𝐅(𝐱)|𝐱𝑜 + ∂𝐅
∂𝐱|𝐱𝑜
(𝐱 − 𝐱𝑜)
𝐱′ = 𝐱 − 𝐱𝑜
𝐲′ = 𝐲 − 𝐱𝑜
𝐲′ + 𝐱𝑜 ≈ 𝐅(𝐱)|𝐱𝑜 + ∂𝐅
∂𝐱|𝐱𝑜
𝐱′
𝐲′ ≈ ∂𝐅
∂𝐱|𝐱𝑜
𝐱′ + 𝐅(𝐱)|𝐱𝑜 − 𝐱𝑜
𝐲′ + 𝐱∗ ≈ ∂𝐅
∂𝐱|𝐱𝑜
(𝐱′ + 𝐱∗ − 𝐱𝑜) + 𝐅(𝐱)|𝐱𝑜
𝐲′ ≈ ∂𝐅
∂𝐱|𝐱𝑜
𝐱′ + 𝐅(𝐱)|𝐱𝑜 +∂𝐅
∂𝐱|𝐱𝑜
(𝐱∗ − 𝐱𝑜) − 𝐱∗
The piecewise affine model can be represented as
𝐲′ ≈ 𝐀𝐱𝑜𝐱′ + 𝐁𝐱𝑜
where
𝐀𝐱𝑜 = ∂𝐅
∂𝐱|𝐱𝑜
𝐁𝐱𝑜 = 𝐅(𝐱)|𝐱𝑜 +∂𝐅
∂𝐱|𝐱𝑜
(𝐱∗ − 𝐱𝑜) − 𝐱∗.
41
4.3 Piecewise Affine System Model of Boost Converter
This section compares the piecewise affine system model of the boost converter without
modeling of diode reverse current blocking as in [7] and with modeling diode reverse current
blocking.
4.3.1 Piecewise Affine Model with Incomplete Diode Model
Take the piecewise affine model of [7]
𝐱[𝑘 + 1] =
{
[
0.4660 −0.0715−2.3361 −0.4130
] 𝐱[𝑘] + [ 1.5657−13.7547
] 𝑖𝑓 𝐅𝐱[𝑘] < −0.4,
[0.8621 0.0891−1.3648 0.2376
] 𝐱[𝑘] + [0.0747−4.0951
] 𝑖𝑓 − 0.4 ≤ 𝐅𝐱[𝑘] < −0.1,
[0.9667 0.0741−0.6847 0.6266
] 𝐱[𝑘] + [0.0000 0.0000
] 𝑖𝑓 − 0.1 ≤ 𝐅𝐱[𝑘] < 0.1,
[1.0036 0.0563−0.2216 0.9229
] 𝐱[𝑘] + [ 0.10932.7743
] 𝑖𝑓 𝐅𝐱[𝑘] ≥ 0.1
The operating points used for linearization are not given in [7], so we determined them by
minimizing the norm of the difference between the linearized model and the given piecewise
affine system matrices. The operating points relative to steady state were determined to be
𝐱𝑜1 = [ 20.5954 2.5505
], 𝐱𝑜2 = [ 9.9928 1.9469
], 𝐱𝑜3 = [ 0 0], 𝐱𝑜4 = [
1.0001 0.00026
].
The transient response of the piecewise affine system model without diode reverse
current blocking is shown in Figure 4-2.
42
Figure 4-2. Transient response of piecewise affine model without diode reverse current blocking.
Figure 4-3 shows the trajectory of the transient response of the piecewise affine system
model without diode reverse current blocking relative to the steady state operating point
x*=[5.0235 0.0323]T. The red dashed line in Figure 4-3 is introduced to indicate when the
inductor current 𝑖𝐿 equals to or saturate zero.
Figure 4-3. Transient response of piecewise affine model without diode reverse current blocking
relative to steady state. (b) Enlarged view around steady state operating point.
0 0.5 1 1.5 2 2.5 3 3.5 4
x 10-3
0
2
4
6
8Response for Piecewise Affine Modeling without Diode Reverse Current Blocking
vC (
V)
0 0.5 1 1.5 2 2.5 3 3.5 4
x 10-3
0
2
4
6
8
i L (
A)
t
-6 -4 -2 0 2-1
0
1
2
3
4
5
6
7
8
D4 D3 D2 D1
i L -
iL*
vC - v
C
*
Transient Response Relative to Steady State Piecewise Affine Modeling
without Diode Reverse Current Blocking
-0.5 0 0.5
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
D3 D2 D1
i L -
iL*
vC - v
C
*
Transient Response Relative to Steady State Piecewise Affine Modeling
without Diode Reverse Current Blocking
43
Figure 4-3 illustrates the state vector entering different domains and becoming stable in
domain 3 where 𝐛3 is a zero vector. The inductor current shown in Figure 4-3 goes below zero,
because diode reverse current blocking has not been modeled.
4.3.2 Piecewise Affine System Model with Complete Diode Model
When the diode is modeled completely, the piecewise affine model becomes
𝐱[𝑘 + 1] =
{
[
0.4660 −0.0715−2.3361 −0.4130
] 𝐱[𝑘] + [ 1.5657−13.7547
] 𝑖𝑓 𝐅𝐱[𝑘] < −0.4, 𝑖𝐿[𝑘] > 0
[0.8621 0.0891−1.3648 0.2376
] 𝐱[𝑘] + [0.0747−4.0951
] 𝑖𝑓 − 0.4 ≤ 𝐅𝐱[𝑘] < −0.1, 𝑖𝐿[𝑘] > 0
[0.9667 0.0741−0.6847 0.6266
] 𝐱[𝑘] + [0.0000 0.0000
] 𝑖𝑓 − 0.1 ≤ 𝐅𝐱[𝑘] < 0.1, 𝑖𝐿[𝑘] > 0
[1.0036 0.0563−0.2216 0.9229
] 𝐱[𝑘] + [ 0.10932.7743
] 𝑖𝑓 𝐅𝐱[𝑘] ≥ 0.1, 𝑖𝐿[𝑘] > 0
[1.0129 −0.00420 0
] 𝐱[𝑘] + [ −0.1477−0.0323
] 𝑖𝑓 𝑖𝐿[𝑘] < 0
where the operating points are chosen the same as Section 4.3.1, except for an additional one
associated with diode reverse current blocking
𝐱𝑜1 = [ 20.5954 2.5505
], 𝐱𝑜2 = [ 9.9928 1.9469
], 𝐱𝑜3 = [ 0 0], 𝐱𝑜4 = [
1.0001 0.00026
], 𝐱𝑜5 = [ 6 0].
The transient response of piecewise affine model with the diode modeled completely is
shown in Figure 4-4. The inductor current stays greater than zero.
44
Figure 4-4. Transient response of piecewise affine model with complete diode model.
Figure 4-5 shows the transient response of piecewise affine system model with the
complete diode model as a phase plane plot with the steady state point at the origin.
Figure 4-5. (a) Transient response of piecewise affine modeling with diode modeled properly relative
to steady state (b) Enlarged view of domain 3.
In Figure 4-5 the state vector switches into the discontinuous-conduction domain and
then switches back into Domain 3 then becomes stable. The inductor current 𝑖𝐿 goes below zero
0 0.5 1 1.5 2 2.5 3 3.5 4
x 10-3
0
2
4
6
8Response for Piecewise Affine Modeling with Diode Modeled Properly
vC (
V)
0 0.5 1 1.5 2 2.5 3 3.5 4
x 10-3
0
2
4
6
8
i L (
A)
t
-6 -4 -2 0 2-1
0
1
2
3
4
5
6
7
8
D5
D4 D3
D2
D1
i L -
iL*
vC - v
C
*
Transient Response Relative to Steady State Piecewise Affine Modeling
with Diode Modeled Properly
-0.5 0 0.5
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
D5
D1
i L -
iL*
vC - v
C
*
Transient Response Relative to Steady State Piecewise Affine Modeling
with Diode Modeled Properly
45
means state vector switches in to 𝐷5 then the current is forced to be zero by the state space
representation of 𝐷5.
Figure 4-6. State space switching sequence for PAS model with complete diode model.
In Figure 4-6, it shows the transient response keeps zero when the system operates on
discontinuous-conduction mode until it switches out the DCM domain into other domains.
4.4 Piecewise Affine System Modeling Guidelines
4.4.1 Selection of Domains
When generating the piecewise affine system model, the following tradeoffs should be
considered:
1. Increasing the number of domains should improve accuracy relative to the generalized state
spaces model. However, the complexity of the partitioning process increases as Nx. This
situation is even worse when the disturbance in introduced into the system. Because the more
domains established the less the disturbance is, at the same time, the less the domain
46
established the disturbance is larger. The complexity of the state space partition with
disturbance is determined by both domains number and disturbance scale.
2. As for the part of state space where the real system is seldom or never reached during real
operating, such as, the state space that leads the duty ratio saturate, the part that is too far
from the origin, and the state space parts are not covered by the restrict area Q. These state
space parts should be seen as entirety.
3. The domain where the steady state is located in, should be narrow for the better simulation
performance.
4.4.2 Selection of Operating Points
After the state space domains have been determined, the operating points to be used for
linearization must be selected. For example, in Domain 𝐷3 the operating point is chosen at state
vector that [𝑣𝐶 𝑖𝐿]𝑇 − 𝐱∗ = 0.
During the linearization of DCM model, the operating points should be chosen near the
state vector values where the discontinuous-conduction mode happens in the simulation of
generalized state space model in Figure 2-16.
4.5 Piecewise Affine System Controller Design
When the boost converter operates stably in CCM mode the duty cycle duty ratio can be
chosen to make the average output voltage equal to the reference voltage 𝑉𝑟𝑒𝑓. For the periodic
steady state, the average current, minimum instantaneous current, and maximum instanteous
current can be expressed,
47
𝐷 = 1 − 𝑉𝑑𝑉𝑜
𝐼𝐿 = 𝑉𝑜
𝑅𝑜 (1 − 𝐷)
∆𝐼𝐿 = 𝐷 𝑇𝑠 𝑉𝑑𝐿
𝑖𝐿(min) = 𝐼𝐿 − ∆𝐼𝐿2
𝑖𝐿(max) = 𝐼𝐿 + ∆𝐼𝐿2
However, for the purpose of voltage regulation a feedback controller should be designed
to realize the fast stable response, resistance to disturbance. A feedback control vector is given in
[7] without the derivations process. In this thesis a simple control synthesis is illustrated and
shown with a satisfactory performance.
Apply the periodic steady state result we can design a piecewise affine controller to
regulate the output voltage of the discrete-time nonlinear system. The piecewise affine controller
comes in the form:
𝑑[𝑘 + 1] = 𝐷 + 𝐅(𝐱[𝑘] − 𝐱∗)
The 𝐱[𝑘] includes the capacitor voltage and inductor current of the last period, 𝒙∗ =
[𝑉𝑜 𝑖𝐿(min)]𝑇 is the steady state capacitor voltage and inductor current, and 𝐷 is a constant
number. Control vector 𝐅 = [−𝛼(𝑉𝑜 , 𝑖𝐿(min), 𝑉𝑑) −𝛽(𝑉𝑜 , 𝑖𝐿(min), 𝑉𝑑)] can be derived by
applying the following principles:
When the last period state vector 𝐱[𝑘] is small, considering the worst case the state
vector 𝐱[𝑘] = [0 0]𝑇, then the output of controller should be a high duty ratio so that the input
48
voltage can charge the capacitor and inductor longer to get more energy and higher 𝑉𝑜𝑢𝑡. By this
idea we set 𝑑[𝑘 + 1] ≈ 0.9 when the last period output is 𝐱[𝑘] = [0 0]𝑇,
𝐷 + [−𝛼 −𝛽]([00] − [
𝑉𝑜𝑖𝐿(min)
]) ≈ 0.9 (4.1)
Furthermore α, β in the control vector should satisfy another equation
10𝑉𝑜
𝑉𝑑 ≈
𝛼𝑉𝑜
𝛽𝑖𝐿(min) (4.2)
By solving equations (4.1) and (4.2), we can get a feasible control vector 𝐅 = [−𝛼 −𝛽]
which has as a satisfactory control performance.
Example 6:
Continuing Example 1, we know
𝐷 = 1 − 1
5= 0.8
𝐼𝐿 = 5
30 (1 − 0.8)= 0.8333
∆𝑖𝐿 = 0.8 ∙ 20 ∙ 10−6 ∙ 1
10 ∙ 10−6= 1.6000
𝑖𝐿(min) = 0.8333 − 1.6000
2= 0.0333
Take 𝐱∗ = [𝑉𝑜
𝑖𝐿(min)] = [
50.0333
] as steady state and set this state as original point for
linearization convenient. The controller logic can be derived by the section of piecewise affine
controller design 𝐅 = [−0.0196 −0.0024]. The duty ratio of the switch is assumed to be
given by
49
𝑑𝑘 = {
0 𝑖𝑓 𝐅𝐱[𝑘] < −0.9
𝐅𝐱[𝑘] + 0.94 𝑖𝑓 − 0.94 ≤ 𝐅𝐱[𝑘] ≤ 0.05
1 𝑖𝑓 𝐅𝐱[𝑘] > 0.1
Then linearize the nonlinear dynamic system by selecting four operating points as shown
in the Figure 4-7. Select following operating points for linearization.
𝐱𝑜1 = [20.000050.0000
], 𝐱𝑜2 = [ 10.000020.0000
], 𝐱𝑜3 = [ 00], 𝐱𝑜4 = [
−10.0000−0.5000
].
Figure 4-7. Operating points for linearization.
The zero-order hold equivalent discrete-time nonlinear model of this system is obtained
as,
𝐱[𝑘 + 1] =
{
[
0.3930 0.2540−2.6185 0.6112
] 𝐱[𝑘] + [ 9.7901 30.1366
] 𝑖𝑓 𝐅𝐱[𝑘] < −0.4,
[0.8380 0.1651−1.5130 0.8431
] 𝐱[𝑘] + [0.71225.7875
] 𝑖𝑓 − 0.4 ≤ 𝐅𝐱[𝑘] < −0.1,
[0.9682 0.0791−0.5891 0.9605
] 𝐱[𝑘] + [0.0000 0.0000
] 𝑖𝑓 − 0.1 ≤ 𝐅𝐱[𝑘] < 0.1,
[0.9989 0.00260.1880 1.0232
] 𝐱[𝑘] + [ 0.05873.9187
] 𝑖𝑓 𝐅𝐱[𝑘] ≥ 0.1,
where 𝐅 = [−0.0196 −0.0024].
-5 0 5 10 15 20
-20
-10
0
10
20
30
40
50 O1
O2
O3 O4
Operating Points for linearization
v C
i L
50
The model is comprised of four affine subsystems where each subsystem is active at
instant of time if and only if the state at that time belongs to a subset of the state space.
By applying the control synthesis when input voltage 𝑉𝑑 = 1 V, output voltage 𝑉𝑜 = 5 V,
with the discrete-time piecewise affine model, the simulation of transient response of the boost
converter is shown in Figure 4-8.
Figure 4-8. Transient response of piecewise affine system model.
Compared with the performance of digital PWM nonlinear model simulation (Figure 4-
9), it shows the piecewise affine model control synthesis is validated and able to regulate the
output voltage of the boost converter.
0 1 2 3 4 5 6 7 8
x 10-3
0
5
10
Response for Piecewise Affine Model
vC
(V)
0 1 2 3 4 5 6 7 8
x 10-3
0
5
10
15
iL (A)
t(s)
51
Figure 4-9. Transient response of boost converter generalized state space model with complete diode
model.
When the input voltage 𝑉𝑑 = 1 V and output voltage 𝑉𝑜 = 6 V, by applying the control
synthesis, the simulation results of two kinds of systems in Figure 4-10 and Figure 4-11 shows
the approach is still feasible in voltage regulation of boost converter.
Figure 4-10. Transient response of piecewise affine system model.
-5
0
5
10
vC
(V
)
Transient Response of Boost Converter Generalized State Space Modeling with Diode Modeled Properly
0 0.002 0.004 0.006 0.008 0.01 0.012-5
0
5
10
15
i L (
A)
t
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016
0
5
10
Response for Piecewise Affine Model
vC
(V)
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.0160
5
10
15
iL (A)
t(s)
52
Figure 4-11. Transient response of boost converter generalized state space model with complete diode
model.
4.6 State Space Partition for Boost Converter with Incomplete Diode Model
Consider on the piecewise affine model on boost converter of [7], the system (𝒮,𝒟) can
be repressed as, 𝑁 = 4 where 𝒮 is defined by
𝐀1 = [ 0.4660 −0.0715−2.3361 −0.4130
] , 𝐛1 = [ 1.5657−13.7547
]
𝐀2 = [0.8621 0.0891−1.3648 0.2376
] , 𝐛2 = [0.0747−4.0951
]
𝐀3 = [0.9667 0.0741−0.6847 0.6266
] , 𝐛3 = [0.0000 0.0000
]
𝐀4 = [1.0036 0.0563−0.2216 0.9229
] , 𝐛4 = [ 0.10932.7743
]
and 𝒟 is defined by,
𝐷1 = {[𝑥1 𝑥2]𝑇 ∈ ℝ2 ∶ 𝐅𝐱 < −0.4},
𝐷2 = {[𝑥1 𝑥2]𝑇 ∈ ℝ2 ∶ −0.4 ≤ 𝐅𝐱 < −0.1},
-5
0
5
10
15
vC
(V
)
Transient Response of Boost Converter Generalized State Space Modeling with Diode Modeled Properly
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016-10
0
10
20
i L (
A)
t
53
𝐷3 = {[𝑥1 𝑥2]𝑇 ∈ ℝ2 ∶ −0.1 ≤ 𝐅𝐱 < 0.1}.
𝐷4 = {[𝑥1 𝑥2]𝑇 ∈ ℝ2 ∶ 𝐅𝐱 ≥ 0.1}.
The boundary for equation (3.7) is defined as a polygon whose vertices are,
𝑄 = [1.8 −1.8 −1.8 1.82 2 −2 −2
]
By applying the algorithm introduced above, the 𝐿 − 𝑝𝑎𝑡ℎ partitions of 𝑄 for 𝐿 = 0,… , 7
are shown in the Figure 4-12.
𝒟0(𝑄) 𝒟1(𝑄)
𝒟2(𝑄) 𝒟3(𝑄)
-4 -3 -2 -1 0 1 2 3 4-3
-2
-1
0
1
2
3
D4
D3 D2
iL - i
L
*
vC
- vC
*
D0
D4
D3 D2
D4
D3 D2
-4 -3 -2 -1 0 1 2 3 4-3
-2
-1
0
1
2
3
D1
D33
D43
D4
D3 D2
iL - i
L
*
vC
- vC
*
-4 -3 -2 -1 0 1 2 3 4-3
-2
-1
0
1
2
3
D2
D333
D433
D4
D3 D2
iL - i
L
*
vC
- vC
*-4 -3 -2 -1 0 1 2 3 4
-3
-2
-1
0
1
2
3
D3
D3333
D4333
D4
D3 D2
iL - i
L
*
vC
- vC
*
54
𝒟4(𝑄) 𝒟5(𝑄)
𝒟6(𝑄) 𝒟7(𝑄)
Figure 4-12. State space partitions of boost converter CCM.
It turns out that the partition 𝒟5(𝑄) is invariant with 𝐷333333(𝑄) and 𝐷3333333(𝑄)
sharing the same interior. The state vectors in the invariant graph in 𝐐 generate a unique
admissible switching sequence 𝜃 = (3,3, … ). Because the spectral radius of 𝐀3 is less than one,
and the affine term 𝐛3 is zero [7], we conclude that the piecewise affine system (𝒮,𝒟) in
Example 2 is uniformly exponentially stable on the invariant area in Figure 4-12.
-4 -3 -2 -1 0 1 2 3 4-3
-2
-1
0
1
2
3
D4
D33333
D43333
D4
D3 D2
iL - i
L
*
vC
- vC
*-4 -3 -2 -1 0 1 2 3 4
-3
-2
-1
0
1
2
3
D5
D333333
D433333
D4
D3 D2
iL - i
L
*
vC
- vC
*
-4 -3 -2 -1 0 1 2 3 4-3
-2
-1
0
1
2
3
D6
D3333333
D4333333
D4
D3 D2
iL - i
L
*
vC
- vC
*-4 -3 -2 -1 0 1 2 3 4
-3
-2
-1
0
1
2
3
D7
D33333333
D43333333
D4
D3 D2
iL - i
L
*
vC
- vC
*
55
4.7 State Space Partition for Boost Converter with Complete Diode Model
Continue on the refined piecewise affine model on boost converter with diode modeled
properly, the system (𝒮,𝒟) can be repressed as, 𝑁 = 5 where 𝒮 is defined by
𝐀1 = [ 0.4660 −0.0715−2.3361 −0.4130
] , 𝐛1 = [ 1.5657−13.7547
]
𝐀2 = [0.8621 0.0891−1.3648 0.2376
] , 𝐛2 = [0.0747−4.0951
]
𝐀3 = [0.9667 0.0741−0.6847 0.6266
] , 𝐛3 = [0.0000 0.0000
]
𝐀4 = [1.0036 0.0563−0.2216 0.9229
] , 𝐛4 = [ 0.10932.7743
]
𝐀5 = [1.0129 −0.00420 0
] , 𝐛5 = [ −0.1477−0.0323
]
and 𝒟 is defined by,
𝐷1 = {[𝑥1 𝑥2]𝑇 ∈ ℝ2: 𝐅𝐱(𝑘𝑇) < −0.4, 𝑖𝐿(𝑘𝑇) > 0},
𝐷2 = {[𝑥1 𝑥2]𝑇 ∈ ℝ2 : − 0.4 ≤ 𝐅𝐱(𝑘𝑇) < −0.1, 𝑖𝐿(𝑘𝑇) > 0 },
𝐷3 = {[𝑥1 𝑥2]𝑇 ∈ ℝ2: −0.1 ≤ 𝐅𝐱(𝑘𝑇) < 0.1, 𝑖𝐿(𝑘𝑇) > 0}.
𝐷4 = {[𝑥1 𝑥2]𝑇 ∈ ℝ2 ∶ 𝐅𝐱(𝑘𝑇) ≥ 0.1, 𝑖𝐿(𝑘𝑇) > 0}.
𝐷5 = {[𝑥1 𝑥2]𝑇 ∈ ℝ2: 𝑖𝐿(𝑘𝑇) < 0}.
The boundary for (3.7) is defined as a polygon whose vertices are
𝑄 = [1.8 −1.8 −1.8 1.82 2 −2 −2
]
The 𝐿 − 𝑝𝑎𝑡ℎ partitions of 𝑄 for 𝐿 = 1,… , 8 are shown in Figure 4-13
56
𝒟1(𝑄) 𝒟2(𝑄)
𝒟3(𝑄) 𝒟4(𝑄)
𝒟5(𝑄) 𝒟6(𝑄)
-2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
D33
D35
D53
D5
D3 D2
iL - i
L
*
vC
- vC
*
D1
-2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
D333
D335
D353
D533 D535
D5
D3 D2
iL - i
L
*
vC
- vC
*
D2
57
𝒟7(𝑄) 𝒟8(𝑄)
𝒟14(𝑄)
58
𝑒𝑛𝑙𝑎𝑟𝑔𝑒𝑚𝑒𝑛𝑡 𝑜𝑓 𝒟14(𝑄)
𝑒𝑛𝑙𝑎𝑟𝑔𝑒𝑚𝑒𝑛𝑡 𝑜𝑓 𝒟14(𝑄)
Figure 4-13. State space partitions of piecewise affine system model with complete diode model.
59
In the enlargement figure of 𝒟14(𝑄) the invariant subdomains 𝐷…33333….(𝑄) becomes
larger and remains invariant. As the path level becomes greater, the number of invariant
subdomains becomes larger. Finally, the small area P will be invariant with switching sequence
𝜃 = (… , 3,3, … ). Because the spectral radius of 𝐀3 is less than one, and the affine term 𝐛3 =
[0 0]𝑇 , we conclude that the piecewise affine system (𝒮,𝒟) in is uniformly exponentially stable
on the invariant area in Figure 4-13.
4.8 State Space Partition for Boost Converter with Disturbance
Since the piecewise affine model is a linearization of the generalized state space model
on certain operating points, there is a difference between the response of the models. This
difference is show in Figure 4-14 and Figure 4-15.
Figure 4-14. Transient simulation of piecewise affine system model and generalized state space model.
0 0.5 1 1.5 2 2.5 3 3.5 4
x 10-3
0
2
4
6
8Voltage Response of Generalized State Space Model and Piecewise Affine Model CCM
GSSM
PASM
0 0.5 1 1.5 2 2.5 3 3.5 4
x 10-3
-5
0
5
10Current Response of Generalized State Space Model and Piecewise Affine Model CCM
GSSM
PASM
60
Figure 4-15. Voltage error and current error between piecewise affine system model and generalized
state space model.
Errors between the two models dimishes to zero as the simulation time increases. The
deviation can be treated as a kind of disturbance in the piecewise affine system modeling and
stability analysis in [7].
Continue on state space partition on boost converter without diode current blocking
modeled with the disturbance 𝑊 which is represented as polygon
[17 17]𝑇
, [−1
7 17]𝑇
, [−1
7 − 1
7]𝑇
and [17 − 1
7]𝑇
.
By applying the algorithm introduced above, the 𝐿 − 𝑝𝑎𝑡ℎ partitions of 𝑄 for 𝐿 = 1 is
shown in the Figure 4-16.
0 0.5 1 1.5 2 2.5 3 3.5 4
x 10-3
-3
-2
-1
0
1
2
3
4
5Voltage and Current Error Between PWAM and GSSM
Voltage Error
Current Error
61
(a) �̃�1 (b) 𝒟1
(c) �̃�2 (d) 𝒟2
62
(e) �̃�3 (f) 𝒟3
(g) �̃�4
Figure 4-16. Several partitions and refinements of piecewise affine system.
𝒟1 is a refinement of �̃�1 by finding the minterms 𝐷5 contains the swithing sequence
{(3,2), (3,3), (3,4)}, 𝐷6 contains {(3,2), (3,3)}, 𝐷7 contains {(3,3), (3,4)}, 𝐷8 contains
{(4,2), (4,3), (4,4)}. Further refinment 𝒟2 of �̃�2 is shown in Figure 4-16-(b). The swithing
sequence of 𝐷9, 𝐷10, 𝐷11, 𝐷12, 𝐷12 are the same as { (3,3,2), (3,3,3), (3,3,4}. The 𝐷14 contains
63
the swithing sequnce as {(4,3,2), (4,3,3), (4,3,4)}. The switching sequnce in 𝒟3 come of
𝐷15~𝐷27 are the same as {(3,3,3,2), (3,3,3,3), (3,3,3,4)}; 𝐷28, 𝐷29 contains {(4,3,3,2),
(4,3,3,3), (4,3,3,4)}.
The state space partition in the restrict area 𝑄 which is in the original domains 𝐷3,
𝐷4 and switching sequence (3,3,3,3, … ) and (4,3,3,3,…) is include in all the subpartitions.
The switching sequence (3,3,3, … ) and (4,3,3,3,…)will be continue with the new partitions
and refinements. Then the system can be stable as satisfying the stability criteria [7].
4.9 Piecewise Affine System Analysis on Boost Converter Operating in DCM
This section shows the implementation of piecewise affine system analysis method on the
boost converter when operating in discontinuous–conduction mode.
If the load resistor for the boost converter in [6] is increased to 𝑅𝑜 = 90 Ω, the converter
operates in discontinuous-conduction mode. Figure 4-17 demonstrates the transient response of
generalized state space modeling approach of Section 3.2 with the same control law of [6].
Figure 4-17. Transient response of GSSM with complete diode model operating in DCM.
-5
0
5
10
vC
(V
)
Transient Response of Generalized State Space Modeling without Diode Reverse Current Blocking
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02-5
0
5
10
i L (
A)
t
64
Figure 4-18. Steady state response of GSSM with complete diode model operating on DCM.
Figure 4-18 shows the steady state response of generalized state space modeling boost
converter operating on discontinuous-conduction mode. The steady state vector is
𝒙∗ = [7.284 0]𝑇.
Continue to construct the piecewise affine system model with complete diode modeled by
reproducing the procedure of Section 4.3. The original domains are chosen as,
𝐷1 = {[𝑥1 𝑥2]𝑇 ∈ ℝ2: 𝐅𝐱(𝑘𝑇) < −0.4, 𝑖𝐿(𝑘𝑇) > 0.5},
𝐷2 = {[𝑥1 𝑥2]𝑇 ∈ ℝ2 : − 0.4 ≤ 𝐅𝐱(𝑘𝑇) < −0.1, 𝑖𝐿(𝑘𝑇) > 0.5 },
𝐷3 = {[𝑥1 𝑥2]𝑇 ∈ ℝ2: −0.1 ≤ 𝐅𝐱(𝑘𝑇) < 0.1, 𝑖𝐿(𝑘𝑇) > 0.5}.
𝐷4 = {[𝑥1 𝑥2]𝑇 ∈ ℝ2 ∶ 𝐅𝐱(𝑘𝑇) ≥ 0.1, 𝑖𝐿(𝑘𝑇) > 0.5}.
𝐷5 = {[𝑥1 𝑥2]𝑇 ∈ ℝ2: 𝑖𝐿(𝑘𝑇) < 0.5}.
with operating points
𝐱𝑜1 = [ 17.2839 10.0000
], 𝐱𝑜2 = [ 12.2839 4.0000
], 𝐱𝑜3 = [ 5.2840 2.0000
], 𝐱𝑜4 = [ −2.716 −0.5000
],
7.285
7.29
7.295
7.3
7.305
7.31
vC
(V
)
Steady State Response of Generalized State Space Modeling without Diode Reverse Current Blocking
0.0126 0.0127 0.0127 0.0128 0.0128 0.0129 0.01290
0.5
1
i L (
A)
t
65
𝐱𝑜5 = [ 7.2840 0
].
The piecewise affine system model is constructed by linearizing the generalized state
space model at the chosen operating points and is represented as
𝐱[𝑘 + 1] =
{
[
0.4153 0.0204−2.5229 −0.3933
] 𝐱[𝑘] + [ 3.59269.0893
] 𝑖𝑓 𝐅𝐱[𝑘] < −0.4, 𝑖𝐿[𝑘] > 0.5
[0.7604 0.0879−1.7767 0.0350
] 𝐱[𝑘] + [0.41090.6456
] 𝑖𝑓 − 0.4 ≤ 𝐅𝐱[𝑘] < −0.1, 𝑖𝐿[𝑘] > 0.5
[0.9624 0.1202−0.9059 0.5743
] 𝐱[𝑘] + [−0.0889 −2.1886
] 𝑖𝑓 − 0.1 ≤ 𝐅𝐱[𝑘] < 0.1, 𝑖𝐿[𝑘] > 0.5
[1.0118 0.01070.2054 1.1932
] 𝐱[𝑘] + [ 0.12214.0223
] 𝑖𝑓 𝐅𝐱[𝑘] ≥ 0.1, 𝑖𝐿[𝑘] > 0.5
[0.9934 0.03410 0
] 𝐱[𝑘] + [ 00] 𝑖𝑓 𝑖𝐿[𝑘] < 0.5
Figure 4-19 shows the transient response of piecewise affine modeling boost converter
with diode model operating on discontinuous-conduction mode.
Figure 4-19. Transient response of piecewise affine system model with complete diode model.
The similarity of the transient responses shown in Figures 4-17 and 4-19 indicates the
operating points are chosen properly. Furthermore, Figure 4-20 shows the transient response of
boost converter operating in discontinuous-conduction mode using a piecewise affine system
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.020
2
4
6
8Response for Piecewise Affine Modeling with Diode Modeled Properly
vC (
V)
0 0.002 0.004 0.006 0.008 0.01 0.0120
5
10
15
20
i L (
A)
t
66
model with the complete diode model as a phase plane plot with the steady state point at the
origin.
Figure 4-20. Transient response of piecewise affine system model with diode modeled completely
relative to steady state.
In Figure 4-20 the state vector switches into the discontinuous-conduction domain 𝐷5 and
remains in 𝐷5 as the boost converter operates in discontinuous-conduction mode.
With the state space partition method of Section 4.5 and define the boundary of (3.7) as a
polygon whose vertices are
𝑄 = [1.8 −1.8 −1.8 1.82 2 −2 −2
]
the 𝐿 − 𝑝𝑎𝑡ℎ partitions of 𝑄 for 𝐿 = 1,… , 12 are shown in Figure 4-21.
-8 -6 -4 -2 0 2
0
2
4
6
8
10
D5
D4 D3
D2
D1
i L -
iL*
vC - v
C
*
Transient Response Relative to Steady State Piecewise Affine Modeling
with Diode Modeled Properly
67
𝒟1(𝑄) 𝒟2(𝑄)
𝒟3(𝑄) 𝒟4(𝑄)
𝒟5(𝑄) 𝒟6(𝑄)
68
𝒟7(𝑄) 𝒟8(𝑄)
𝒟9(𝑄) 𝒟10(𝑄)
69
𝒟11(𝑄) 𝒟12(𝑄)
Figure 4-21. State space partitions of boost converter DCM.
The patterns in Figure 4-21 shows the subpartitions in 𝒟11(𝑄) and 𝒟11(𝑄) are invariant.
The state vectors in the invariant graph in 𝐐 generate a unique admissible switching
sequence 𝜃 = (… ,5,5, … ). Because the spectral radius of 𝐀5(1,1) is less than one, and the affine
term 𝐛5 is zero [7], we conclude that the piecewise affine system (𝒮, 𝒟) of boost converter that
operating in discontinuous-conduction mode is uniformly exponentially stable on the invariant
area in Figure 4-21. Additionally, this section shows that the piecewise affine system theory
analysis method can model and simulate power electronic converters that operating in
discontinuous-conduction mode with the diode modeled completely.
70
Chapter 5
Conclusion
5.1 Summary
In this project, the piecewise affine system (PAS) modeling and stability analysis
procedures described in [7] were applied to a boost dc-to-dc power converter. Computer codes
for this purpose were developed from algorithms in [7] and were validated by reproducing the
results of several examples from the same source. A PAS model of a boost converter in [7] that
had been adapted from [6] was shown to be incomplete in the sense that diode reverse current
blocking had not been modeled. An augmented model that includes diode reverse current
blocking was created and analyzed for stability.
5.2 Future Work
There are three obvious research directions emanating from this project. First, with
regard to having to model CCM and DCM operation of single-switch converters separately, is
there a systematic approach to relaxing the dependence of the initial PAS model on the choice of
operating points? Second, with regard to control synthesis, how can PAS modeling be used to
design digital controllers with performance that exceeds conventional analog controllers over a
range of operating conditions. Third, how can the computational complexity of the PAS stability
analysis be addressed.
Appendix
Test file
%==========================================================
% State space partition on Boost Converter that piecewise
affine modeled
% with/without diode in the circuit.
%
% [1] Based on the modeling approach of piecewise affine
system by
% Mirzazad-Barijough, S., On Analysis of Discrete-Time
Piecewise
% Affine Systems, Ph.D. dissertation Penn State
University, 2012. pp.21
%
% Mirzazad-Barijough, S. and J-W Lee, On Stability and
Performance
% Analysis of Discrete-Time Piecewise Affine Systems,
49th IEEE
% Conference on Decision and Control, 2010.
%
% [2] Improved the model by modeling the diode which is
common in real
% power electronic converter then adding the
linearization of
% discontineous-conduction mode as a domian.
%
%==========================================================
test = 5 % select test example
if test == 1
N = 4;
level = 7;
q = [1.8 -1.8 -1.8 1.8
2 2 -1 -1];
W = 0;
72
elseif test == 2
N = 4;
level = 3;
q = [1.8 -1.8 -1.8 1.8
2 2 -2 -2];
W = 1/7;
elseif test == 3
N = 4;
level = 10;
q = [2 -2 -2 2
2 2 -2 -2];
W = 0;
elseif test == 4
N = 4;
level = 3;
q = [1.8 -1.8 -1.8 1.8
2 2 -2 -2];
W = 1/10;
elseif test == 5
N = 5;
level = 15;
q = [1.8 -1.8 -1.8 1.8
2 2 -1 -1];
W = 0;
end
%% Define piecewise affine system model.
A = cell(1, N);
b = cell(1, N);
A_D = cell(1, N);
b_D = cell(1, N);
A{1} = [0.4660, -0.0715; -2.3361, -0.4130];
A{2} = [0.8621, 0.0891; -1.3648, 0.2376];
A{3} = [0.9667, 0.0741; -0.6847, 0.6266];
A{4} = [1.0036, 0.0563; -0.2216, 0.9229];
73
b{1} = [1.5657; -13.7547];
b{2} = [0.0747; -4.0951];
b{3} = [0; 0];
b{4} = [0.1093; 2.7743];
F = [-0.0291 -0.0356]; % control law
if N == 4 % parameters of modeling without diode
A_D{1} = [zeros(1,2); F];
A_D{2} = [-F; F];
A_D{3} = [-F; F];
A_D{4} = [-F; zeros(1,2)];
b_D{1} = [0; -0.4];
b_D{2} = [0.4; -0.1];
b_D{3} = [0.1; 0.1];
b_D{4} = [-0.1; 0];
elseif N == 5 % parameters of modeling with diode
A{5} = [1.012982343222489, -0.004220119262431; 0, 0];
b{5} = [ -0.147660200984055; -0.032300000000000];
A_D{1} = [zeros(1,2); F; 0 -1];
A_D{2} = [-F; F; 0 -1];
A_D{3} = [-F; F; 0 -1];
A_D{4} = [-F; zeros(1,2); 0 -1];
A_D{5} = [0 1; 0 0; 0 0];
b_D{1} = [0; -0.4; 0.0323-1e-3];
b_D{2} = [0.4; -0.1; 0.0323-1e-3];
b_D{3} = [0.1; 0.1; 0.0323-1e-3];
b_D{4} = [-0.1; 0; 0.0323-1e-3];
b_D{5}= [-0.0323+1e-3; 0; 0];
else
disp('N must be 4 or 5')
keyboard
end
%% Construct symbolic model.
D0 = cell(1, N);
for n = 1:N
D0{n}.index = n;
D0{n}.A = A_D{n};
D0{n}.b = b_D{n};
74
D0{n}.vertices = [];
end
% Initialize subdomain serial number set V0.
V0 = 1:N;
% Initialize switching sequence (i0 i1 i2 i3 i4 ...).
M0 = cell(1, N);
for n = 1:N
M0{n}.swq = n;
M0{n}.num = n;
end
%% Partition state space.
partition_state_space(A, b, D0, V0, M0, q, W, level)
partition_state_space
function partition_state_space(A, b, D0, V0, M0, q, W,
level)
count = 0;
for nn = 1:level
count = count + 1
D1_tilde ...
=
partition_piecewise_affine_system_with_disturbance( ...
A, b, D0, V0, M0, q, W);
%% Eliminate empty domains.
N = length(D1_tilde);
keep = true(1, N);
for i = 1:N
if isempty(D1_tilde{i}.vertices) ||
size(D1_tilde{i}.vertices, 2) < 3
keep(i) = false;
end
end
75
D1_tilde = D1_tilde(keep);
%% Find minterms of overlapping domains.
if W == 0
minterms = D1_tilde;
else
minterms = minterms_finder(D1_tilde, D0, V0);
end
%% Construct D1 and V1.
D1 = cell(1, length(minterms));
V1 = [];
for i = 1:length(minterms) % copy minterms to D1 and
construct V1
D1{i}.sq = max(V0) + i;
V1 = [V1 D1{i}.sq];
D1{i}.A = minterms{i}.A;
D1{i}.b = minterms{i}.b;
D1{i}.vertices = minterms{i}.vertices;
end
%% M1{}
M1 = M_generator(minterms, D1, D1_tilde, M0, V0);
%% Plot the partition figure.
num = plot_figure(D1, nn, M1);
%% Copy S1 information to S0.
D0 = D1;
V0 = V1;
M0 = M1;
end
end
76
partition_piecewise_affine_system_with_disturbance
%==========================================================
% function: partition =
piecewise_affine_system_state_space_partition(...
%
A,b,D_0,V_0,M_0,disp_zone,Q,W)
% inputs: A,b( pieceswise affine system state state spcae
representation)
% D_0( last partition subdomain's information)
% V_0( last partition subdomain's serial number
set)
% M_0( last partition subdomain's real switching
sequence)
% Q( restrict area)
% W( disturbance)
% output: partition( D_tilde information: inequality
functions,
% polygon vertexes, switch sequence
number of subdomains)
%==========================================================
function partition ...
=
partition_piecewise_affine_system_with_disturbance( ...
A, b, D0, V0, M0, q, W)
%% Convert boundary polygon to inequalities.
[A_q, b_q] = polygon2inequalities(q);
%% Copy subdomain inequalities from previous partition.
M = length(D0);
A_D0 = cell(1, M);
b_D0 = cell(1, M);
for i = 1:M
A_D0{i} = D0{i}.A;
b_D0{i} = D0{i}.b;
end
%% Add disturbance.
b_W = cell(1, M);
for i = 1:M
77
b_W{i} = b_D0{i} + ones(size(b_D0{i}))*W;
end
%% inequality function generator and solver
swi_sq = cell(1, M^2);
% generate switching sequence for new partition in V_0 name
n = 1;
for i = 1:M
for j = 1:M
swi_sq{n} = [V0(i) V0(j)];
n = n + 1;
end
end
% calculate the subdomain vertices of new partition:
% by combine all the last partition's subdomain_A's and
subdomain_B's
% inequalty fucntions to detect if there is solvable; also
the combination
% of twosubdomains should be reasonable by real switching
sequence of M_0
% exapmle: real switching {1,2} can not be combined with
{1,3}
% even if there is solution of combined inequalty functions
sub_domain = cell(1, M^2);
for i = 1:M^2
MM = [];
sq = swi_sq{i};
for j = 1:M % find last partition subdomin_A in
which original domain
if M0{j}.num == sq(1)
D_start = M0{j}.swq(1,1);
break
end
end
sw_start = sq(1);
sw_end = sq(2);
if length(M0{1}.swq(1,:)) == 1 % incase the level 1
MM = [sw_start sw_end];
end
78
if length(M0{1}.swq(1,:)) > 1
for j = 1:length(M0) % find sw_start's
real swithing sequence
if M0{j}.num == sq(1) % when there is
disturbance the M_0{j} have more then one lines
sq1 = M0{j}.swq;
break
end
end
for j = 1:length(M0) % find sw_end's
real swithing sequence
if M0{j}.num == sq(2)
sq2 = M0{j}.swq;
break
end
end
% find all the reasonable
% switching sequence. such as,
% {1,2,3} and {2,3,4} can combine
% as {1,2,3,4}
for sq1_i = 1:size(sq1,1)
for sq2_i = 1:size(sq2,1)
aa = sq1(sq1_i,:);
bb = sq2(sq2_i,:);
if isequal(aa(2:end), bb(1:(end - 1)))
MM = [MM; aa, bb(end)];
end
end
end
% -------------------
end
if ~isempty(MM)
% combine inquality functions of 2 subdomain and restrict
area
sub_domain{i}.A ...
= [
A_D0{sw_end - V0(1) + 1}*A{D_start};
A_q*A{D_start};
A_q;
A_D0{sw_start - V0(1) + 1}
79
];
sub_domain{i}.b ...
= [
b_W{sw_end - V0(1) + 1} - A_D0{sw_end -
V0(1) + 1}*b{D_start};
b_q - A_q*b{D_start};
b_q;
b_D0{sw_start - V0(1) + 1}
];
% Solve the inequality functions
sub_domain{i}.vertices ...
= inequality_function_solver_R2_bounded( ...
sub_domain{i}.A, sub_domain{i}.b);
if ~isempty(sub_domain{i}.vertices)
sub_domain{i}.vertices ...
= simplify_vertex(sub_domain{i}.vertices);
% cancel the duplicate points
if size(sub_domain{i}.vertices,2) > 2
% make sure the vertexes can make up polygon
[RR, kk] =
polygon2inequalities(sub_domain{i}.vertices); % simplify
the inequality fucntions
sub_domain{i}.A = RR;
sub_domain{i}.b = kk;
end
end
sub_domain{i}.sq = sq;
else
sub_domain{i}.A = [];
sub_domain{i}.b = [];
sub_domain{i}.vertices = [];
sub_domain{i}.sq = [];
end
end
partition = sub_domain;
end
80
inequality_function_solver_R2_bounded
%==========================================================
% Solve the inequality functions in form C*x <= D && R*x
<=k and get the
% feasible area vertexes.
% inputs: C,d( partation inequality functions)
% disp_zone( display zone)
% output: vertexes of the partation or return empty set
%
% comment: since the partition includes the restrict area
Q, the partition
% is bounded
%==========================================================
function
draw_points_convex=inequality_function_solver_R2_bounded(C,
d)
%% caculate intersection dots between inenquality functions
function_num = length(d);
intersection_points = [];
for i = 1:function_num
for j = (i+1):function_num
A = [C(i, :); C(j, :)];
if rank(A) < 2
continue;
end
b = [d(i); d(j)];
point = A\b;
intersection_points = [intersection_points point];
end
end
81
%% copy points that satisfy the inequality functions
output_points=[];
s2 = size(intersection_points,2);
for i=1:1:s2
flag = 1;
ww = C*intersection_points(:,i)-d;
for j=1:function_num
if ww(j,1)> 1e-9% matlab can not identify 0 == 0.00
flag=0;
break;
end
end
if flag
output_points=[output_points
intersection_points(:,i)];
end
end
%% cancel duplicate and rearrange points to be clockwise
draw_points_convex = [];
if ~isempty(output_points)
draw_points_convex = simplify_vertex(output_points);
end
end
simplify_vertex
%==========================================================
% simplify polygon points: cancel dulpicate points and 3
points in a line
82
% arange the points to be clockwise for patch function
working properly
%==========================================================
function simplify_convex = simplify_vertex(vertex)
simplify_convex = [];
N = size(vertex, 2);
if N == 0
return
end
%% Cancel duplicate points.
output_points = vertex(:,1);
for i = 1:N
flag = 1;
for j = 1: size(output_points,2)
AA = vertex(:,i) - output_points(:,j);
if abs( AA(1) ) < 1e-9 && abs( AA(2) ) < 1e-
9 % matlab can mot identify 0 == 0.00
flag = 0;
break
end
end
if flag
output_points = [output_points vertex(:,i)];
end
end
%% Order points and check for convexity.
if ~isempty(output_points) && size(output_points,2) >
2 % if output_points is empty then skip arrange to be
convex
ss2 = size(output_points, 2);
points_central = mean(output_points, 2);
points = [];
for i = 1:1:ss2
angle1 = double( atan2( output_points(2,i)-
83
points_central(2) , output_points(1,i)-
points_central(1) ) ); % force to double is essential
point = [output_points(:,i); angle1 ];
points = [points point];
end
points = points';
points = sortrows(points,3)'; % arrange the points
by the angle to the center points
simplify_convex = double( points([1 2],: ) );
end
end
polygon2inequalities
%==========================================================
% POLYGON2INEQUALITIES Map polygon to inequalities.
% Map a polygon to a corresponding set of inequalities in
R2.
% The inequalities will be in simple form, if and only if
the polygon
% is strictly convex (i.e., no repeated vertices or co-
linear sides).
%
% [A, b] = POLYGON2INEQUALITIES(p) returns a set of
inequalities
% represented by matrix A and vector b (Ax < b) that
corresponds to
% a polygon with vertices specified as columns of matrix p.
The rows
% of A and b are ordered to match the vertices of the
polygon, with
% the intersection of the first two inequalities
corresponding to the
% first vertex of the polygon.
%==========================================================
function [A, b] = polygon2inequalities(p)
%% Check polygon to ensure it is in R2.
[M, N] = size(p);
84
if M ~= 2
error('polygon2inequalities:notR2', 'Not R2.');
end
%% Construct inequalities from polygon edges.
p = [p(:, end) p]';
A = [diff(p(:,2)) -diff(p(:,1))];
b = A(:,1).*p(1:N, 1) + A(:,2).*p(1:N, 2);
%% Normalize matrix and vector.
w = max(abs(A), [], 2);
A = repmat(1./w, 1, 2).*A;
b = b./w;
end
%==========================================================
% 2013-11-21 JSM Created.
%==========================================================
minterms_finder
%==========================================================
% This function is designed to find minterms of the
overlaping partitions
% based on the fact that the partitions do not have
nonconvex terms
%==========================================================
function D1 = minterms_finder(D1_tilde, D0, V0)
D1 = [];
%% Detect which D1_tilde subdomains belong in each D0
subdomain.
N = length(D0)
for i = 1:N
InD = [];
for j = 1:length(D1_tilde)
85
if D1_tilde{j}.sq(1) == V0(i)
InD = [InD j];
end
end
in_D0{i} = InD;
InD
end
%% Find minterm boundary.
bound = cell(N, 1);
for n = 1:N
if isempty(in_D0{n}) % incase empty set
bound{n}.vertices = [];
continue
end
boundary_points = [];
for j = 1:length(in_D0{n})
boundary_points = [boundary_points,
D1_tilde{in_D0{n}(j)}.vertices];
end
boundary_points = simplify_vertex(boundary_points);
% ----------------------- caculate the out bound of the
subdomains set
boundary_points = boundary_points';
x = boundary_points(:,1);
y = boundary_points(:,2);
dt = delaunayTriangulation(x,y);
k = convexHull(dt);
% -----------------------
bound{n}.vertices = boundary_points(k(2:end), :)';
% Convert vertexes into inequalities
[CC, dd] = polygon2inequalities(bound{n}.vertices);
% if there are points in the same line
% then the inequality functions will has
% duplicate rows
uniq = unique([CC dd], 'rows'); % cancel duplicate rows
bound{n}.A = uniq(:, [1,2]);
86
bound{n}.b = uniq(:, 3);
bound{n}.vertices ...
= inequality_function_solver_R2_bounded(bound{n}.A,
bound{n}.b);
end
%% Calculate complementary sets comp_set{n}, n is the
number of subdomains of D_telda
n = 1;
for j = 1:N
if isempty(in_D0{j})
continue
end
Q_set.A = bound{j}.A;
Q_set.b = bound{j}.b;
Q_set.vertices = bound{j}.vertices;
for i = 1:length(in_D0{j})
A_set = D1_tilde{in_D0{j}(i)};
comp_set{n} = find_complementary(A_set, Q_set);
% calculate the complementary set of each subdomain
n = n + 1;
% ordered by original domains
end
end
%% Calculate minterms.
num = 1;
for j = 1:length(D0)
if isempty(in_D0{j})
continue
end
% generate the minterm functions:
% for example, In_D{j} has 2 subdomains, the minterms
function is
% {0 0, 0 1, 1 0, 1 1} where 0 indicates original set,1
% indicates the complementary set
aa = [];
while size(aa,1) ~= 2^length(in_D0{j})
bb = randi([0 1], [1 length(in_D0{j})]);
% 0 is original set, 1 is the comp set
aa = [aa; bb];
aa = unique(aa, 'rows');
end
87
for k = 1:size(aa, 1)
flag = 0;
func{1} = [];
for i = 1:length( in_D0{j} )
if aa(k,i) == 0 % if 0, is original set
N = length(func);
for n = 1: N
func{n} = [func{n};
D1_tilde{in_D0{j}(i)}.A, D1_tilde{in_D0{j}(i)}.b];
end
end
if aa(k,i) == 1 % if 1 is complementary set
% if set {j}(i) does not have any
complementary set,the minterm funct do not have answer
if isempty(comp_set{in_D0{j}(i)})
flag = 1;
break
end
M = length(comp_set{in_D0{j}(i)});
% test num of comp set, subdomain In_D{j}(i) has
if M > 1 % if more than one comp set
N = length(func);
% caculate num of inequality funcs sets that exist
for n = 1:(M - 1)
% generate M-1 copies of the existing ineq funcs
% set and add M-1 complementary sets to the copies
for oo = 1:N
func{ n*N+oo } =[ func{ oo };
comp_set{ in_D0{j}(i) }{n+1}.A,
comp_set{ in_D0{j}(i) }{n+1}.b ];
end
end
% add complementary sets to the original set
for oo = 1:N
func{ oo } =[ func{ oo };
comp_set{ in_D0{j}(i) }{1}.A,
comp_set{ in_D0{j}(i) }{1}.b ];
end
88
end
if M == 1
N = length(func);
% add complementary sets to the set
for n = 1: N
func{n} = [func{n};
comp_set{ in_D0{j}(i) }{1}.A,
comp_set{ in_D0{j}(i) }{1}.b ];
end
end
end
end
if flag
continue
end
N = length(func);
for i = 1:N % solve all the minterm funcs
if ~isempty(func{i})
C = func{i}(:, [1 2]);
d = func{i}(:, 3);
vertices =
inequality_function_solver_R2_bounded(C,d);
if ~isempty(vertices) && size(vertices,2) >
2
D1{num}.vertices = vertices;
D1{num}.A = C;
D1{num}.b = d;
D1{num}.sq = num;
num = num + 1;
end
end
end
end
end
end
89
find_complementary
%==========================================================
% find complementary set of the input
% idea form Prof. Mayer
% input: SET A & boundry Q
% output: complementary sets & if the comp set is empty
returns empty []
% A_set.A A_set.b
%==========================================================
function A_comps = find_complementary(A_set, Q_set)
A_comps = [];
N = length(A_set.A); % caculate the number of A_set's edge
n = 1;
for i = 1:N
A_C = reduce_Q(A_set.A(i,:), A_set.b(i), Q_set);
if ~isempty(A_C)
flag = 0;
if size(A_C.vertices,2) > 2 % cancel duplicate
points
[A, b] = polygon2inequalities(A_C.vertices);
[A, b] = simplify_func(A, b);
A_C.vertices =
inequality_function_solver_R2_bounded(A,b);
flag = 1;
end
if size(A_C.vertices, 2) > 2 && flag %% incase
points in same line, points is 2, or empty
A_comps{n}.vertices = A_C.vertices;
A_comps{n}.A = A;
A_comps{n}.b = b;
n = n + 1;
end
end
Q_set.A = [Q_set.A; A_set.A(i,:)]; % cut of the saved
comp set from the bound
Q_set.b = [Q_set.b; A_set.b(i,:)];
Q_set.vertices =
90
inequality_function_solver_R2_bounded(Q_set.A,
Q_set.b); % vertexes of the remain set
end
end
%% function that get complementary sets of subdomains
function A_C = reduce_Q(A_edge_C, A_edge_d, Q_set)
A_C = [];
boundary_points = [];
%% Calculate intersections of Q_set boundary with
A_set_edge
for i = 1:length(Q_set.A)
A = [Q_set.A(i,:); -1*A_edge_C];
if rank(A) < 2
continue
end
b = [Q_set.b(i); -1*A_edge_d];
point = A\b;
if restrict(point, Q_set)
boundary_points = [boundary_points point];
end
end
%% Cancel boundary points that do not satify -1*A_edge.
A_edge.A = -1*A_edge_C;
A_edge.b = -1*A_edge_d;
for i = 1:length(Q_set.vertices)
if restrict(Q_set.vertices(:,i), A_edge) ~= 1
continue
end
boundary_points = [boundary_points
Q_set.vertices(:,i)];
end
boundary_points = simplify_vertex(boundary_points);
if ~isempty(boundary_points) && size(boundary_points,2) > 2
A_C.vertices = boundary_points;
91
[A_C.A, A_C.b] = polygon2inequalities(boundary_points);
else
A_C = [];
A_C.vertices = [];
A_C.A = [];
A_C.b = [];
end
end
%%
function n = restrict(point,Q_set) % detect if the
intersextion point is out of the boundary
n = max( Q_set.A*point - Q_set.b ) < 1e-9;
end
%% Cancel duplicate inequality functions.
function [A,b] = simplify_func(C,d)
Rank_AA = [C d];
Rank_A = [];
for oo = 1: length(Rank_AA) % incase func has nan
if isnan(Rank_AA(oo,1))
continue;
end
Rank_A = [Rank_A; Rank_AA(oo,:)];
end
C = Rank_A(:, [1 2]);
d = Rank_A(:, 3);
% ---------------------------------------------------------
-
func = [C d];
N = size(func,1);
output_func = func(1,:);
n = 2;
for i = 1: N
flag = 1;
for j = 1: size(output_func,1)
92
AA = func(i,:) - output_func(j,:);
if abs( AA(1) ) < 1e-9 && abs( AA(2) ) < 1e-9 &&
abs( AA(3) ) < 1e-9 % detact if the func is already exists
flag = 0;
break
end
end
if flag % save the unique functions
output_func = [output_func; func(i,:)];
n = n + 1;
end
end
A = output_func(:, [ 1 2]);
b = output_func(:, 3);
end
M_generator
function M1 = M_generator(minterms, D1, D1_tilde, M0, V0)
M1 = cell(1, length(minterms));
for i = 1:length(minterms)
D1_i.vertices = minterms{i}.vertices;
mi = mi_extractor(D1_i, D1_tilde); % determine the
subdomains of D_1 belongs to which domain in D_0
MM = [];
for oo = 1:size(mi,1) % generate Mi of subdomain i
sq = mi(oo,:); % copy switch sequence of V_1
if length(M0{1}.swq(1,:)) > 1
for j = 1:length(M0)
% find aq(1)'s real switching squences from M_0{}
if M0{j}.num == sq(1)
93
sq1 = M0{j}.swq;
break
end
end
for j = 1:length(M0) % find aq(2)'s real
switching squences from M_0{}
if M0{j}.num == sq(2)
sq2 = M0{j}.swq;
break
end
end
% ------------------
for sq1_i = 1:size(sq1,1)
for sq2_i = 1: size(sq2,1)
aa = sq1(sq1_i,:);
bb = sq2(sq2_i,:);
if isequal(aa(2:end), bb(1:(end - 1)))
MM = [MM; aa, bb(end)];
% combine rows of sq1 and sq2 if sq1(i,:)(2: end) equals
sq2(j,:)(1:length(bb)-1)
end
end
end
% -------------------
end
if length(M0{1}.swq(1,:)) == 1 % incase the
original Domain, just combine real switching sequence
MM = [MM; M0{sq(1)-V0(1)+1}.swq, M0{sq(2)-
V0(1)+1}.swq(end)];
end
end
M1{i}.swq = MM; % copy real switching sequence
into M_1{i}
M1{i}.num = D1{i}.sq; % copy domian number into
M_1{i} for further search
end
end
%% Extract mi sequence (see algorithm from [1 p. 22]).
94
function mi = mi_extractor(D1_i, D1_tilde)
mi = [];
D1_i_vertices = D1_i.vertices;
tile_columns = ones(1, size(D1_i_vertices, 2));
N = length(D1_tilde);
for i = 1:N
if ~isempty(D1_tilde{i}.A) && ~isempty(D1_tilde{i}.b)
y = D1_tilde{i}.A*D1_i_vertices - D1_tilde{i}.b(:,
tile_columns);
if all(max(y) < 1e-3)
mi = [mi; D1_tilde{i}.sq];
end
end
end
end
plot_figure
%==========================================================
% function generate domain pic
% input: domian struct and switching sequence
% output: nonempty domain num
%==========================================================
function num = plot_figure(C_p1, fig_num, M_1)
PP = pretty_plotting(18);
Q = [1.8 -1.8 -1.8 1.8 % set the restrict area Q
2 2 -2 -2];
C_p = C_p1;
figure(fig_num)
set(gca, PP.AxisStyle{:})
% PP = pretty_plotting(12);
num = 0;
95
for i = 1: length(C_p)
vertices = C_p{i}.vertices;
if isempty(M_1)
sq_num = C_p{i}.sq;
else
sq_num = M_1{i}.swq;
end
if ~isempty(vertices) && size(vertices,2) > 2
patch_x = vertices(1, :);
patch_y = vertices(2, :);
% patch_color = rand(1,3);
patch(patch_x, patch_y, [1 1 1], 'FaceAlpha', 0.05)
%-------------
centroid = transpose( mean(transpose(vertices)));
word_num = ['D'];
for w = 1: length(sq_num)
word_num = [ word_num num2str( sq_num(w) )];
end
text( double( centroid(1,1) ),
double( centroid(2,1) ), word_num,PP.TextStyle{:} );
hold on;
num = num +1;
end
end
%% additional labels
hold on
Q_zone = [ Q(:,end) Q];
plot(Q_zone(1,:),Q_zone(2,:), '--b' );
hold on
alpha = 0.0291;
96
beta = 0.0356;
vC = [-4, 4];
iL1= (-0.4+alpha*vC)/(-beta);
vC2 = [-4, 3.4759];
iL2= (-0.1+alpha*vC2)/(-beta);
vC1 = [-4, -3.3969];
iL3= (0.1+alpha*vC1)/(-beta);
plot(vC,iL1,'k',vC2,iL2,'k',vC1,iL3,'k')
hold on
red_line = [-4 4
-0.0323 -0.0323];
plot(red_line(1,:),red_line(2,:),'r');
% label
PP = pretty_plotting(18);
text(0, -1.25, 'D5',PP.TextStyle{:});
text( -2, 2, 'D3' ,PP.TextStyle{:});
text( 2, 2, 'D2',PP.TextStyle{:} );
text( 10, 10, 'D1',PP.TextStyle{:} );
ylabel('\iti_L - i_L^*\rm', PP.YLabelStyle{:});
xlabel('\itv_C - v_C^*\rm', PP.XLabelStyle{:});
Title = ['D' num2str(fig_num)];
title(Title,PP.TextStyle{:});
axis equal;
grid on
axis(1*[-2.5 2.5 -2.5 2.5])
end
97
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