ALU Report

PROJECT REPORT ON

4-BIT ARITHMETIC AND LOGIC UNIT (ALU) USING ADDERS

SUBMITTED BY

MOHAMMED AZHER KHAN ( 04-08-4018 )

MOHAMMED AZHARUDDIN ( 04-08-4024 )

ON COMPLETION OF TWO WEEK WORKSHOP ON

DIGITAL AND ANALOG VLSI DESIGN

CO-ORDINATOR

Mr. ARIFUDDIN SOHEL

Assoc. Prof., ECED

MJCET

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

MUFFAKHAM JAH COLLEGE OF ENGINEERING AND TECHNOLOGY

ABSTRACT

The aim of this project was to create a four-bit arithmetic logic unit. This

ALU was to take two four bit numbers and perform the following

operations on them - add, subtract,detect equality,or and exclusive-or

function. The ALU has 4 full adders and eight 2:1 multiplexers.

INTRODUCTION

This project was done in a structural manner. The implementation of the 4-bit ALU circuit

was done on Tanner Tools version 12.6 . We have laid out this report so that the information

portrayed will be easy to verify and comprehend. We have attempted to show all the

operations of ALU by giving all the possible inputs to the circuit .And the waveforms of both

inputs and corresponding outputs are recorded .

This should allow the viewer to simply hold a sheet of paper over the waveform output and

see the explanation of the inputs and results.

DESCRIPTION

IMPLEMENTING 4-BIT ALU USING ADDERS

An arithmetic and logical operaions unit(ALU) must,obviously be able to add two binary

numbers (A+B), and must also be able to subtract (A-B).

From the point of view of the logical operations it is essential to be able to And two binary

words (A.B). It is also desirable to Or (A+B) and perhaps also detect Equality, and of course

we also need an Exclusive-Or function.

Substraction by adder is an easy operation provided that the binary numbers A and B are

presented in twos complement form. In this case, to find the difference A-B it is only

necessary to complement B (exchange for 0 and vice versafor all the bits of B), add 1 to the

number thus obtained , then add tis quantity to A using the standard assition process

discussed earlier.The output of the adder will then be required difference in twos

complement form.Note that the complement facility necessary for substraction also serve to

form the logical complement (which is indeed exchanging 0 and 1 and vice-versa).

It is highly desirable to keep the architecture of ALU as simple as possible, and it

would be nice if the adder could be made to perform logical operations as readily as it

performs substraction.

In order to examine this possibility, consider the standard adder equation set.

Sum S=H’kCk-1 + HkC’k-1

New carry Ck=AkBk + HkCk-1

Where Half sum H=A'kBk + AkB’k

Consider, first the sum output if Ck-1 is held at logical 0, then

Sk= Hk.1 + H’k. =Hk

that is Sk=Hk=AkBk + AkBk ---------An Exclusive-Or operation

Now , hold Ck-1 a logical 1, then

S’k =Hk.0 + H’k.1 = H’k

that is Sk =H’k=A’kB’k + AkBk ---------An Exclusive-Nor (Equality)

operation

Next,consider the carry output of each element, first if Ck-1 is held at logical 0.

Then Ck=AkBk + Hk.0----------An And operation

Now if Ck-1 is held at logical 1, then

Ck = AkBk + Hk.1 = AkBk + A’k Bk +Ak.B’k

Therefore Ck= Ak + Bk --------------An Or operation

Thus it may be seen that the suitable switching of the carry line between adder elements will

give the ALU logical functions.A possible arrangement of the adder elements for both the

arithmetic and logic fuctions is suggested in the diagram as shown.

BLOCK DIAGRAM

T-SPICE PROGRAM

* SPICE export by: SEDIT 12.60

* Export time: Fri Jul 16 15:27:57 2010

* Design: azhar

* Cell: alu_4bit

* View: view0

* Export as: top-level cell

* Export mode: hierarchical

* Exclude .model: no

* Exclude .end: no

* Expand paths: yes

* Wrap lines: no

* Root path: D:\azhar

* Exclude global pins: no

* Control property name: SPICE

********* Simulation Settings - General section *********

.probe

.option probev

.option probei

.option probeq

.lib "C:\Documents and Settings\admin.MJCET-50B89CA38\My

Documents\Tanner EDA\Tanner Tools

v12.6\Libraries\Models\Generic_025.lib" tt

*************** Subcircuits *****************

.subckt inverter Vin_inv Vout_inv Gnd Vdd

*-------- Devices: SPICE.ORDER > 0 --------

MNMOS_1 Vout_inv Vin_inv Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u

AD=2.25p PD=6.8u

MPMOS_1 Vout_inv Vin_inv Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u

AD=2.25p PD=6.8u

.ends

.subckt Mux2 A B Out Sel Gnd Vdd

*-------- Devices: SPICE.ORDER < 0 --------

* Design: LogicGates / Cell: Mux2 / View: Main / Page:

* Designed by: Tanner EDA Library Development Team

* Organization: Tanner EDA - Tanner Research, Inc.

* Info: 2 Input Multiplexer

* Date: 5/22/2007 1:13:54 AM

* Revision: 107


MN5 6 G Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

MN6 Out 3 Gnd 0 NMOS W=2.5u L=250n M=2 AS=4.5p PS=13.6u AD=3.125p

PD=7.5u

MN1 G Sel Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

MN2 3 A 4 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

MN3 4 Sel Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

MN4 3 B 6 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

MP1 G Sel Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u

MP2 2 G Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

MP3 3 A 2 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

MP4 5 Sel Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u

MP5 3 B 5 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

MP6 Out 3 Vdd Vdd PMOS W=2.5u L=250n M=2 AS=4.5p PS=13.6u AD=3.125p

PD=7.5u

.ends

.subckt nand A B Vout Gnd Vdd


MNMOS_1 Vout A N_1 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u

MNMOS_2 N_1 B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u

MPMOS_1 Vout A Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u

MPMOS_2 Vout B Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u

.ends

.subckt nor A_nor B_nor Vout_nor Gnd Vdd


MNMOS_1 Vout_nor A_nor Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u

AD=2.25p PD=6.8u

MNMOS_2 Vout_nor B_nor Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u

AD=2.25p PD=6.8u

MPMOS_1 N_2 A_nor Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u

AD=2.25p PD=6.8u

MPMOS_2 Vout_nor B_nor N_2 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u

AD=2.25p PD=6.8u

.ends

.subckt halfadder A_halfadder B_halfadder Carry_halfadder

Sum_halfadder Gnd Vdd

Xnand_3 B_halfadder N_1 N_3 Gnd Vdd nand

Xnand_4 N_3 N_2 Sum_halfadder Gnd Vdd nand

Xnand_1 N_1 A_halfadder N_2 Gnd Vdd nand

Xinverter_1 N_1 Carry_halfadder Gnd Vdd inverter

Xnand_2 B_halfadder A_halfadder N_1 Gnd Vdd nand

.ends

.subckt or A_or B_or Vout_or Gnd Vdd

Xinverter_1 N_1 Vout_or Gnd Vdd inverter

Xnor_1 B_or A_or N_1 Gnd Vdd nor

.ends

.subckt fulladder A_fulladder B_fulladder C_fulladder

Carry_fulladder Sum_fulladder Gnd Vdd

Xhalfadder_1 B_fulladder A_fulladder N_2 N_1 Gnd Vdd halfadder

Xhalfadder_3 C_fulladder N_1 N_3 Sum_fulladder Gnd Vdd halfadder

Xor_1 N_3 N_2 Carry_fulladder Gnd Vdd or

.ends

********* Simulation Settings - Parameters and SPICE Options

*********

*-------- Devices: SPICE.ORDER == 0 --------

Xfulladder_2 Vdd N_4 C0 C1 S1 Gnd Vdd fulladder

Xfulladder_3 Vdd N_6 C1 C2 S2 Gnd Vdd fulladder

Xfulladder_4 Gnd N_8 C2 C3 S3 Gnd Vdd fulladder

XMux2_1 N_1 B0 N_2 Sel_1 Gnd Vdd Mux2

XMux2_2 N_3 Vdd N_4 Sel_1 Gnd Vdd Mux2

XMux2_3 N_5 B2 N_6 Sel_1 Gnd Vdd Mux2

XMux2_4 N_7 Gnd N_8 Sel_1 Gnd Vdd Mux2

XMux2_5 Gnd Vdd N_9 Sel_2 Gnd Vdd Mux2

Xinverter_1 B0 N_1 Gnd Vdd inverter

Xinverter_2 Vdd N_3 Gnd Vdd inverter

Xinverter_3 B2 N_5 Gnd Vdd inverter

Xinverter_4 Gnd N_7 Gnd Vdd inverter

Xfulladder_1 Vdd N_2 N_9 C0 S0 Gnd Vdd fulladder


VVoltageSource_1 Vdd Gnd DC 5

VVoltageSource_2 B0 Gnd PULSE(0 5 0 5n 5n 95n 200n)

VVoltageSource_3 Sel_1 Gnd PULSE(0 5 0 20n 20n 380n 1.6u)

VVoltageSource_4 B2 Gnd PULSE(0 5 0 10n 10n 190n 400n)

VVoltageSource_5 Sel_2 Gnd PULSE(0 5 0 15n 15n 285n 800n)

.PRINT TRAN V(C1)

.PRINT TRAN V(C3)

.PRINT TRAN V(C2)

.PRINT TRAN V(B0)

.PRINT TRAN V(B2)

.PRINT TRAN V(Sel_1)

.PRINT TRAN V(Sel_2)

.PRINT TRAN V(S0)

.PRINT TRAN V(S1)

.PRINT TRAN V(S2)

.PRINT TRAN V(S3)

.PRINT TRAN V(C0)

********* Simulation Settings - Analysis section *********

.op

.tran/Powerup 10ns 1000ns start=0ns

.option prtdel=10ns

********* Simulation Settings - Additional SPICE commands *********

.end

FINDINGS

While creating this ALU we spent most of my time on the switch unit. We tried to implement

the switch unit but we faced problems,and then we replaced switch unit with 2:1 mux.

All of the other units were straightforward and no hurdles were faced in the rest of the

project.

CONCLUSIONS

All the possible inputs and corresponding outputs cases have been testes and no errors

were obtained in them.

We now feel that we have a very good understanding implementation of usage of Tanner

Tools and also how a 4-bit ALU functions