Lab Report-32bit ALU and ROM(final).doc

8/10/2019 Lab Report-32bit ALU and ROM(final).doc

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HOON MIEW JIE BK10110096

DISHEN A/L KESEVA KUMAR BK10110062

MOHD AIZZAT BIN MASTAN BK10160339

SHERIELYN SAFIRA RANTI BK10110269


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TITLE: 32-BIT ALU !" ROM

1# INTRODU$TION

A computer is one of the most important discoveries of the human race. The CPU (Central

processing unit is the main brain of this great invention which could be one of the most used

appliances in the world today. Almost every household has a computer and it is a multi-million

dollar industry which is still vastly growing and expanding. The CPU is used to process

information needed by the computer it acts li!e a brain when we thin! to move our body

parts and etc. "hen loo!ing into a CPU the few basic things that we should !now is that the

CPU has four basic tas!s that it performs. The tas!s are fetch decode manipulate and output.

The speed rating for the CPU is measured by #$% but in fact it is not all that accurate. This

CPU chip is comprised of a million logic gates that are embedded which are used to complete

a variety of di&erent operations. These gates are used with a cloc! that regulates at a speed

which the CPU is fed data. The CPU is comprised of 've basic components )A# )egistersbuses A*U and control unit. )A# is a component which is created from combining latches with

a decoder. The latches create circuitry that can remember while the decoder creates a way for

individual memory location to be selected. )egisters are components that are special memory

locations that can be accessed very swiftly. The three registers are instruction register the

program counter and the accumulator. +uses are the information path or highway for the CPU.

+uses are many tiny wires that carry data between components. The most important buses

are the address buses the data buses and the control buses. The A*U or arithmetic control

unit performs all the mathematical calculations of the CPU. ,t is composed of complex circuitrywhich ma!es this component very important. The A*U can add subtract multiply divide and

perform a lot of other calculations on binary numbers as well.

2# LITERATURE REVIEW

2#1 A 16-B%&' R%'( )*+(,''+* A*(%&,(&.*,: $+!&*+,* S&&, M(%!,' A!"

F.!(&%+! V,*%(&%+! U'%! V,*%+ H"

,smail aad et al /0 presents the design and simulation of /1-bit ),C processor architecture

behavioral model based on $2* methodology using 3erilog-$2* software. The processor

system consists of )4# )A# ,54 and CPU. The CPU module is merely a shell which instances

the real processor de'nition in cpu6core.v control.v datapath.v and alsu.v 'le. +ehavioral

model of control module which comprises of controller state machine ,nstruction )egister (,)7

and a group of Control ignals are explained thoroughly. The tas!s of modeling )ead "rite

and Tristate bu&er operation for datapath module are also deeply being explained. The

functionality of the processor design was tested by executing three instructions type. Thus it

is shown that 3erilog-$2* can be used to improve the design process of new microprocessor

architecture.


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F%.*,2#1 4 )*+(,''+* $+!&*+ U!%& A*(%&,(&.*, !" 54 )*+(,''+*D&& U!%& A*(%&,(&.*, 718

2#2 32-B%& ALU D,'%!

,n his boo! Paul 3. +oloto& presents the general A*U function. #icroprocessors tend to

have a single module that performs arithmetic operations on integer values. This is

because many of the di&erent arithmetic and logical operations can be performed

using similar (if not identical7 hardware. The component that performs the arithmetic

and logical operations is !nown as the Arithmetic *ogic Unit or A*U. 80

The A*U is one of the most important components in a microprocessor and is

typically the part of the processor that is designed 'rst. 4nce the A*U is designed the

rest of the microprocessor is implemented to feed operands and control codes to the

A*U.

*ogic and addition are some of the easiest but also the most common

operations. 9or this reason typical A*Us are designed to handle these operations

specially and other operations such as multiplication and division are handled in a

separate module.

:otice also that the A*U units that discussed here are only for integer

datatypes not ;oating-point data. *uc!ily once integer A*U and multiplier units have

been designed those units can be used to create ;oating-point units (9PU7. The

following is an example of a basic 8-bit A*U. The boxes on the right hand side of the

image are multiplexers and are used to select between various operations< 4) A:2

=4) and addition.


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F%.*, 2#2 A 5'%( 2-5%& ALU 728

Unfortunately implementing a true >8-bit A*U will ?uic!ly turn the pro@ect out of scale

if similar approach is ta!en. Therefore a simpli'cation made in the A*U module in

3erilog is ta!en advantage of.

3# METHODOLOY

A >8-bit A*U is modi'ed based on the wor! by ,smail aad et al /0. 9or a >8-bit

micorprocessor design some of ma@or modi'cation is made where modi'cation for each

module and the @usti'cation is explained in details below.

3#1 O(+",' +".,

An opcodes is the operation codesB which contains a list of de'ned function that are used for

the microprocessor. The coding itself does not have any speci'c tas!. ,t is @ust used to de'ne

all the listed function which easier for anyone to understand the program such as we can @ust

call the opcode without remember the value inside it which might consist of a very long binary

number.

55#acro 4pcodes


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de'neA22r ;DEbFFFF8-bit A*U ma!es it possible to implement ;oating-point (which has a >8-bit format7

possible of complex calculation within a very short cycle-time< a H-bit processor using ;oating-

point format will need at least D-cycle for data transfer compared to a >8-bit processor which

only re?uires at least / cycle.

The A*U function is expanded to D bits e?uivalent to /1 instructions in total. "ith this extra

A*U function is implemented.

+y increasing the number of bits ,) instruction set can be increased where more A*U

function is implemented and the addressable register is increased to 8II register (8H7.

$owever in this pro@ect the register is only increased to H register (in which )4 to )H

registers are created7 to !eep the pro@ect manageable and as a proof of concept.

>?'@input/ +*input8 +*9unction4 (',9unction4 A22:result6temp input/ input8C U+:result6temp input/ -input8C A:2:result6temp input/ input8C

4):result6temp input/ input8C =4):result6temp input/ input8C :4T:result6temp Ginput/C )A:result6temp input/ /C *A:result6temp input/ /C 55new function #42:result6temp input/ input8C 55new function JK*:result6temp input/input84/:FC 55new function L)JATJ):result6temp input/ input84/:FC 55new function #A**J):result6temp input/ input84/:FC 55new function

#U*T:result6temp input/ input8C 55new function 2,3:result6temp input/ /input8C 55new function

",.&:result6temp input/C ,!"(',F%.*, 3#2 32-B%& A. M+".,

2e'ned in the opcodes.v the A*U perform the arithmetic and logical operation in the

microprocessor. ,n this microprocessor the A*U function. The A*U will operate the arithmetic

function according to the de'ned function in the opcodes. The A*UMs /1 functions are

addition subtraction and or xor xnor not modulus logical left and right shift arithmetic

left and right shift multiplication division and choose the /stinput and 8nd input. The input

and output are >8bit. The new function is labelled in green comment.

An additional ;ag status is also designed in A*U module. The over;ow ;ag is designed.

The calculation is made in a bu&er register of 81Dbit. "hen the result is larger than 8>8 the

over;ow logic is triggered. :ote that for troubleshooting purpose the members set the result

to return the remainder value if the resultant calculation is less than 8>8. ,n this case the


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function of carry-over bit is simulated. ,f the resultant calculation is bigger than 8>> the result

will returns 8>8value. ,n practice this implementation of A*U design is wrong. A*U module are

designed in bit-by-bit which has inbuilt carry-over bit li!e ripple carry-in bit. 4ver;ow bit is

actually the of the #+ carry-over bit. This is designed as a proof-of concept.

always@(result_temp) begin if((result_temp >32'hFFFFFFFF)||(result_temp ==32'hFFFFFFFF))//2^32 begin Overflow =1; result =result_temp-64'hF00000000; if(result_temp >32'hFFFFFFFF)result =32'hFFFFFFFF;

endelse

begin Overflow =0; result=result_temp; end end

The over;ow logic from noti'es the control module and set the over;ow ;ag if the setbit is

selected.

F%.*, 3#2 32-B%& A. M+".,

3#3 32-B%& $+!&*+ M+"., !" *,%'&,* R< R< R6< RP

The control module executes operations in proper se?uence by means of controller state

machine as shown in 9igure >. The control module generates the control signals shown in

9igure 8 that causes each instruction to be executed. The instruction register is a /1-bit

register with ,)/I


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F%.*, 3#3 : $+!&*+,* S&&, M(%!, S&&, D%*

The following code is used to set the >8-bit ,) in control module.

''%!4pcode ,)7>/:8D8C''%!#ode+it ,)7>/:>F8C''%!)d ,)78>:/18C''%!)s/ ,)7/I:H8C''%!)s8 ,)7O:F8C''%!A*Ufunc ,)78O


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F%.*, 3#P 32-B%& I!'&*.(&%+! R,%'&,* .'," %! &, $)U

3# 32-B%& D&& M+"., !" *,%'&,* R< R< R6< RP

,t consists of functional units such as the A*U and performs the data processing

operation. 2atapath will store the data in the register of the main memory. 2atapath module

is used to suit the de'nition of design processor to model read and write operation using )s/

and )s8 from the registers available in the microprocessor. ,n datapath there is the tri state

bu&er. The Tris state bu&er (TrisA*U TrisPC Tris)s8 Tris)d nTris)d7 is used to control the ;ow

of data in the module. ,n our datapath module there are H register being used which are PC

)/ )8 )> )D )I )1 and )O. The extra register is made by assigning new variable in the ,)

instruction set. Then the selected register is assigned its control variable in control unit. A

further assignment is made in datapath module. The coding below shows the assignment of

the new register.

AssignRs1 =(ReadR4_1)?R4 :32.*+;

F%.*, 3# ''%!,!& + &, !,> *,%'&,*

3# 32-5%& ROM M+"., !" 109""*,''5, M,+*? A""*,''

)ead only memory ()4#7 functions as a permanent storage (non-volatile7 for

microprogramming library subroutines system program (+,47 function stables and

embedded system code.

The output of the )4# module is a/1-bit data bus data6bus and the input an H-bit addressbus Address6bus determines which data stored in the )4# will be selected and to be

outputted

As stated before the )4# address is also increased up to a limit of 8>8which is Dx/FN. Again

in order to !eep pro@ect manageable the maximum )4# address is set to /F8D only.

*,7>/:F82ata6stored 7/F8D:F8C

F%.*, 3#9 D& S&+*,"

Tris#em is to control the data transfer from )4# to the sysbus.

''%!ysbus Tris#em42ata6in:>8Eb%C

F%.*, 3#10 T*%'M,


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F%.*, 3#11 T, ROM 5+( "%* !" ROM %,,!&&%+!

A better memory management unit could be implemented instead of directly feeding the data

from the )4# module to the CPU module. $owever it is not implemented as the members

have trouble with the T), timing on reading the )4# data. The approach the group choose is

to manually select the data address from the )4# module and transfer it to the CPU module

via testbench.

Test+ench DHF Address6busFC DHF Address6bus/C

)4# #odule

2ata6stored7F8;*2


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ata_stored[3=32'h0000FFFF;

F%.*, #1 L+" !" S&+*, O,*&%+!

The waveform of the timing result is displayed. The timing where the register changes the

result is highlighted.

F%.*,#2 L+"%! "& 00FFFFFF,4 !" 0000FFFF,4 %!&+ *,%'&,*1

!" *,%'&,*2 *,',(&%Q,?#

)egister-)egister 4peration - #ultiplication and 2ivision

At address /8 #U*T,P*,CAT,4: instruction of register/ register8 is performed. The result is

then written to registerO. ubse?uently address /> performs 2,3,,4: and written into

register>. The division of FF999999hex(/1OOO8/Idec7 by FFFF9999hex(1II>Idec7 is

FFFFF/FFhex(8I1dec7. The A*U is shown performing and a >8-bit A*U can address a

maximum of 8>8

digits.

ata_stored[12=!4'*0010"$("$R5"$R1"$R2#; ata_stored[13=!4'*0010"$7"$R3"$R1"$R2#;


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F%.*, #3 L+"%! "& 00FFFFFF,4 !" 0000FFFF,4 %!&+ *,%'&,*1 !"

*,%'&,*2 *,',(&%Q,?#

9or #U*T,P*,CAT,4: operation since the result is larger than 8>8 it triggers the over;ow ;ag.

"hen the over;ow ;ag is triggered and the result is larger than 8>> the result will

automatically be registered 8>8

as an indicator for user. ,n real operation over;ow ;ag shouldtriggers immediate program termination via interrupt function. )egisterO is used in this case

to test the implementation.

)egister-)egister 4peration Q J?ual Lreater maller

At address /D an JKUA* comparison is made between the data in register/ and register8.

The data are not e?ual therefore the result given is %ero and written into register>. Address

/I and /1 performs L)JATJ) and #A**J) operation respectively. The results given were /

and F respectively input/ being greater than input8. All the result is written in register>. The

following code is used to perform the operation.

ata_stored[14=!4.*0010"$!8"$R3"$R1"$R2#;ata_stored[19=!4.*0010"$:R!!R"$R3"$R1"$R2#;

ata_stored[16=!4.*0010"$


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larger than data in register8. Conse?uently the %ero ;ag is terminated. At address /I

#A**J) operation returns F (false7 value and the %ero ;ag is triggered again.

F%.*, #R,%'&,*-R,%'&,* O,*&%+!

ummary

*ogic comparators are essential in implementing algorithm where if-else for while logic is

based on. #ultiplication and division on the other hand is rather unrealistic as the operationis completed within a cycle. )eal multiplication and division operation are advanced

instruction based on conditional-shifting binary logic involving binary shift. Although this

implementation is wrong it serves as a proof of concept. 4ver;ow ;ag and %ero ;ag is proved

wor!ing in the example as well.

#2 )*+5,' E!(+.!&,*," D.*%! T, D,'%!

/7 inout wire assign declaration

,nitially the 3erilog declaration was confusing and intimidating. Therefore the declaration for

input and output between subse?uent modules need to be clari'ed and understood.

Jrror< 2eclaration for Eysbus6wireE incompatible with earlier vectored declaration at

C


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87 )egister-)egister Addition 4peration

$alf of the time is spent on troubleshooting the code while trying to understand why the

operation such as operation involving adding register/ and register8 and then put the result

into register8 did not wor! accordingly. 9or troubleshooting purpose waveform from wire )s/

)s8 and )d was extracted from the datapath module. +y carefully monitoring the waveform

and also constant reference to the coding the 3erilog coding was painsta!ingly analy%ed. ,t

was later found in that TrisA*U which needs to be enabled for the results to be written into a

register. The condition for activating TrisA*u is given below.

''%!TrisA*U sub6state address6setup4sub6state address6hold44state Jxecute4#ode+it 8Eb//#ode+it 8Eb/F44C

)8 S- )/ U+r )8

,n the following waveform an instruction was given to subtract register8 from register/ and

put the result in register>. The data I and / had been inserted into register/ and register8

respectively. A subtraction between the two register was then made. The result shows D

which is correct. $owever the data was not written into register>.

2ata6stored7I8 ;U+r memory cycles to complete.

)esult is correct but and is passed

to )d wire but is not written to

the register.


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ince in the coding / cycle is stated to be /F units > memory cycles is e?uivalent to >1 cloc!

cycle or >1F units.

>7 Understanding the Cloc!-Cycle

Therefore in this program the pulse is set a I unit where each / cloc! cycle (consist of

rising and falling edge7 is /F unit where / unit is /FFps. A state has D sub-state where each

sub-state has >-cloc! cycle giving a state of at least /8-cloc! cycle (/-memory cycle7 or

/8FFF ps or /8F unit. ome of the instructions ta!e 8 states to complete of which 8DF units

is necessary. This information is important for the system to wor!. Although this information is

given in the beginning of the lesson this understanding was made very late and a lot of time

is wasted on senseless trial-error troubleshooting. Unfortunately most of the members were

overwhelmed at the information presented at the beginning of the lesson and had a hard time

discerning essential information. The lac! of the membersM initiative and preparation hinders

the progress as well.

D7 :o Proper Coding 2ocumentation

Although the paper presents extensive information and bloc! diagram the lac! of coding

documentation ma!es it very hard to relate concept especially when the code are given in

parts. The full picture and the usage of each module were understood at a very late stage.

Jven then it is very dicult to understand why the author chooses the particular coding. 9or

example< in the opcodes module it is dicult to see what the assignment of the binary code

is use for. ,n the code below there is no explanation on what is A22r A22i A22rcc and so onand a proper documentation on how to use it. econdly there is no explanation as on how the

author set the macro opcodes in relation to the control module. Third a ma@ority of the

explanation given is based on the paper which helps little as most of members are struggling

on implementing their idea into 3erilog coding due to the lac! of understanding on the 3erilog

coding.

#3 D*>5(' O T, 32-B%& A. D,'%!

/7 Complex Architecture ,mplementation

Jlectronic implementation may be very dicult to achieve as sophisticated e?uipments is

necessary for such fabrication. $igh processing capability is also essential to utili%e the >8-bit

data processing. As the result the cost of fabrication is overwhelming and may be out of

reach for most people. A detailed structured design is also necessary to fully utili%e the >8-bit

processing capability. As such extensive research and time need to be invested of which is

out of the scope of this pro@ect.

87 Used for $igh-end Application

A >8-bit processor is usually used for processing-extensive devices. As such for this pro@ect

an implementation of a >8-bit processor o&ers no real bene't as there are most li!ely no

application that is within the scope of the this study which re?uires such processing capability.


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This implementation is however useful for students in understanding and learning how the

design of a processor can be made and simulated in 3erilog environment. ,t also helps the

student to associate in designing and implementation in real-world engineering.

REFEREN$ES

/0 ,smail aad P. 3. (8FFD7. $2*-+AJ2 2J,L: #JT$424*4LV 49 /1-bit ),C

#,C)4P)4CJ4). 3rd International Conference on Advanced Manufacturing

Technology (ICAMT 2004!Wuala *umpur #alaysia.

80 CPU designers have used a variety of names for the arithmetic logic unit including

RA*UR Rinteger execution unitR and RJ-boxR. Paul 3. +oloto&. R9unctional Principles of

Cache #emoryR8FFO.

>0 Andrei-orin Lheorghe C. +. (8F/F7. LJ:J)A* PU)P4J #,C)4P)4CJ4). A3ALJ/1Q /1-+,T ),C A)C$,TJCTU)J /.

D0 +haas!aran 3. . (8F//7. /1-+it ),C Processor 2esign for Convolution Application. /.

I0 X. $. (/NNH7. Computer architecture and organisation . #cgraw $ill.

10 Wui V, V.-$. 2. (8FFN7. >8-bit ),C based on #,P. instruction fetch module design /.

O0 *iu V. (8F/87. $,C< A computer architeccture using operand descriptor. /.

H0 )ahman A. +. (August 8FFD7. $2*-+AJ2 2J,L: #JT$424*4LV 49 /1-bit ),C

#,C)4P)4CJ4). A :J" /1-+,T ),C P)4CJ4) A)C$,TJCTU)J< C4:T)4**J)

TATJ #AC$,:J A:2 9U:CT,4:A* 3J),9,CAT,4: U,:L 3J),*4LY $2* /8.

N0 )a@ Wumar ingh Parihar . ). (8FF17. )JP4)T 4: 2J,L: 49 /1 Q +,T ),C

P)4CJ4).
http://alasir.com/articles/cache_principles/cache_hierarchy.htmlhttp://alasir.com/articles/cache_principles/cache_hierarchy.htmlhttp://alasir.com/articles/cache_principles/cache_hierarchy.htmlhttp://alasir.com/articles/cache_principles/cache_hierarchy.html


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/F0 )epa! #. (8F/87. A imple imulator for a +asic microprocessor.

//0 awit%!i . (8F/87. Processor design using a functional hardware description language.

/.

/80 =iao Tie@un *. 9. (8FFH7. /1-+it Teaching #icroprocessor 2esign and Application. /.

A))ENDI: $ODIN

opcodes.v

// fu"#to"s$def"e 4'd0$def"eOR 4'd3$def"e=O 4'd9$def"e


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$def"eR9 ?'*00001111$def"eR6 ?'*00011111$def"eR5 ?'*00111111

//(a#ro Op#odes$def"er !4'*0000"$# //add R1 wth R0$def"e !4'*0100"$#$def"er## !4'*0010"$#$def"e## !4'*0110"$#

$def"e%r- !4'*0001"$#$def"e%- !4'*0101"$#$def"eORr !4'*0000"$>OR#$def"e>OR !4'*0100"$>OR#$def"e>ORr## !4'*0010"$>OR#$def"e>OR## !4'*0110"$>OR#$def"e%>ORr- !4'*0001"$>OR#$def"e%>OR- !4'*0101"$>OR#$def"e=Or !4'*0000"$=O#$def"e=Or## !4'*0010"$=O#$def"e%=Or- !4'*0001"$=O#$def"e


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input[3:0Fu"#to";

wire-ero;regOverflow""derflow;reg[31:0result;reg[63:0result_temp;wire[31:0"put1""put2;

assign-ero =(result_temp ==0);

always@(result_temp) begin if((result_temp >32'hFFFFFFFF)||(result_temp ==32'hFFFFFFFF))//2^32 begin Overflow =1; result =result_temp-64'hF00000000; if(result_temp >32'hFFFFFFFF)result =32'hFFFFFFFF; end

else begin Overflow =0; result=result_temp;

end

end

always@("put1 or"put2 orFu"#to") ase(Fu"#to") $:result_temp ="put1 '"put2; $OR:result_temp ="put1 "put2; $=O:result_temp ="put1; $


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inout[31:0


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// :e"erate trstate #o"tol s,"als for


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//// %o"dto"al "stru#to"always@(posedge%lo#&) begin if((((state ==$!e#ute&&(ode)t ==2'*01)&&su*_state ==$data_hold)||(state==$Fet#h1&&(ode)t ==2'*00&&su*_state ==$data_setup))&&set*t ==1'*1) +ero_fla,_re,


22/28

else begin deassignstate; deassignsu*_state; deassignR; deassign+ero_fla,_re,; deassignoverflow_fla,_re,; deassignu"derflow_fla,_re,; end

end%odule

datapath.v

includeRopcodes.vRtimescale/FFps//Fps

+".,datapathysbus


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''%!)s8 )ead)8684)8 :>8Eb%C''%!)s8 )ead)>684)> :>8Eb%C''%!)s8 )ead)D684)D :>8Eb%C''%!)s8 )ead)I684)I :>8Eb%C''%!)s8 )ead)1684)1 :>8Eb%C''%!)s8 )ead)O684)O :>8Eb%C

alu A*U alu6Gero


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''%!PC6wirePCC ''%!)/6wire)/C ''%!)86wire)8C ''%!)>6wire)>C ''%!)D6wire)DC ''%!)I6wire)IC ''%!)16wire)1C ''%!)O6wire)OC

''%!2)6wire2)C ''%!)F6wire)FC ''%!)s/6wire)s/C ''%!)s86wire)s8C ''%!)d6wire)dC ''%!)esult6wireresultC,!"+".,

cpu6core.v

55cpu6core.v

timescale/FFps//Fps

+".,cpu6coreysbus


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55C42J8EhFFFF9999 2ata6stored7F8;*2


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rom RO((ata_out"ddress_*us""O!""%! );

assignata_" =ata_out;

assign"O! ="tal_value;

assign"%! ="tal_value;always@("Reset)

if("Reset) begin assign"tal_value =0; end else begin //deass," "tal_value; "tal_value=1; end

e"dmodule

test6benchO6cpu.v

//(odule =ameK #pu_tstEv//est )e"#h for #pu modelE

$tmes#ale100ps$10ps%oduletest_*e"#h5_#pu;

//data t@pe de#larato"sreg"Reset"%lo#&;

reg[31:0ddress_*us;

wire[31:0C%_wre"R1_wre"R2_wre"R3_wre;wire[31:0R4_wre"R9_wre"R6_wre"R5_wre"R0_wre"R_wre;

wire[31:0Rd_wre"Rs1_wre"Rs2_wre"Result_wre"


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,4?0 ddress_*us=A; ,4?0 ddress_*us=10; ,4?0 ddress_*us=11; ,4?0 ddress_*us=12; ,4?0 ddress_*us=13; ,4?0 ddress_*us=14; ,4?0 ddress_*us=19; ,4?0 ddress_*us=16; ,4?0 ddress_*us=15;

,4?0 ddress_*us=1?; ,4?0 ddress_*us=1A; ,4?0 ddress_*us=20; ,4?0 ddress_*us=32;

,4?0Lstop; //M4?0 Lf"sh;

endinitialbeginfore.er,9%lo#& =%lo#&;endend%odule

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Lab Report-32bit ALU and ROM(final).doc