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EE290C - Spring 2004Advanced Topics in Circuit DesignHigh-Speed Electrical Interfaces

Lecture 6EqualizersBorivoje NikolicFebruary 5, 2004.

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Agenda

Equalization BackgroundImplementation of Equalizers

Digital Receive EqualizersMixed-Signal Receive EqualizersTransmit Equalizers

Some practical implementationsSummary

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Link as a Communication System

Communication through a band-limited channel

Tx Rx

Channel

frequency

H(f)channel

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Inter-Symbol Interference

Effects of frequency-selective attenuation in the time domain

No ISIx[nT] · x[mT] = 0m ? n

No ISIx[nT] · x[mT] ? 0m ? n

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5

Channel

General channel should be ISI-free

TxRcvr

Front-End

Channel

Slicer/Detector

ISI-free channel

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Equalizer

Most channels are low-pass

EqChannel

f

H(f)Channel G(f)

EqualizerG(f)H(f)Channel + equalizer

f f

Band-limited channel (w/ISI) ? no ISI

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Equalizer: Amplitude + Phase

f

|H(f)|channel

|G(f)|Equalizer

f

Band-limited channel (w/ISI) ? no ISIf

∠ H(f)channel

∠ G(f)Equalizer

f

1

0.1

10

1

0

-90o

90o

0

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Implementing Equalizers

Digital receive equalizersAnalog receive equalizersTransmit equalizers

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Receive Equalizers

Digital equalizer

Mixed-signal equalizer

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Receive Equalizers

ADC resolution

f

|H(f)|channel

1

0.01

QN

Analog equalizers can reduce the resolution requirement for the ADC

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Implementing Equalizers

Digital receive equalizersAnalog receive equalizersTransmit equalizers

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Transversal Filter

FIR filter, direct form

[ ] [ ] ]1[...]2[]1[ 210 +−++−+−+= Nnxanxanxanxany N

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Critical Path

Digital FIR

T = Tmult + (N-1)Tadd

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Pipelining

Pipelining can be used in both digital and analog (mixed-signal) implementations to increase throughput

Pipelining: Adding same number of delay elements in each forward cutset (in the data-flow graph) from the input to the output

Cutset: set of edges in a graph that if removed, graph becomes disjointForward cutset: cutset from input to output over all edges

Increases latency

Register overhead (power, area)

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Pipelining

3-tap FIR

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Pipelined Direct FIR

Critical path

T = Tmult + Tadd

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Multi-Operand Addition

Adders form a tree

T = Tmult + (log2N)Tadd

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Multi-Operand Addition

Using 3:2 or 4:2 compression

Optional pipelining, 1-2 stages

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Transposing FIR

Transposition:Reversing the direction of all the edges in a signal-flow graph,Interchanging the input and output ports Functionality unchanged

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Transposed FIR

Represent as a signal-flow graph

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Transposed FIR

Critical path shortened

Input loading increased

T = Tmult + Tadd

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Parallel FIR

Feed-forward algorithms are easy to parallelizeProcessing element representation of a transversal filter

a1 x[n]

y[n]a0 a1 a2

x[n-1] x[n-2]

0

Transversal filterProcessing element

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Parallel FIR

Two parallel pathsTwo cycles to complete operationCan be extended to more

Processing elementTwo parallel path FIR

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Practical Digital EqualizersMita, ISSCC’96, two parallel paths150Mb/s 0.7µm BiCMOS

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Practical Digital Equalizers

Moloney, JSSC 7/98, 2 parallel paths, 3:2 Wallace150Mb/s 0.7µm BiCMOS

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Practical Digital Equalizers

Wong, Rudell, Uehara, Gray JSSC 3/95, 4 parallel paths50Mb/s, 1.2µm CMOS

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Practical Digital Equalizers

Thon, ISSCC’95Transposed filter, 240Mb/s 0.8µm 3.7V CMOS, 150mW

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Practical Digital Equalizers

Staszewski, JSSC 8/002 parallel transposed paths550Mb/s 0.21µm CMOS, 36mW

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Practical Digital Equalizers

Rylov, ISSCC’012.3Gb/s, 1.2W, 0.18µm domino CMOS

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Practical Digital Equalizers

Tierno, ISSCC’02

1.3Gb/s, 450mW, 0.18µm 2.1V domino CMOS

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Implementing Equalizers

Digital receive equalizersAnalog receive equalizersTransmit equalizers

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Analog Receive Equalizers

Delay-line-based FIRStraightforward, direct or transposeNeeds two S/H per tapS/H offset, noise, error accumulate

Shuffling architecturesDigital shuffling of tap coefficients

Shuffling of analog inputs in the current domain

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Practical Analog Equalizers

Coefficient shuffling

Lee, Razavi, CICC’01

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Practical Analog EqualizersXu, ISSCC’96200MHz, 9-tap, 0.6µm CMOS, 500mW

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Practical Analog Equalizers

Lee, CICC’01, 125MHz, 1000Base-T

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Receive EqualizersADC resolution

f

|H(f)|channel

1

QN

Analog pre-equalizers can reduce the resolution requirement for the ADC

Before pre-equalization

After pre-equalization

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Boost in CTF

E.g. 7-p 2-z CTF

See calculation in A. Hadji-Abdolhamid, D. Johns, ESSCIRC’03

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Implementing Equalizers

Digital receive equalizersAnalog receive equalizersTransmit equalizers

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Simple 2P/4P Tx Equalizing 5-Tap 2P/4P Tx

TNTP

A[0]

A[1]

A[2]

1/z

1/z

...

A[0]

B[0]

1/z

E[0]

TNT P

W/L

W/L

W/L

W/L

W/L

W/L

Transmit Equalizers

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Original 5-Tap 2-PAM/4-PAM equalizing transmitter

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Shared equalizing transmitter

Transmit Equalizers

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Summary

Digital receive equalizers are a solution with <2Gb/s and low ADC (~6-b) resolutions

Power is an issue

Mixed signal receive equalizers are hard to buildLower powerReduce ADC resolution requirements

High signaling rates – transmit equalization

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ReferencesR. Jain, P.T. Yang, T. Yoshino, "FIRGEN: a computer -aided design system for high performance FIR filter integrated circuits," IEEE Transactions on Signal Processing, vol.39, no.7, pp.1655 -1668, July 1991.R.A. Hawley, B.C. Wong, T.-J. Lin, J. Laskowski , H. Samueli, "Design techniques for silicon compiler implementations of high-speed FIR digital filters," IEEE Journal of Solid -State Circuits, vol.31, no.5, pp.656 -667, May 1996.W.L. Abbott, et al, “A digital chip with adaptive equalizer for PRML detection in hard-disk drives” IEEE International Solid -State Circuits Conference, Digest of Technical Papers, ISSCC’94, San Francisco, CA, Feb. 16-18, 1994, pp. 284 -285.D.J. Pearson, et al, “Digital FIR filters for high speed PRML disk read channels,” IEEE Journal of Solid -State Circuits, vol.30, no.12, pp.1517-1523, May 1995.S. Mita, et al, “A 150 Mb/s PRML chip for magnetic disk drives,” IEEE International Solid -State Circuits Conference, Digest of Technical Papers, ISSCC’96, San Francisco, CA, Feb. 8 -10, 1996, pp. 62 -63, 418.D. Moloney, J. O'Brien, E. O'Rourke, F. Brianti, "Low-power 200-Msps, area-efficient, five-tap programmable FIR filter," IEEE Journal of Solid -State Circuits, vol.33, no.7, pp.1134 -1138, July 1998.C.S.H. Wong, J.C. Rudell, G.T. Uehara, P.R. Gray, "A 50 MHz eight-tap adaptive equalizer for partial-response channels," IEEE Journal of Solid -State Circuits, vol.30, no.3, pp.228-234, March 1995.L.E. Thon, P. Sutardja, F.-S. Lai, G. Coleman, "A 240 MHz 8 -tap programmable FIR filter for disk-drive read channes," 1995 IEEE International Solid -State Circuits Conference, Digest of Technical Papers, ISSCC '95, pp.82-3, 343, San Francisco, CA, 15-17 Feb. 1995. R. B. Staszewski, K. Muhammad, P. Balsara, "A 550 -MSample/s 8 -Tap FIR Digital Filter for Magnetic Recording Read Channels," IEEE Journal of Solid -State Circuits, vol. 35, no. 8, pp. 1205 -1210, August 2000.S. Rylov, et al, “A 2.3 GSample/s 10-tap digital FIR filter for magnetic recording read channels,” IEEE International Solid -State Circuits Conference, Digest of Technical Papers, ISSCC’01, San Francisco, CA, Feb. 5-7, 2001, pp. 190 -191.J. Tierno, et at, “A 1.3 GSample/s 10-tap full -rate variable-latency self -timed FIR filter with clocked interfaces,” IEEE International Solid -State Circuits Conference, Digest of Technical Papers, ISSCC’02, San Francisco, CA, Feb. 3 -7, 2002, pp. 60 -61, 444.