AD797 Datasheet

8/3/2019 AD797 Datasheet

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Ultralow DistortionUltralow Noise Op Am

AD797

Rev. GInformation furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or otherrights of third parties that may result from its use. Specifications subject to change without notice. Nolicense is granted by implication or otherwise under any patent or patent rights of Analog Devices.Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.Tel: 781.329.4700 www.analog.comFax: 781.461.3113 2008 Analog Devices, Inc. All rights reserved

FEATURESLow noise0.9 nV/Hz typical (1.2 nV/Hz maximum) input voltage

noise at 1 kHz50 nV p-p input voltage noise, 0.1 Hz to 10 HzLow distortion

120 dB total harmonic distortion at 20 kHzExcellent ac characteristics

800 ns settling time to 16 bits (10 V step)110 MHz gain bandwidth (G = 1000)8 MHz bandwidth (G = 10)280 kHz full power bandwidth at 20 V p-p20 V/s slew rate

Excellent dc precision

80 V maximum input offset voltage1.0 V/C VOS driftSpecified for 5 V and 15 V power suppliesHigh output drive current of 50 mA

APPLICATIONSProfessional audio preamplifiersIR, CCD, and sonar imaging systemsSpectrum analyzersUltrasound preamplifiersSeismic detectors- ADC/DAC buffers

PIN CONFIGURATION

AD797

TOP VIEW

OFFSET NULL 1

IN 2

+IN 3

VS 4

DECOMPENSATIONAND DISTORTIONNEUTRALIZATION+VSOUTPUT

OFFSET NULL

8

7

6

5 0 0 8 4 6

- 0 0 1

Figure 1. 8-Lead Plastic Dual In-Line Package [PDIP] and

8-Lead Standard Small Outline Package [SOIC]

GENERAL DESCRIPTIONThe AD797 is a very low noise, low distortion operatiamplifier ideal for use as a preamplifier. The low noise0.9 nV/Hz and low total harmonic distortion of 120audio bandwidths give the AD797 the wide dynamic r

necessary for preamps in microphones and mixing conFurthermore, the AD797s excellent slew rate of 20 V110 MHz gain bandwidth make it highly suitable for lfrequency ultrasound applications.The AD797 is also useful in infrared (IR) and sonar imapplications, where the widest dynamic range is neceslow distortion and 16-bit settling time of the AD797 mideal for buffering the inputs to - ADCs or the outphigh resolution DACs, especially when the device is ucritical applications such as seismic detection or in spanalyzers. Key features such as a 50 mA output currenand the specified power supply voltage range of 5 V

make the AD797 an excellent general-purpose amplifi

0 0 8 4 6

- 0 0 2

5

010M

3

1

100

2

10

4

1M100k10k1k

FREQUENCY (Hz)

I N P U T V O L T A G E N O I S E ( n V / H z )

Figure 2. AD797 Voltage Noise Spectral Density

90

130300k

120

300100

110

100

100k30k10k3k1kFREQUENCY (Hz)

T H D ( d B )

0.001

0.0003

0.0001

T H D ( % )

MEASUREMENTLIMIT

Figure 3. THD vs. Frequency


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AD797

Rev. G | Page 2 of 20

TABLE OF CONTENTSFeatures .............................................................................................. 1

Applications ....................................................................................... 1

Pin Configuration ............................................................................. 1

General Description ......................................................................... 1 Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 5

ESD Caution .................................................................................. 5

Typical Performance Characteristics ............................................. 6

Theory of Operation ...................................................................... 11

Noise and Source Impedance Considerations ............................ 12

Low Frequency Noise ....................................................

Wideband Noise .............................................................

Bypassing Considerations ..............................................

The Noninverting Configuration .................................... The Inverting Configuration ..........................................

Driving Capacitive Loads ...............................................

Settling Time ..................................................................

Distortion Reduction ......................................................

Outline Dimensions ...........................................................

Ordering Guide ..............................................................

REVISION HISTORY9/08Rev. F to Rev. G

Changes to Input Common-Mode Voltage Range Parameter,Table 1 ................................................................................................ 31/08Rev. E to Rev. F

Changes to Absolute Maximum Ratings ....................................... 5Change to Equation 1 ..................................................................... 12Changes to the Noninverting Configuration Section ................ 13Updated Outline Dimensions ....................................................... 19Changes to Ordering Guide .......................................................... 207/05Rev. D to Rev. E

Updated Figure 1 Caption ............................................................... 1Deleted Metallization Photo ........................................................... 6Changes to Equation 1 ................................................................... 12Updated Outline Dimensions ....................................................... 19Changes to Ordering Guide .......................................................... 20

10/02Rev. C to Rev. D

Deleted 8-Lead CERDIP Package (Q-8) ......................... UEdits to Specifications .......................................................Edits to Absolute Maximum Ratings .................................Edits to Ordering Guide ....................................................Edits to Table I ..................................................................Deleted Operational Amplifiers Graphic ...........................Updated Outline Dimensions .............................................


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AD79


SPECIFICATIONSTA = 25C and VS= 15 V dc, unless otherwise noted.

Table 1.Supply AD797A AD797B

Parameter Conditions Voltage (V) Min Typ Max Min Typ Max UnitINPUT OFFSET VOLTAGE 5 V, 15 V 25 80 10 40 TMINto TMAX 50 125/180 30 60 V

Offset Voltage Drift 5 V, 15 V 0.2 1.0 0.2 0.6 VINPUT BIAS CURRENT 5 V, 15 V 0.25 1.5 0.25 0.9

TMINto TMAX 0.5 3.0 0.25 2.0 AINPUT OFFSET CURRENT 5 V, 15 V 100 400 80 200

TMINto TMAX 120 600/700 120 300 nAOPEN-LOOP GAIN VOUT= 10 V 15 V 1 20 2 20 V/

RLOAD= 2 k 1 6 2 10 V/VTMINto TMAX 1 15 2 15 V/VRLOAD= 600 1 5 2 7 V/VTMINto TMAX 14,000 20,000 14,000 20,000 V/V@ 20 kHz1

DYNAMIC PERFORMANCEGain Bandwidth Product G = 1000 15 V 110 110 MH

G = 10002 15 V 450 450 MHz3 dB Bandwidth G = 10 15 V 8 8 MHFull Power Bandwidth1 VOUT= 20 V p-p,

RLOAD= 1 k15 V 280 280 kHz

Slew Rate RLOAD= 1 k 15 V 12.5 20 12.5 20 V/Settling Time to 0.0015% 10 V step 15 V 800 1200 800 1200 ns

COMMON-MODE REJECTION VCM= CMVR 5 V, 15 V 114 130 120 130 dBTMINto TMAX 110 120 114 120 dB

POWER SUPPLY REJECTION VS = 5 V to 18 V 114 130 120 114 dBTMINto TMAX 110 120 130 120 dB

INPUT VOLTAGE NOISE f = 0.1 Hz to 10 Hz 15 V 50 50 f = 10 Hz 15 V 1.7 1.7 2.5 nV/f = 1 kHz 15 V 0.9 1.2 0.9 1.2 nVf = 10 Hz to 1 MHz 15 V 1.0 1.3 1.0 1.2 V

INPUT CURRENT NOISE f = 1 kHz 15 V 2.0 2.0 INPUT COMMON-MODE VOLTAGE RANGE 15 V 11 12 11 12

5 V 2.5 3 2.5 3 VOUTPUT VOLTAGE SWING RLOAD= 2 k 15 V 12 13 12 13 V

RLOAD= 600 15 V 11 13 11 13 VRLOAD= 600 5 V 2.5 3 2.5 3 V

Short-Circuit Current 5 V, 15 V 80 80 mAOutput Current3 5 V, 15 V 30 50 30 50 mA

TOTAL HARMONIC DISTORTION RLOAD= 1 k, CN = 50 pF,f = 250 kHz, 3 V rms

15 V 98 90 98 90 dB

RLOAD= 1 k,f = 20 kHz, 3 V rms

15 V 120 110 120 110 dB

INPUT CHARACTERISTICSInput Resistance

Differential 7.5 7.5 kCommon Mode 100 100 M

Input CapacitanceDifferential4 20 20 pFCommon Mode 5 5 pF


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AD797


Supply AD797A AD797BParameter Conditions Voltage (V) Min Typ Max Min Typ Max UnitOUTPUT RESISTANCE AV= 1, f = 1 kHz 3 3 mPOWER SUPPLY

Operating Range 5 18 5 18 VQuiescent Current 5 V, 15 V 8.2 10.5 8.2 10.5 mA

1 Full power bandwidth = slew rate/2 VPEAK .2 Specified using external decompensation capacitor.3 Output current for |VS VOUT| > 4 V, AOL> 200 k.4 Differential input capacitance consists of 1.5 pF package capacitance and 18.5 pF from the input differential pair.


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AD79


ABSOLUTE MAXIMUM RATINGSTable 2.Parameter RatingsSupply Voltage 18 V

Internal Power Dissipation @ 25C1

PDIP 1.3 W (TA 25C)/JA SOIC 0.9 W (TA 25C)/JA

Input Voltage VS Differential Input Voltage2 0.7 VOutput Short-Circuit Duration Indefinite within

maximum internalpower dissipation

Storage Temperature Range(N, R Suffix)

65C to +125C

Operating Temperature Range 40C to +85C Lead Temperature Range

(Soldering 60 sec)300C

1JA= 95C/W for the 8-lead PDIP; 155C/W for the 8-lead SOIC.2The AD797 inputs are protected by back-to-back diodes. To achieve lownoise, internal current-limiting resistors are not incorporated into the designof this amplifier. If the differential input voltage exceeds 0.7 V, the inputcurrent should be limited to less than 25 mA by series protection resistors.Note, however, that this degrades the low noise performance of the device.

Stresses above those listed under Absolute Maximum may cause permanent damage to the device. This is a rating only; functional operation of the device at theseother conditions above those indicated in the operatiosection of this specification is not implied. Exposure tmaximum rating conditions for extended periods maydevice reliability.

ESD CAUTION


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AD797


TYPICAL PERFORMANCE CHARACTERISTICS

0 0 8 4 6

- 0 0 4

20

00 20

15

5

5

10

10 15

I N P U T C O M M O N - M

O D E R A N G E ( V )

SUPPLY VOLTAGE (V)

Figure 4. Input Common-Mode Voltage Range vs. Supply Voltage

0 0 8 4 6

- 0 0

5

O U T P U T V O L T A G E S W I N G ( V )

20

00 20

15

5

5

10

10 15

SUPPLY VOLTAGE (V)

VOUT+VOUT

Figure 5. Output Voltage Swing vs. Supply Voltage

0 0 8 4 6

- 0 0 6

O U T P U T V O L T A G E S W I N G ( V p - p

)

LOAD RESISTANCE ( )

30

10

010 100 10k1k

20

VS = 5

VS = 15V

Figure 6. Output Voltage Swing vs. Load Resistance

0 0 8 4 6

- 0 0 7

HORIZONTAL SCALE (5sec/DIV)

V E R T I C A L S C A L E ( 0

. 0 1 V / D I V )

Figure 7. 0.1 Hz to 10 Hz Noise

0 0 8 4 6

- 0 0 8

TEMPERATURE (C)

I N P U T B I A S C U R R E N T ( A )

60 40 100 120806040200 20 2.0

1.5

1.0

0.5

0

Figure 8. Input Bias Current vs. Temperature

0 0 8 4 6

- 0 0 9

TEMPERATURE (C)

S H O R T - C I R C U I T C U R R E N T ( m A )

140

140

100

60

40

80

60

120

120100806040200 2040

SOURCE CURRENTSINK CURRENT

Figure 9. Short-Circuit Current vs. Temperature


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AD79


0 0 8 4 6

- 0 1 0

SUPPLY VOLTAGE (V)

Q U I E S C E N T S U P P L Y C U R R E N T ( m A )

205 150 10

11

6

9

7

8

10 +125C

+25C

55C

Figure 10. Quiescent Supply Current vs. Supply Voltage

0 0 8 4 6

- 0 1 1

SUPPLY VOLTAGE (V)

O U T P U T V O L T A G E ( V r m s

)

1 2

00 20

9

3

5

6

10 15

f = 1kHzRL = 600 G = +10

Figure 11. Output Voltage vs. Supply Voltage for 0.01% Distortion

0 0 8 4 6

- 0 1 2

STEP SIZE (V)

S E T T L I N G T I M E ( s )

1.0

010

0.6

0.2

2

0.4

0

0.8

864

0.0015%

0.01%

Figure 12. Settling Time vs. Step Size ()

0 0 8 4 6

- 0 1 3

FREQUENCY (Hz)

P O W E R S U P P L Y R E J E C T I O N ( d B )

201M

80

40

10

60

1

120

100

100k10k1k100

140

50

75

100

125

150

175

200

CMR

C O M M O N M O D E R E J E C T I O N ( d B )

PSR SUPPLY

PSR+SUPPLY

Figure 13. Power Supply and Common-Mode Rejection vs. Frequency

0 0 8 4 6

- 0 1 4

OUTPUT LEVEL (V)

T H D + N O I S E ( d B )

60

100

1200.01 0.1 101

80

RL = 600 G = +10f = 10kHzNOISE BW = 100kHz

VS = 5V

VS = 15V

Figure 14. Total Harmonic Distortion (THD) + Noise vs. Output Level

0 0 8 4 6

- 0 1 5

30

10

010k 100k 10M1M

20

5V SUPPLIES

15V SUPPLIESRL = 600

FREQUENCY (Hz)

O U T P U T V O L T A G E ( V p - p

)

Figure 15. Large-Signal Frequency Response


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AD797


0 0 8 4 6

- 0 1 6

5

010M

3

1

100

2

10

4

1M100k10k1k

FREQUENCY (Hz)

I N P U T V O L T A G E N

O I S E ( n V / H z )

Figure 16. Input Voltage Noise Spectral Density

0 0 8

4 6

- 0 1 7

FREQUENCY (Hz)

O P E N - L

O O P G A I N ( d B )

120

0100M

60

20

1k

40

100

100

80

10M1M100k10k

100

80

60

40

20

0

P H A S E M A R G I N ( D e g r e e s

)

PHASE MARGIN

GAIN

WITHOUTRS *

WITHOUTRS *

WITH RS *

WITH RS *

*RS = 100

*SEE FIGURE 25.

Figure 17. Open-Loop Gain and Phase Margin vs. Frequency

0 0 8 4 6

- 0 1 8

TEMPERATURE (C)

I N P U T O F F S E T C U R R E N T ( n A )

60 140 40 100 120806040200 20

300

150

0

150

300

UNDER COMPENSATED

OVERCOMPENSATED

Figure 18. Input Offset Current vs. Temperature

0 0 8 4 6

- 0 1 9

TEMPERATURE (C)

S L E W

R A T E ( V / s )

G A I N / B A N D W I D T H P R O D U C T ( M H z

( G =

1 0 0 0 ) )

60 140 40 100 120806040200 20

120

110

100

90

80

35

30

25

20

15

GAIN/BANDWIDTH PRODUCT

SLEW RATE

RISING EDGE

SLEW RATEFALLING EDGE

Figure 19. Slew Rate and Gain/Bandwidth Product vs. Temperature

0 0 8 4 6

- 0 2 0

LOAD RESISTANCE ( )

O P E N - L

O O P G A I N ( d B )

100 10k1k

160

100

120

140

Figure 20. Open-Loop Gain vs. Load Resistance

0 0 8 4 6

- 0 2 1

FREQUENCY (Hz)

M A G N I T U D E O F O U T P U T I M P E D A N C E ( )

100

0.0110 1M

10

0.1

100

1

10k 100k1k

WITHOUT C N*

WITH C N**SEE FIGURE 32.

Figure 21. Magnitude of Output Impedance vs. Frequency


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AD79


VOUT

1k

1k

20pF

VIN

AD797

*

VS

+VS

*43

6

72

0 0 8 4 6

- 0 2 2

*SEE FIGURE 35.

Figure 22. Inverter Connection

0 0 8 4 6

- 0 2 3

10090

10

0%

5V

1s

Figure 23. Inverter Large-Signal Pulse Response

0 0 8 4 6

- 0 2

4

100

90

10

0%

50mV 100ns

Figure 24. Inverter Small-Signal Pulse Response

VOUT

100

600 VIN

AD797

**

VS

+VS

RS *

*VALUE OF SOURCE RESISTANCE(SEE THE NOISE AND SOURCE IMPEDANCECONSIDERATIONS SECTION).

*SEE FIGURE 35.

**43

6

72

0 0 8 4 6

- 0 2 5

*

Figure 25. Follower Connection

0 0 8 4 6

- 0 2 6

10090

10

0%

5V 1s

Figure 26. Follower Large-Signal Pulse Response

0 0 8 4 6

- 0 2

7

100

90

10

0%

50mV 100ns

Figure 27. Follower Small-Signal Pulse Response


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AD797


0 0 8 4 6

- 0 2 8

100

90

10

0%

50mV 500ns

Figure 28. 16-Bit Settling Time Positive Input Pulse 0 0 8 4 6

- 0 2 9

100

90

10

0%

50mV 500ns

Figure 29. 16-Bit Settling Time Negative Input Pulse


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AD79


THEORY OF OPERATIONThe architecture of the AD797 was developed to overcomeinherent limitations in previous amplifier designs. Previousprecision amplifiers used three stages to ensure high open-loopgain (seeFigure 30) at the expense of additional frequency com-pensation components. Slew rate and settling performance areusually compromised, and dynamic performance is not adequatebeyond audio frequencies. As can be seen inFigure 30, the firststage gain is rolled off at high frequencies by the compensationnetwork. Second stage noise and distortion then appears at theinput and degrade performance. The AD797, on the other hand,uses a single ultrahigh gain stage to achieve dc as well as dynamicprecision. As shown in the simplified schematic (Figure 31),Node A, Node B, and Node C track the input voltage, forcingthe operating points of all pairs of devices in the signal path tomatch. By exploiting the inherent matching of devices fabricated onthe same IC chip, high open-loop gain, CMRR, PSRR, and lowVOSare guaranteed by pairwise device matching (that is, NPNto NPN and PNP to PNP), not by an absolute parameter such asbeta and the early voltage.

R1

R1

C1

g m

g m

GAIN = g m R1 5 10 6

GAIN = g m R1 A2 A3

C1

R2

BUFFER

BUFFER

RL

RL

VOUT

VOUT

a.

b.

A2 A3

C2

0 0 8 4 6

- 0 3 0

Figure 30. Model of AD797 vs. That of a Typical Three-Stage Amplifier

R2R1 I5

VOUT

Q1 Q2+IN IN

R3

Q5

C

Q6

I7I1 I4I6

Q12 Q8

Q9

Q11

Q10Q3 Q7

Q4

A B

CN

CC

VSS

VCC

0 0 8 4 6

- 0 3 1

Figure 31. AD797 Simplified Schematic

This matching benefits not just dc precision, but, because it holdsup dynamically, both distortion and settling time are also reduced.This single stage has a voltage gain of >5 106 and VOS< 80 V,while at the same time providing a THD + noise of less than120 dB and true 16-bit settling in less than 800 ns.

The elimination of second-stage noise effects has the abenefit of making the low noise of the AD797 (


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AD797


NOISE AND SOURCE IMPEDANCE CONSIDERATIONSThe AD797 ultralow voltage noise of 0.9 nV/Hz is achievedwith special input transistors running at nearly 1 mA of collectorcurrent. Therefore, it is important to consider the total input-referred noise (eNtotal), which includes contributions from voltage

noise (eN), current noise (iN), and resistor noise (4 kTRS).2/122 ])(4[ SN SN N RikTRetotal e ++= (1)

where RS is the total input source resistance.This equation is plotted for the AD797 inFigure 33. Becauseoptimum dc performance is obtained with matched sourceresistances, this case is considered even though it is clear fromEquation 1 that eliminating the balancing source resistancelowers the total noise by reducing the total RS by a factor of 2.At very low source resistance (RS< 50 ), the voltage noise of theamplifier dominates. As source resistance increases, the Johnsonnoise of RS dominates until a higher resistance of RS > 2 k is

achieved; the current noise component is larger than theresistor noise.

0 0 8 4 6

- 0 3 3

100

1

0.1

10

10 100 1000 10000

SOURCE RESISTANCE ( )

N O I S E ( n V / H z )

TOTAL NOISE

RESISTORNOISEONLY

Figure 33. Noise vs. Source Resistance

The AD797 is the optimum choice for low noise performance if the source resistance is kept


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AD79


BYPASSING CONSIDERATIONSTaking full advantage of the very wide bandwidth and dynamicrange capabilities of the AD797 requires some precautions.First, multiple bypassing is recommended in any precisionapplication. A 1.0 F to 4.7 F tantalum in parallel with 0.1 F

ceramic bypass capacitors are sufficient in most applications.When driving heavy loads, a larger demand is placed on thesupply bypassing. In this case, selective use of larger values of tantalum capacitors and damping of their lead inductance withsmall-value (1.1 to 4.7 ) carbon resistors can achieve animprovement.Figure 35summarizes power supply bypassingrecommendations.

USE SHORTLEAD LENGTHS(200 k/

Table 4. Values for Follower with Gain Circuit

Gain R1 R2 CL Noise(Excluding RS)

2 1 k 1 k 20 pF 3.0 nV/Hz2 300 300 10 pF 1.8 nV/Hz10 33.2 300 5 pF 1.2 nV/Hz20 16.5 316 1.0 nV/Hz>35 10 (G 1) 10 0.98 nV/H
http://www.analog.com/AD600http://www.analog.com/AD600http://www.analog.com/AD600http://www.analog.com/AD600


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AD797


The I-to-V converter is a special case of the follower configu-ration. When the AD797 is used in an I-to-V converter, forexample as a DAC buffer, the circuit shown inFigure 39shouldbe used. The value of CLdepends on the DAC, and if CLis greaterthan 33 pF, a 100 series resistor is required. A bypassed balancingresistor (RS and CS) can be included to minimize dc errors.

7

*

*

V O U T

+VS

VS

AD797

0 0 8 4 6

- 0 3 9

R1

RS

IIN

CS

6

3 4

100

600

20pF TO 120pF

2

*USE THE POWER SUPPLY BYPASSING SHOWN IN FIGURE 35. Figure 39. I-to-V Converter Connection

THE INVERTING CONFIGURATIONThe inverting configuration (seeFigure 40) presents a low inputimpedance, R1, to the source. For this reason, the goals of bothlow noise and input buffering are at odds with one another.Nonetheless, the excellent dynamics of the AD797 makesit the preferred choice in many inverting applications, andwith careful selection of feedback resistors, the noise penaltiesare minimal. Some examples are presented inTable 5andFigure 40.

7

*

*

V OU T

V IN

+VS

VS

AD797

0 0 8 4 6

- 0 4 0

R2

RL

RS

R1

CL

6

3 4

2

*USE THE POWER SUPPLY BYPASSING SHOWN IN FIGURE 35. Figure 40. Inverting Amplifier Connection

Table 5. Values for Inverting Circuit

Gain R1 R2 CL Noise(Excluding RS)1 1 k 1 k 20 pF 3.0 nV/Hz1 300 300 10 pF 1.8 nV/Hz10 150 1500 5 pF 1.8 nV/Hz

DRIVING CAPACITIVE LOADSThe capacitive load driving capabilities of the AD797 aredisplayed inFigure 41. At gains greater than 10, usually nospecial precautions are necessary. If more drive is desirablhowever, the circuit shown inFigure 42should be used. For

example, this circuit allows a 5000 pF load to be driven clat a noise gain 2.

0 0 8 4 6

- 0 4 1

100nF

10nF

1pF100101 1

1nF

100pF

10pF

CLOSED-LOOP GAIN

C

k

A P A C I T I V E L O A D D R I V E C A P A B I L I T Y

Figure 41. Capacitive Load Drive Capability vs. Closed-Loop Gain

7

*

*

V OU T

V IN

+VS

VS

AD797

0 0 8 4 6

- 0 4 2

C1

20pF

200pF

6

3 4

2

33

100

1k

1k

*USE THE POWER SUPPLY BYPASSING SHOWN IN FIGURE 35. Figure 42. Recommended Circuit for Driving a High Capacitance Load

SETTLING TIMEThe AD797 is unique among ultralow noise amplifiers in settles to 16 bits (


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AD797


Differential Line Receiver

The differential receiver circuit of Figure 46is useful for many applications, from audio to MRI imaging. The circuit allowsextraction of a low level signal in the presence of common-mode noise. As shown inFigure 47, the AD797 provides this

function with only 9 nV/Hz noise at the output.Figure 48 shows the AD797 20-bit THD performance over the audio bandand the 16-bit accuracy to 250 kHz.

**

**

AD797

0 0 8 4 6

- 0 4 6

6

2

3

1k

DIFFERENTIALINPUT

1k

1k

1k

20pF

50pF*

20pF

VS

+VS

4

7

8

V O UT

OPTIONALUSE THE POWER SUPPLY BYPASSINGSHOWN IN FIGURE 35.

***

Figure 46. Differential Line Receiver

0 0 8 4 6

- 0 4 7

16

610M

12

8

100

10

10

14

1M100k10k1k

FREQUENCY (Hz)

O U T P U T V O L T A G E

N O I S E ( n V / H z )

Figure 47. Output Voltage Noise Spectral Density

for Differential Line Receiver

0 0 8 4 6

- 0 4 8

FREQUENCY (Hz)

T H D ( d B )

T H D

( % )

90

300k

120

130300100

110

100

100k30k10k3k1k

0.003

0.0003

0.001

0.0001

WITHOUTOPTIONAL50pF C N

WITHOPTIONAL

50pF C N

MEASUREMENTLIMIT

Figure 48. Total Harmonic Distortion (THD) vs. Frequency

for Differential Line Receiver

A General-Purpose ATE/Instrumentation I/O Driver

The ultralow noise and distortion of the AD797 can be

combined with the wide bandwidth, slew rate, and load drof a current feedback amplifier to yield a very wide dynamrange general-purpose driver. The circuit shown inFigure 49 combines the AD797 with the AD811 in just such anapplication. Using the component values shown, this circucapable of better than 90 dB THD with a 5 V, 500 kHz signal. The circuit is, therefore, suitable for driving a highresolution ADC as an output driver in automatic test equip(ATE) systems. Using a 100 kHz sine wave, the circuit dri600 load to a level of 7 V rms with less than 109 dB Tand a 10 k load at less than 117 dB THD.

*

7

*

*

*

+VS

+VS

VS

AD797

0 0 8 4 6

- 0 4 9

22pF

2k

649

649

1k

R2

6

3 4

2

7

AD811 6

2 4

3

VS

*USE THE POWER SUPPLY BYPASSING SHOWN IN FIGURE 35.

VOUTVIN

Figure 49. A General-Purpose ATE/Instrumentation I/O Driver


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AD797


OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MS-001CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. 0

7 0 6 0 6 - A

0.022 (0.56)0.018 (0.46)0.014 (0.36)

SEATINGPLANE

0.015(0.38)MIN

0.210 (5.33)MAX

0.150 (3.81)0.130 (3.30)0.115 (2.92)

0.070 (1.78)0.060 (1.52)0.045 (1.14)

8

1 4

5 0.280 (7.11)0.250 (6.35)0.240 (6.10)

0.100 (2.54)BSC

0.400 (10.16)0.365 (9.27)0.355 (9.02)

0.060 (1.52)MAX

0.430 (10.92)MAX

0.014 (0.36)0.010 (0.25)0.008 (0.20)

0.325 (8.26)0.310 (7.87)0.300 (7.62)

0.195 (4.95)0.130 (3.30)0.115 (2.92)

0.015 (0.38)GAUGEPLANE

0.005 (0.13)MIN

Figure 55. 8-Lead Plastic Dual In-Line Package [PDIP]

Narrow Body (N-8)Dimensions shown in inches and (millimeters)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-012-AA

0 1 2 4 0 7 - A

0.25 (0.0098)0.17 (0.0067)

1.27 (0.0500)0.40 (0.0157)

0.50 (0.0196)0.25 (0.0099)

45

80

1.75 (0.0688)1.35 (0.0532)

SEATINGPLANE

0.25 (0.0098)0.10 (0.0040)

41

8 5

5.00 (0.1968)4.80 (0.1890)

4.00 (0.1574)3.80 (0.1497)

1.27 (0.0500)BSC

6.20 (0.2441)5.80 (0.2284)

0.51 (0.0201)0.31 (0.0122)

COPLANARITY0.10

Figure 56. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-8)Dimensions shown in millimeters and (inches)


19/20

AD79


ORDERING GUIDEModel Temperature Range Package Description Package OptionAD797AN 40C to +85C 8-Lead Plastic Dual In-Line Package [PDIP] N-8AD797ANZ1 40C to +85C 8-Lead Plastic Dual In-Line Package [PDIP] N-8AD797AR 40C to +85C 8-Lead Standard Small Outline Package [SOIC_N] R-8AD797AR-REEL 40C to +85C 8-Lead Standard Small Outline Package [SOIC_N] R-8AD797AR-REEL7 40C to +85C 8-Lead Standard Small Outline Package [SOIC_N] R-8AD797ARZ1 40C to +85C 8-Lead Standard Small Outline Package [SOIC_N] R-8AD797ARZ-REEL1 40C to +85C 8-Lead Standard Small Outline Package [SOIC_N] R-8AD797ARZ-REEL71 40C to +85C 8-Lead Standard Small Outline Package [SOIC_N] R-8AD797BR 40C to +85C 8-Lead Standard Small Outline Package [SOIC_N] R-8AD797BR-REEL 40C to +85C 8-Lead Standard Small Outline Package [SOIC_N] R-8AD797BR-REEL7 40C to +85C 8-Lead Standard Small Outline Package [SOIC_N] R-8AD797BRZ1 40C to +85C 8-Lead Standard Small Outline Package [SOIC_N] R-8AD797BRZ-REEL1 40C to +85C 8-Lead Standard Small Outline Package [SOIC_N] R-8AD797BRZ-REEL71 40C to +85C 8-Lead Standard Small Outline Package [SOIC_N] R-8

1 Z = RoHS Compliant Part.

Documents

AD797 Datasheet