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    TLH5066

    MF5Univers

    alMonolithicSwitchedC

    apacitorFilter

    February1995

    MF5 Universal Monolithic Switched Capacitor FilterGeneral Descript ion

    The MF5 consists of anextremelyeasyto use general pur-pose CMOS active filter building block and an uncommittedop amp The filter building block together with an external

    clock and a fewresistors can produce various second orderfunctions The filter building block has 3 output pins One ofthe output pins can be configured to perform highpass all-pass or notch functions and the remaining 2 output pins

    perform bandpass and lowpass functions The center fre-quency of the filter can be directly dependent on the clockfrequency or it can depend on both clock frequency andexternal resistor ratios The uncommitted op amp can be

    used for cascading purposes for obtaining additional all-pass and notch functions or for various other applicationsHigher order filter functions can be obtained by cascading

    several MF5s or by using the MF 5 in conjuction with theMF10 (dual switched capacitor filter building block) TheMF5 is functionally compatible with the MF10 Any of theclassical filter configurations (such as Butterworth Bessel

    Cauer and Chebyshev) can be formed

    FeaturesY Low costY 14-pin DIP or 14-pin Surface Mount (SO) wide-body

    package

    Y Easy to useY Clock to center frequency ratio accuracy g 06%Y Filter cutoff frequency stability directly dependent on

    external clock qualityY Low sensitivity to external component variations

    Y Separate highpass (or notch or allpass) bandpass low-pass outputs

    Y foc Q range up to 200 kHzY Operation up to 30 kHz (typical)Y Additional uncommitted op-amp

    Block and Connectio n Diagrams

    TLH50661

    All Packages

    TLH50662Top View

    Order Number MF5CNSee NS Package Numb er N14A

    Order Number MF5CWMSee NS Package Number M14B

    C1995 National Semiconductor Corporation RRD-B30M115Printedin U SA

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    Absolute Maximum RatingsIf MilitaryAerospace specified devices are requiredplease contact the National Semiconductor Sales

    OfficeDistributors for availability and specifications

    SupplyVoltage (Va b Vb ) 14V

    PowerDissipation TA e 25C (note 1) 500 mW

    Storage Temp 150C

    Soldering InformationN Package 10sec 260CSO Package Vaporphase(60 sec) 215C

    Infrared (15sec) 220C

    See AN-450 Surface Mounting Methods and Their Effecton Product Reliability for other methods of soldering sur-

    face mount devices

    Input Voltage (any pin) Vb s Vin s Va

    OperatingTempRange TMINs TA s TMAX

    MF5CN MF5CWM 0C s TA s 70C

    Electrical Characteristic s Va e 5V g 05% Vb e b 5Vg 0 5% unless otherwise noted Boldface limitsapply over temperatureTMIN s TA s TMAX For all other limits TAe 25C

    Typical Tes ted Des ig n

    Parameter Condit io ns(Note 6)

    Limit Limit Units(No te 7) (No te 8)

    Supply Voltage Min 8 V(Va b Vb ) Max 14 V

    Maximum Supply Current Clock applied to Pin 8 45 60 mANo InputSignal

    Clock Filter Output 10 mV

    Feedthrough Op-amp Output 10 mV

    Filter Electr ical Characterist ics Va e 5Vg 05% Vb e b 5Vg 05% unless otherwise noted Boldfacelimits apply over temperatureTMIN s TA s TMAX For all other limits TA e 25C

    Typical Test ed Design

    Parameter Co nditions(Note 6)

    Limit Limit Units(No t e 7) (No te 8)

    Center Frequency Max 30 20 kHzRange (fo) Min 01 0 2 Hz

    Clock Frequency Max 15 1 0 MHzRange (fCLK) Min 50 10 Hz

    Clock to CenterIdeal

    Vpin9e a 5V 5011g 02% 5011 g 15%FrequencyRatio

    Qe 10 FCLKe 250 kHz

    (fCLKfo) Mode1 Vpin9e b 5V 10004 g 02% 10004 g 15%

    FCLKe 500 kHzfCLKfoTemp Vpin9e a 5V g 10 ppmCCoefficient (501 CLK ratio)

    Vpin9e b 5V g 20 ppmC(1001 CLK ratio)

    Q Accuracy (Max)Ideal

    Vpin9e a 5V g 10 %(Note 2)

    Qe 10 FCLKe 250 kHz

    Mode1 Vpin9e b 5V g 10 %FCLKe 500 kHz

    Q Temperature Vpin9e a 5V b 200 ppmCCoefficient (501 CLK ratio)

    Vpin9e b 5V b 70 ppmC(1001 CLK ratio)

    DC Lowpass Gain Mode 1g 02 dB

    Accuracy (Max) R1e R2 e 10kX

    DC Offset Vos1 g 50 mV

    Voltage (Max) Vos2 Vpin9e a 5V b 185 mV

    Vos3 (501 CLK ratio) a 115 mV

    (Note 3) Vos2 Vpin9e b 5V b 310 mV

    Vos3 (1001 CLK ratio) a 240 mV

    2

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    Filter Electrical Characteristic s Va e 5Vg 05% Vb e b 5Vg 05% unless otherwise noted Boldfacelimits apply over temperatureTMIN s TA s TMAXFor all other limits TAe 25C(Continued)

    Typical Tes ted Design

    Parameter Condit ions(Note 6)

    Limit Limit Unit s( No te 7) (No t e 8)

    Output BP LP pins RLe 5 kX g 40 g 38 VSwing(Min) NAPHP pin RLe 35 kX g 42 g 38 V

    Vpin9e a 5V 83 dB

    Dynamic Range (501 CLK ratio)(Note 4) Vpin9e b 5V 80 dB

    (1001 CLK ratio)

    MaximumOutput Short Circuit Source 20 mACurrent(Note 5) Sink 30 mA

    OP-AMP Electr ical Characterist ics Va e a 5Vg 0 5% Vb e b 5Vg 05% unless other noted Bold-face limits apply over temperatureTMIN s TA s TMAXFor all other limits TAe 25C

    Typical Tested Design

    Parameter Condit ions(Note 6)

    Limit Limit Units(Not e 7) (Not e 8)

    Gain Bandwidth Product 2 5 MHz

    OutputVoltage S wing (M in) R Le 35 kX g 42 g 38 V

    Slew Rate 7 0 Vms

    DC Open-Loop Gain 80 db

    Input Offset Voltage (Max) g 50 g 20 mV

    Input Bias Current 10 pA

    MaximumOutputSource

    20 mAShortCircuitCurrent(Note5) Sink 3 0 mA

    Logic Input Characteristics Boldface limits apply over temperatureTMIN s TA s TMAXAll other limits TA e 25C

    Typical Test ed Design

    Paramet er Conditions(Note 6)

    Limit Limit Unit s(No t e 7) (No t e 8)

    CMOS Clock Min Logical 1 30 VInput Input Voltage Va e a 5V Vb e b 5V

    MaxLogical 0 VLSh e 0V b 30 V

    Input VoltageMin Logical 1 80 VInput Voltage Va e a 10V Vb e 0V

    MaxLogical 0 VLSh e a 5V 20 VInput Voltage

    TTL Clock MinLogical 1 20 VInput Input Voltage Va e a 5V Vb e b 5V

    MaxLogical 0 VLSh e 0V 08 VInput Voltage

    Note 1 The typical junction-to-ambient thermal resistance (i J A) of the 14 pin N package is 160CW and 82CW for the M package

    Note 2 The accuracy of the Q value is a function of the center frequency (fo) This is illustrated in the curves under the heading Typical Performance

    Characteristics

    Note 3 Vos1 Vos2 and Vos3 refer to the internal offsets as discussed in the Application Informations ection 34

    Note 4 For g 5V supplies the dynamic range is referenced to 282V rms (4V peak) where the wideband noise overa 20 kHz bandwidth is typically200mV rms for

    the MF5 with a 501 CLK ratio and 280mV rms forthe MF5 with a 1001 CLK ratio

    Note 5 The short circuit sourcecurrent is measured byforcing theoutputthatis beingtestedto itsmaximumpositive voltageswingand then shorting that outputto

    the negative supply The short circuitsink current is measured byforcingthe outputthat is being tested to its maximum negative voltage swing andthen shorting

    that output to the positive supply These are the worst case conditions

    Note 6 Typicals are at 25C and represent most likely parametric normNote 7 Guaranteed and 100% tested

    Note 8 Guaranteed but not 100% tested These limits are not used to calculate outgoing quality levels

    3

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    Pin Descriptio nLP(14) BP(1) The second order lowpass bandpassNAPHP(2) and notchallpasshighpass outputs The

    LP and BP outputs can typicallysink 1 mA

    and source 3 mA The NAPHP outputcan typicallysink 15 mA and source 3mAEach outputtypically swings to within1V of each supply

    INV1(3) The inverting input of the summingopamp of the filter This is a high impedanceinput butthe non-inverting inputisinternally tied to AGNDmakingINV1

    behave like a summingjunction (lowimpedance currentinput)

    S1(4) S1 is a signal input pin used in the allpass

    filter configurations (seemodes 4 and 5)The pin should bedriven with a sourceimpedance of less than 1 kX If S1is notdrivenwith a signal itshould betied to

    AGND (mid-supply)SA(5) This pin activates a switchthatconnects

    one of the inputs of the filters secondsummer to either AGND (SA tied to Vb )or to the lowpass (LP) output (SA tied toVa )This offers the flexibility neededfor

    configuring the filter in its various modes

    of operation50100(9) This pin is usedto settheinternal clock to

    centerfrequencyratio (fCLKfo) of the

    filter Bytying the pin to Va anfCLKforatio of about 501 (typically5011 g

    02%) is obtained Tyingthe 50100 pin toeither AGNDor Vb willset the fCLKforatio to about 1001 (typically10004 g

    02%)AGND(11) This is the analog ground pin This pin

    should be connected to the systemground fordual supplyoperation or biasedto mid-supplyfor singlesupply operationFor a further discussion of mid-supply

    biasing techniques see theApplicationsInformation(Section32) For optimumfilterperformance a clean groundmust

    be provided

    Va (6) Vb (10) These arethe positive and negativesupplypinsThe MF5 will operate overatotal supplyrange of 8V to 14V

    Decoupling the supplypins with 01 mFcapacitors is highlyrecommended

    CLK(8) This is the clock input for the filterCMOSorTTL logic level clocks canbe

    accomodated bysetting the L Sh pintothe levels described in the L Sh pindescriptionFor optimumfilterperformance a 50% dutycycle clock is

    recommended for clock frequenciesgreater than 200 kHzThis gives each opamp the maximumamount of time to

    settle to a new sampledinputL Sh(7) This pin allows the MF5 to accommodate

    either CMOS or TTL logic level clocks Fordual supply operation (ie g 5V) a CMOSorTTL logic level clock can beaccepted ifthe LSh pin is tied to mid-supply (AGND)which should be the system ground

    For single supplyoperation the L Sh pinshould be tied to mid-supply(AGND) foraCMOS logic level clock The mid-supplybias shouldbe a verylow impedance

    node See Applications Information forbiasing techniques For a TTL logic levelclock the L Sh pin shouldbe tiedto Vb

    which should be the system groundINV2(12) This is the invertinginput of the

    uncommitted op amp This is a veryhighimpedance input butthe non-inverting

    input is internallytiedto AGND makingINV2 behave likea summing junction(low-impedance currentinput)

    Vo2(13) This is the outputof the uncommitted opamp It will typicallysink 15 mA andsource 30 mAIt will typically swing towithin 1V of eachsupply

    Typical Perf ormance Characteristic s

    Deviation ofFCLK

    Fov s No mi nal Q De vi at io n o f

    FCLK

    Fovs Nominal Q

    OPAMP Output Voltage

    Swing vs Temperature

    TL H 50663

    4

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    Typical Perf ormanceCharacteristics (Continued)

    Supply Current vs Temperature

    TLH50664

    10 Definitions of Termsf CLK the frequency of the external clock signal applied topin 8

    f o center frequency of the second order function complexpole pair fo is measuredat the bandpass output of the MF5

    and is the frequency of maximumbandpass gain (Figure 1)

    f notch the frequency of minimum (ideally zero) gain at thenotch output

    f z the center frequency of the second order complex zeropair if any If fz is different from fo and ifQz is high itcanbe

    observed as the frequency of a notch at the allpass output(Figure 10)

    Q quality factor of the 2nd order filter Q is measured atthe bandpass outputof the MF5 and is equal to fo dividedbytheb 3dB bandwidth of the 2nd order bandpass filter (Fig-ure 1) The value of Q determines the shape of the 2ndorder filter responses as shown in Figure 6

    Qzthe quality factorof the second order complexzero pair

    if any Qz is related to the allpass characteristic which iswritten

    HAP(s) e

    HOAPs2 b

    s0 o

    Qza 0 o2J

    s2 a s0 o

    Qa 0 o2

    where Qz e Q for an all-pass response

    HOBP the gain (in VV) of the bandpass output at fe fo

    HOLP the gain (in VV) of the lowpass outputas fx 0 Hz(Figure 2)

    HOHP the gain (in VV) of the highpass output asfx fclk2 (Figure 3)

    HON the gain (in VV) of the notch output as fx 0 Hz andas fx fclk2 when the notch filter has equal gain aboveand below the center frequency (Figure 4) When the low-frequency gain differs from the high-frequency gain as in

    modes 2 and 3a (Figures 11 and8) the two quantities be-low are used in place of HON

    HON1 the gain (in VV) of the notch output as fx 0 Hz

    HON2 the gain (in VV) of the notch output as fx fclk2

    (a) 50665 (b) 50666

    HBP(s) e HOBP

    0o

    Q s

    s2a s0o

    Qa 0 o2

    Qe fo

    fH b fL foe 0fLfH

    fLe fob 1

    2Qa 0

    1

    2QJ2

    a 1JfHe fo

    1

    2Qa 0

    1

    2QJ2

    a 1J0 o e 2q fo

    FIGURE 1 2nd-Order Bandpass Response

    (a) TL H 50667 (b) TL H 50668

    HLP(s) e HOLP0 o2

    s2a s0 o

    Qa 0 o2

    fce foc 01 b 1

    2Q2Ja 01 b 1

    2Q2J2

    a 1

    fp e fo01 b 1

    2Q2

    HOPe HOLPc 1

    1

    Q01 b 1

    4Q2

    FIGURE 22nd-Order Low-Pass Response

    (a) 0669

    FIGURE 3 2nd-Order High-Pass Response

    (b) 506610

    HHP(s)e HOHPs2

    s2a s0o

    Qa 0o2

    fce foc01b 12Q2Ja 01b 12Q2J2

    a 1(b 1

    fp e foc 01 b 1

    2Q2(b 1

    HOPe HOHPc 1

    1

    Q01 b 1

    4Q2

    5

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    20 Modes o f OperationThe MF5 is a switched capacitor (sampled data) filter Tofully describe its transfer functions a time domain approach

    is appropriate Since this is cumbersome and since theMF5 closely approximates continuous filters the followingdiscussion is based on the well known frequency domain

    Each MF5 can produce a full 2nd order function See Table

    1 for a summaryof the characteristics of the various modes

    MODE 1 Notch 1 Bandpass Lowpass Outputs

    fnotch e fo (SeeFigure 7)

    fo e center frequency of the complex pole pair

    e fCLK

    100or

    fCLK

    50

    fnotch e center frequency of the imaginary zero paire fo

    HOLP e Lowpass gain (as fx 0) e b R2

    R1

    HOBP e Bandpass gain (at fe fo) e b R3

    R1

    HON e Notch outputgainas fx 0

    fx fCLK2(e

    b R2

    R1

    Q e fo

    BWe

    R3

    R2

    BW e theb 3 dB bandwidth of the bandpass output

    Circuit dynamics

    HOLPe HOBP

    Q

    orHOBP e HOLPc Qe HONc Q

    HOLP(peak) j Q c HOLP(for high Qs)

    MODE 1a Non-Inverting BPLP (See Figure 8)

    fo e fCLK

    100or

    fCLK

    50

    Q e R3

    R2

    HOLP e b 1 HOLP(peak) j Q c HOLP (for high Qs)

    HOBP1 e b

    R3

    R2

    HOBP2 e 1 (non-inverting)

    Circuit dynamics HOBP1e Q

    Note VINshould be driven from a low impedance (k 1 kX )

    TLH506616

    FIGURE 7 MODE 1

    TLH506617

    FIGURE 8MODE 1a

    7

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    20 Modes of Operation (Continued)

    MODE 2 Notch 2 Bandpass Lowpass f notchk fo

    (SeeFigure 9)

    fo e center frequency

    e fCLK

    100 0R2

    R4a 1 or

    fCLK

    500R2

    R4a 1

    fnotch e fCLK

    100or f

    CLK

    50

    Q e quality factor of the complex pole pair

    e 0R2R4 a 1

    R2R3

    HOLP e Lowpass output gain (as fx 0)

    e b R2R1

    R2R4 a 1

    HOBP e Bandpass output gain (at fe fo) e b R3R1

    HON1 e Notch output gain (as fx 0)

    e b R2R1

    R2R4 a 1

    HON2 e Notch output gain

    as fx

    fCLK

    2 Je b R2R1Filter dynamics HOBPe Q 0HOLPHON

    2

    e Q 0HON1

    HON2

    MODE 3 Highpass Bandpass Lowpass Outputs

    (SeeFigure 10 )

    fo e fCLK

    100c 0

    R2

    R4or

    fCLK

    50c 0

    R2

    R4

    Q e quality factor of the complex pole pair

    e 0R2R4

    c R3R2

    HOHP e Highpass gainas fx

    fCLK

    2 Je b R2

    R1

    HOBP e Bandpass gain (at fe fo) e b R3

    R1

    HOLP e Lowpass gain (as fx 0)e b R4

    R1

    Circuit dynamicsR2

    R4e

    HOHP

    HOLP HOBPe 0HOHPc HOLP c Q

    HOLP(peak) j Q c HOLP(for high Qs)

    HOHP(peak) j Q c HOHP(for high Qs)

    TLH506618

    FIGURE 9MODE 2

    TLH506619

    FIGURE 10 MODE 3

    In Mode 3 the feedback loop is closed around

    the inputsumming amplifier the finite GBW prod-

    uct of this op amp causes a s light Q enhance-

    ment Ifthisis a problemconnect a small capaci-

    tor (10 pF 100 pF) across R 4 to provide some

    phase lead

    8

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    20 Modes o f Operation (Continued)

    MODE 3a HPBPLP and Notch with External Op amp(See Figure 11)

    fo e fCLK

    100c 0

    R2

    R4or

    fCLK

    50c 0

    R2

    R4

    Q e

    0

    R2

    R4

    c R3

    R2

    HOHP e b R2

    R1

    HOBP e b R3

    R1

    HOLP e b R4

    R1

    fn e notch frequency e fCLK

    100 0Rh

    Rlor

    fCLK

    500Rh

    Rl

    Hon e gain of notch at fe foe Q

    Rg

    RlHOLPb

    Rg

    RhHOHPJ

    Hn1 e gain of notch (as fx 0)e Rg

    Rlc HOLP

    Hn2 e gain of notchas fx

    fCLK

    2 Je b Rg

    Rhc HOHP

    MODE 4Allpass BandpassLowp ass Outputs (SeeFigure 12)

    fo e center frequency

    e fCLK

    100or

    fCLK

    50

    fze center frequencyof the complex zero pairj fo

    Q e fo

    BWe

    R3

    R2

    Qz e quality factor of complex zero pair e R3

    R1

    For AP output make R1 e R2

    H OAP e Allpass gainat0 k fk

    fCLK

    2 Je b R2

    R1e b 1

    HOLP e Lowpass gain (as fx 0)

    e b

    R2

    R1a 1Je b 2

    HOBP e Bandpass gain (at fe fo)

    e b R3

    R21 a

    R2

    R1Je b 2R3

    R2JCircuit dynamics HOBP e (HOLP) c Q e (HOAP a 1) Q

    Due to the sampled data nature of the filter a s light mismatch of fzand fooccurs causing a 04 dB peaking around foof the allpass filter amplitude

    response (which theoretically should be a straight line) If this is unaccept-

    able Mode 5 is recommended

    TL H506620

    FIGURE 11 MODE 3a

    TLH 5066 21

    FIGURE 12 MODE 4

    9

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    20 Modes of Operation (Continued)

    MODE 5Numerator Complex Zeros BPL P(See Figure 13)

    fo e 01 a R2

    R4c

    fCLK

    100or01a

    R2

    R4c

    fCLK

    50

    fz e

    01 b

    R1

    R4

    c fCLK

    100

    or

    01 b

    R1

    R4

    c fCLK

    50

    Q e 01 a R2R4 c R3

    R2

    Qz e 01 b R1R4 c R3

    R1

    H0z1 e gain at CZ output (as fx 0 Hz)e

    b R2 (R4b R1)

    R1 (R4a R2)

    H0z2 e gain at CZ output

    as fx

    fCLK

    2 Jeb R2

    R1

    HOBP e b e

    R2

    R1a 1Jc

    R3

    R2

    HOLP e b R2 a R1

    R2 a R4Jc R4

    R1

    MODE 6aSingle PoleHPLP Filter (See Figure 14)

    fc e cutoff frequency of LP or HP output

    e R2

    R3

    fCLK

    100or

    R2

    R3

    fCLK

    50

    HOLP

    e b R3

    R1

    HOHP e bR 2

    R1

    MODE 6b Single Pole LP Filter (Inverting and Non-Inverting) (See Figure 15 )

    fc e cutoff frequency of LP outputs

    j R2

    R3

    fCLK

    100or

    R2

    R3

    fCLK

    50

    HOLP1e 1 (non-inverting)

    HOLP2e b

    R3

    R2

    TLH506622

    FIGURE 13MODE 5

    TLH506623

    FIGURE 14MODE 6a

    TLH506624

    FIGURE 15 MODE 6b

    10

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    20 Modes o f Operation (Continued)TABLE I Summary of Modes Realizable filter types (e glow-pass) denoted by asterisks Unless otherwise noted

    gains of various filter outputs are inverting and adjustable by resistor ratios

    Mode BP LP HP N AP Nu mb er o f A d ju stab le

    Notesresist ors fCLKf o

    1

    3 No

    (2) May need input buf-

    1a HOBP1e b Q HOLPe a 1 2 No fer P oor dynamics

    HOBP2e a 1 for highQ

    Yes (above

    2

    3 fCLK50or

    fCLK100)

    Universal State-

    3

    4 Yes Variable Filter Best

    general-purpose mode

    As above butalso

    3a

    7 Yes includes resistor-

    tuneable notch

    Gives Allpass res-

    4

    3 No ponse with HOAPe b 1

    and HOLPe b 2

    Gives flatter allpass

    5

    4 response than above

    if R1e R2e 002R4

    6a

    3 Single pole

    (2)

    6b HOLPe a 1 2 Single pole

    HOLP2eb R3

    R2

    30 Applications InformationThe MF5 is a general-purpose second-order state variable

    filter whose center frequency is proportional to the frequen-cy of the square wave applied to the clock input (fCLK) Byconnecting pin 9 to the appropriate DC voltage the filtercenter frequency focan be made equal to either fCLK100

    or fCLK50 fo can be very accurately set (withing 06%)byusing a crystal clock oscillator or can be easily varied overa wide frequency range by adjusting the clock frequency If

    desired the fCLKfo ratio can be altered by external resis-tors as in Figures 91011 13 14 and 15 The filter Q andgain are determined by external resistors

    All of the five second-order filter types can be builtusing theMF5 These are illustrated inFigures 1 through5 along withtheir transfer functions and some related equationsFigure6 shows the effect of Q on the s hapes of these curvesWhen filter orders greater than two are desired two or moreMF5s can be cascaded The MF5 also includes an uncom-mitted CMOS operational amplifier for additional signal pro-

    cessing applications

    31 DESIGN EXAMPLE

    An example will help illustrate the MF5 design procedure

    For the example we will design a 2nd order Butterworthlow-pass filterwith a cutoff frequencyof 200 Hz and a pass-band gain ofb 2 The circuit will operate from a g 5V powersupply and the clock amplitude will be g 5v (CMOS) levels)

    From the specifications the filter parameters are

    foe 200 Hz HOLPe b 2 and for Butterworth responseQe 0707

    In section 20 are several modes of operation for the MF5each having different characteristics S ome allow adjust-ment of fCLKfo others produce different combinations offilter types some are inverting while others are non-invert-

    ing etc These characteristics aresummarizedin Table I Tokeep the example simple we will use mode 1 which hasnotch bandpass and lowpass outputs and inverts the sig-nal polarity Three external resistors determine the filters Q

    and gain F rom the equations accompanying Figure 7Qe R3R2 and the passband gain HOLP e b R 2R1 Sincethe input signal is driving a summing junction through R 1

    the input impedance will be equal to R1 Start bychoosing avalue forR 1 10k is convenientand gives a reasonable inputimpedance For HOLP e b 2 we have

    R2e b R1HOLP e 10k c 2 e 20k

    For Q e 0707 we have

    R3e R2Q e 20k c 0707 e 1414k Use 15k

    For operation on g 5V supplies Va

    is connected to a 5VVb to b 5V and AGND to ground The power suppliesshould be clean (regulated supplies are preferred) and01mF bypass capacitors are recommended

    11

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    30 Applications Information (Continued)

    TLH506625

    FIGURE 16 2nd-Order Butterworth Low-Pass Filter of Design

    ExampleForf CLK

    f0e 50Connect Pin 9 to a 5Vand

    Change Clock Frequency t o 10 kHz

    TLH506626

    FIGURE 17 Butterworth Low-Pass Circuit of Examplebut Designed fo r Single-Supply Operation

    12

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