May 31, 2017U. GoerkeAPP-HVP-LPC

Active Clamp Flyback Power Stage Design Calculations for use with UCC28780 ACF controller

Work in progress. Useable,but not finalized.

User Inputs are in yellow highlights. Calculation results are in boxes.

Do not change anything except the User Inputs or you'll screw up the design and the calculator tool.It is good practice to keep an unedited "master file" of this tool for reference and only edit copies of it.

Design power stage for Transition Mode, QR-ZVS operation at minimum input, maximum load.fSW design goal is selected at min line, max load (will increase at max line, max load).

Definitions: mΩ 0.001Ω

Input parameters of design:

VACmax 265V <== Enter maximum rms input voltage for normal running.

VACmin 85V <== Enter minimum rms input voltage for normal running.

VACswell 300V <== Enter maximum rms input voltage allowed for swell, no shut down.

VACstart 75V <== Enter minimum rms input voltage for start-up.

fLINEmax 63Hz<== Enter the maximum to minimum line frequencies over which the converter isexpected to operate.fLINEmin 47Hz

VACmaxpeak VACmax 2 374.767V VACswellpk VACswell 2 424.264V

VACminpeak VACmin 2 120.208V VACstartpk VACstart 2 106.066V

Output parameters of design:

VOUTnom 20.0V <== Enter nominal output voltage and regulation accuracy expected, in ± percent.

Tol_Vo 2% VOUTmax VOUTnom 1 Tol_Vo( ) 20.4 V This is regulation, not the OVP limit.

VOUTmin VOUTnom 1 Tol_Vo( ) 19.6 V

IOUTnom 2.25A <== Enter nominal rated output current.

POUTnom VOUTnom IOUTnom 45 W

ηmin 0.93 <== Enter minimum efficiency required at rated maximum load, minimum line.

(Example: ηmin>93% at 45W output, 85Vac, for >15W/in3.)

KOPP 110% <== Enter value for percentage of rated power at which Over-Power Protection (OPP)should begin. Sustained output power above this factor operates for 160 ms, thenshuts down. NOTE: Output above rated power (over-load) up to OPP may be drawnindefinitely without shutdown. Thermal design should be done for this condition.

POUTmax KOPP POUTnom 49.5 W

ηOPP 0.925 <== Enter estimate of η during over-load operation, possibly lower than ηmin.

PINnom

POUTnom

ηmin48.387 W PINmax

POUTmax

ηOPP53.514 W

Bulk Capacitor Calculations

VBULKmin_tgt 70V <== Enter minimum bulk voltage target at which output regulation must bemaintained. Typical value for adapter application at 85Vac input is ~70V,corresponding to ~58% of peak value, or ~42% bulk ripple. - A higher minimum target increases bulk capacitor size, with reduction inpower stage current stresses. - A lower minimum target reduces bulk capacitor size, with increase inpower stage current stresses.

NHC 0 <== Enter total number of AC-line half-cycles (NHC) to be held-up by bulk capacitance

during line dropouts. Set NHC = 0 if no half-cycle dropout hold-up time is needed.

PINcalc PINnom <== Decide: use PINnom or PINmax ( for OPP) for CBULK calculation.

CBULK_calc

2PINcalc 0.25 0.5NHC1

2πasin

VBULKmin_tgt

VACminpeak

VACminpeak 2V 2 VBULKmin_tgt2

fLINEmin

79.184 μF

CBULK1 39μF <== Choose bulk capacitor value based on standard components commercially available.Total bulk capacitance can be split into multiple parallel capacitors, and not necessarily ofequal capacity. Most common, though, is 2 caps at equal values (often separated by aninductor for differential-mode EMI supression).

CBULK2 39μF

CBULK_tgt CBULK1 CBULK2 78 μF

For conditions: PINnom 48.387 W VACminpeak 120.208 V VBULKmin_tgt 70 V fLINEmin 47 Hz

VBULKmin_chk VBULKmin_tgt

VBULKmin_chk 69.25V <== Iterate VBULKmin_chk up or down until CBULK_check CBULK_tgt= , then stop.

<== If you decide that CBULK_chk is not close enough to CBULK_tgt, adjust one or more of the CBULKx values and repeat the iteration.

CBULK_check 78.01 μF

CBULK_tgt 78 μF

CBULK CBULK_tgt 78 μF

VBULKmin VBULKmin_chk 69.25 V This is the minimum bulk valley voltage that you will get withthe bulk capacitance chosen and at the power level specified.

ΔVBULKrpl VACminpeak 2V VBULKmin 48.958 V

ΔVBULK%rpl

ΔVBULKrpl

VACminpeak 2V41.417 %

Bulk-cap ripple current and peak input current:

VLINE t( ) Vacpk sin 2π fLINE t = ICv CBULK

dVLINEv

dt= IBv

POUT

ηv VBULKv=

Iin_pkv ICv IBv= CBULK 2 π fLINE Vacpk cos 2π fLINE tv POUT

ηv VBULKv=

IBRDG t( ) Iin_pkv

dIBRDG

dtt= Iin_pkv

IBpk Iin_pkv

tpk tvt= valid from tv to tzi;

= 0 from tzi to the next tv.

To find tv, use VBULKv estimate from CBULK calculation, above:

VBULKv VBULKmin 69.25 V

fLINEmin 47 Hztv

asinVBULKv

VACminpeak 2V

2π fLINEmin2.119 ms

VACmin 85 V

tpk

asinVACminpeak

VACminpeak

2π fLINEmin5.319 ms

At max load, low-line (ll), assume:

ηv_ll 0.90 ηpk_ll 0.93 <== Enter estimates of instantaneous conversion efficiency at specific bulk voltage points (valley and peak).

Peak capacitor current is a functionof the dv/dt across the cap at thevalley point.

IC_v CBULK 2 π fLINEmin VACminpeak cos 2π fLINEmin tv 2.244 A

IB_v

POUTnom

ηv_ll VBULKv0.722 A IB_pk

POUTnom

ηpk_ll VACminpeak 2V 0.409 A IC_pk IB_pk 0.409 A

Iinpk_v IC_v IB_v 2.966 A

time intervals

thc1

2fLINEmin10.638 ms

SlopeIB_pk Iinpk_v

tpk tv799.049

A

s tzi tpk

IC_pk

Slope 5.831 ms

point in time tchrg tzi tv 3.712 ms

tzi_pk tzi tpk 0.512 ms

thc_zi thc tzi 4.807 ms

Using triangular waveform approximation:

Average input current may be useful for diode bridgeloss estimation or input power estimations. Note: each diode conducts half of this current.

IBRDGmax_avg

Iinpk_v

2tchrg 2 fLINEmin 0.517 A

RMS input current used to find losses in allfront-end series resistances.IBRDGmax_rms Iinpk_v

tchrg 2 fLINEmin

3 1.012 A

Low-frequency bulk-capacitor rms current is "assembled" by piece-wise summation oflinearized current segments. ("DC component" of load current has been removed.) If the totalbulk cap consists of more than one parallel caps, the rms current is split arithmetically amonsgtthem by the ratios of their values to the total capacitance.

ICrms1

IC_v2

3tpk tv 2fLINEmin 0.711 A

ICrms2

IC_pk2

3tzi_pk 2fLINEmin 0.052 A

ICrms3

IC_pk IB_v 2 IC_pk IB_v

3

thc_zi 2fLINEmin 0.243 A

ICbulk_lf_rms ICrms12

ICrms22

ICrms32

0.753 A

ICbulk1_lf_rms ICbulk_lf_rms

CBULK1

CBULK 0.376 A ICbulk2_lf_rms ICbulk_lf_rms

CBULK2

CBULK 0.376 A

High-frequency switching rms currents also need to be factored into each capacitor's stress. - If no DM inductor is present, total high-frequency switching rms current is split arithmetically amongsteach cap, same as the low-frequency currents. - If a significant DM inductor is placed between them, most high-frequency current affects only thedown-stream bulk cap, and not much to the up-stream cap. In this case the down-stream cap loss wouldbe higher than the up-stream cap loss. Capacitor esr is different at low frequency than at high frequency,so losses are calculated by summing the low-freq esr loss with the high-freq esr loss, using separate lowand high frequency rms currents for each. ESR values for lf and hf also need to be determiend for eachbulk cap.

High-frequency switching current has not yet been determined, so losses cannot be fully calculated. Revisit bulk-cap losses after maximum primary switching rms current is determined.

ICbulk_hf_rms 0.953A <== Set initial value = 0A. Enter calculated value ofhigh-frequency bulk cap rms current from RCS section, below,

after completing design calculations down to that point.

Assumefundame

If no DM inductor is used between bulk caps:

ICbulk_tot_rms ICbulk_lf_rms2

ICbulk_hf_rms2

1.214 A

ICbulk1_tot_rms ICbulk_tot_rms

CBULK1

CBULK 0.607 A ICbulk2_tot_rms ICbulk_tot_rms

CBULK2

CBULK 0.607 A

If a DM inductor is used between bulk caps:

ICbulk1_tot_rms ICbulk1_lf_rms 0.376 A ICbulk1_hf_rms 0A

ICbulk2_tot_rms ICbulk2_lf_rms2

ICbulk_hf_rms2

1.025 A ICbulk2_hf_rms ICbulk_hf_rms 0.953 A

Since lf_esr and hf_esr are different values and the losses are othogonal, it is not useful to considera total bulk rms current. Instead, the lf and hf currents should be kept separate and esr lossesevaluated separately.

ESR loss calculations here...

ESR1_lf 1Ω ESR1_hf 0.1Ω <== Enter values of low-frequency and high frequency esrs foreach bulk capacitor. Values are listed on or derived fromcapacitor datasheet information.ESR2_lf 1Ω ESR2_hf 0.1Ω

PCbulk1_esr_lf ICbulk1_lf_rms2

ESR1_lf 0.142 W

PCbulk1_esr_hf ICbulk1_hf_rms2

ESR1_hf 0 W

PCbulk2_esr_lf ICbulk2_lf_rms2

ESR2_lf 0.142 W

PCbulk2_esr_hf ICbulk2_hf_rms2

ESR2_hf 0.091 W

Other Front-End Series-Resistive Losses

Front-end series resistive losses include: Rfuse, Rinrush, RCM, RDM, Resr which affect max-load efficiency.

Front-end parallel losses include: Rxcap (if any), IMOVlk, IBRDGlk, and ICbulklk, all of which are insignificant at full

power but could significantly affect stand-by losses.

Input Fuse

Max input current is up-rated (with crude approximation) toaccount for operating at full load at just above the start-upvoltage. Does not include operation just below over-power limit.

IFusemax IBRDGmax_rms

VACmin

VACstart 1.146 A

IFuse_rating 2A <== Enter current rating of fuse chosen to protect this application. (This value for re

RFuse 0.032Ω <== Enter resistance from fuse datsheet, adjusted for temperature.

PFuse IBRDGmax_rms2

RFuse 0.033 W

Inrush Current Limiter (if used)

IBRIDGErate

2 PINnom

VBULKmin1.397 A

VF_BRIDGE 0.7V <== Enter average forward voltage of individual bridge diode at expectedjunction temperature at full load.

PBRIDGE VF_BRIDGE IBRDGmax_avg 0.362 W Estimate of full load power dissipation at min line

ISURGEpeak_halfcycle150A

2 <== Enter surge rating of selected bridge. Derated by half.

Minimum "cool" resistance target based upon maximum allowable inrush peak current (limited by bridge diodes).

RINRUSHcool_tgt

VACmax 2

ISURGEpeak_halfcycle4.997 Ω

RINRUSHcool 10Ω <== Enter inrush-limiting NTC resistor nominal "cool" value.

RINRUSHhot 0.34Ω <== Enter inrush resistor "hot" value, based on datasheet curves/data, at IBRDGmax_rms.

PINRUSH IBRDGmax_rms2

RINRUSHhot

347.886 mW

IINRUSHpeak

VACmax 2

RINRUSHcool37.477 A

http://www.newark.com/pdfs/techarticles/ametherm/Ametherm_PPT_FEB07_REV6DistyTutorial.pdf

Energy thermister needs to absorb due to surge at turn on, due to input cap

JRtherm 0.5 CBULK VACmax 2 2 5.478 J

Common-Mode Inductor for EMI Suppression

RCM_choke 0.280Ω <== Enter total series resistance of both windings from inductor datasheet, adjusted for operating temperature.

PCM_choke IBRDGmax_rms2

RCM_choke 0.286 W

Differential-Mode Inductor for EMI Suppression

RDM_choke 0.060Ω <== Enter resistance of winding from inductor datsheet, adjusted for operating temperature.

Current in DM choke is mostly that current whichpeak charges CBULK2 plus the ~dc load current

from CBULK1 between line peaks.

IBRDGmax_rms2

ICbulk1_lf_rms2

0.939 A

PDM_choke IBRDGmax_rms2

ICbulk1_lf_rms2

2

RDM_choke 0.053 W

Flyback Transformer Calculations

Note: For now, this calculation tool does not include methods and equations for the detailed design ofthe actual flyback transformer itself. That task itself is quite involved and requires expertise not availablein this tool at this time. For now, it is assumed that the transformer is designed separately, and thefinal salient parameters are entered into this tool for further calculation dependencies.

Instead, this section of the tool provides target values for turns ratios and magnetizing inductance basedon system-level operating parameters and limits.

Determine Primary-to-Secondary Turns-Ratio

OUTPUT RECTIFIER PARAMETERS

VDRM_rating 150V <== Enter output rectifier blocking voltage rating(whether diode or SR MOSFET) and % derating.

kVdrm_derate 10%

VDRMlim 1 kVdrm_derate VDRM_rating 135 V

VFrect 0V <== Enter average forward voltage drop of output rectifier. If Synchronous Rectification is used, enter 0V.

VDspike 30V <== Estimate the spike voltage on the output diode.

VOUTmax 20.4 V

VOUTmax_turns 22V <== Revise maximum output voltage for turns-ratio calculation purposes, if desired.

PRIMARY MOSFET PARAMETERS

VDSmax_rating 600V <== Enter main MOSFET drain-source voltage rating and % derating.

kVds_derate 10%

VDSlim 1 kVds_derate VDSmax_rating 540 V

VBULKmax VACmaxpeak 374.767 V <== Revise maximum bulk voltage for turns-ratio calculation purposes, if desired.

Reflected voltage allowed, with 50% bufferbetween highest VDS and VDS limit.VRfl_allowed

VDSlim VBULKmax 1.5

110.156 V

VTVSΔ 20V <== Estimate the TVS limiting ∆-voltage on clamp cap (not the TVS rating itself).

NPSideal_min

VBULKmax

VDRMlim VOUTmax_turns VDspike 4.515 NPSideal_max

VDSlim VBULKmax VTVSΔ

VOUTmax_turns VFrect 6.60

NPSrange_center

NPSideal_min NPSideal_max

25.558

NPS is best determined at high line.

Choose target NPS between NPSideal_min and NPSideal-max.

- Lower NPS reduces ISEC rms, "crowds" rectifier VDRM rating, higher PFE;

- Higher NPS reduces IPRI rms, "crowds" main FET BVDSS rating, lower PFE;

Leaning toward higher NPS reduces high-line core loss, with lower Cu loss. This may

help boost high-line efficiency, if efficiency over line is skewed too much to low-line.

NPS 6 <== Enter choice for primary to secondary turns-ratio target. (Technically, this need not be an integral number.)

VRfl NPS VOUTnom 120 V

VDS_high VBULKmax NPS VOUTmax VFrect VTVSΔ 517.167 V

VDS_margin VDSlim VDS_high 22.833 V

VDS_low VBULKmin NPS VOUTmax VFrect VTVSΔ 211.65 V

One reason to choose an NPS above the center of the range is to ensure that the minimum on-time of the main

switch at high-line, light-load conditions is greater than the primary controller leading-edge-blanking period.Higher NPS allows a shorter demagnetization time of the transformer, relative to the on-time. At very high

frequencies (as presumed with GaN designs) the minimum on-time of the controller becomes a significantfraction of the total switching period. A minimum inductance is necessary to ensure that tONmin is long enough

to keep Ipk controllable at highest line, lowest current sense peak limit. Since much is still unknown at thispoint, this condition will have to be a checked at a later time to verify compliance.

Determine Primary-to-Auxiliary Turns-Ratio

During the flyback interval, the secondary output voltage is reflected to the auxiliary winding, scaledby the auxiliary-to-secondary turns-ratio NAS. The minimum bias voltage required by the primary-side

controller and gate-driver ICs is used to determine NAS, which then determines NPA.

Although it is convenient to use NAS to translate conditons on the secondary to the auxiliary winding,

transformer specifications commonly specify the turns of all other windings as a ratio to the primarywinding only. Hence, NPS and NPA are usually specified, but NAS is not.

VDD_min 12V <== Enter minimum bias voltage required during steady-state operation.

VF_bias 0.9V <== Enter average forward voltage drop of auxiliary winding rectifier.

VOUT_min_vdd 18V <== Enter minimum output voltage at which VDD = VDD_min.

VF_out 0.0V <== Enter average forward voltage drop of output winding rectifier. If SR is used, set to 0V.

NAS_min represents the minimum value for NAS.

Actual whole-number turns on the final transformerdesign will determine the final NAS value.

NAS_min

VDD_min VF_bias

VOUT_min_vdd VF_out0.717

Tentative primary-to-auxiliary ratio NPA_tent is based on the calculated minimum NAS-min.

Final primary-to-auxiliary ratio NPA is determined by actual whole-number turns on the final

transformer design.

NPA_tent

NPS

NAS_min8.372

From a simplified, idealized point of view, the transformer magnetizing inductance LM can be derived from the

well-known relationship PIN 0.5 LM Ipk2

fmin= , provided fmin

and Ipk

are known. The peak inductor current Ipk

can be substituted with a term based on input and output voltages and duty-cycle, and fmin can be specified bythe designer.

However, the Active-Clamp Flyback topology uses zero-voltage switching (ZVS) to minimize switching losses,which introduces a portion of a resonant cycle into the switching period which deviates the actual frequency tobelow the expected fmin. In low-frequency designs (f < ~100 kHz), this deviation is usually small enough to beneglected and a first-pass estimate of LM is fairly close to the actual final value and the actual fmin is fairly closeto the expected fmin. But in high-frequency designs (f > ~200 kHz), the resonant interval constitutes a significant portion of theswitching period and large errors in LM and/or fmin can result if this is not taken into account. Consequently,some inital estimation followed by iteration is required to minimize discrepancies between calculated and

some inital estimation followed by iteration is required to minimize discrepancies between calculated andmeasured results.This effect is considerably greater in designs using SJ-MOSFETs (with highly non-linear COSS) compared tothose using GaN MOSFETs.

The resonant frequency which generates the ZVS interval is dependent on the total switched-node capacitance atthe drain terminal of the primary switching MOSFET. To complicate matters, this capacitance comprises theaggregate time-related effective COSS of the main switch, the clamp switch, and the output rectifier (reflected tothe primary), plus the winding capacitances and any reflected snubber caps. The effective COSS is calculatedbased on MOSFET datasheet parameters and circuit conditions.

Therefore, some decisions must be made up front concerning the choices of MOSFETs and diodes or SR-Fetsfor the converter and switching frequency, based on previous experience or educated estimations.

Calculation of Effective COSS

For silicon Super-Junction MOSFETs (SJ-Fets), the COSS is highly non-linear with drain voltage

with very large value at low VDS, and a time-related effective COSStr must be found.

For GaN MOSFETs (GaN-Fets), the COSS is still non-linear but not so dramatic, and the value

is small (compared to SJ-Fets). However, the same process can be used.

Note: effective COSS varies slightly with bulk voltage, being larger at low-V.

For purposes of determining LM, effective COSS should be calculated at the condition where the

bulk voltage is minimum.

From MOSFET datasheet, determine a 2-level piece-wise linear approximation of COSS with "big"

capacitance and "small" capacitance values, changing at a threshold voltage Vth(Coss).

Example, for Infineon IPP60R180C7 device (600V, 180mΩ, C7) at bulk voltage of ~70V.

Vth_Coss 22V Coss_bg 5000pF Coss_sm 22pF <== Enter MOSFET simplified COSS

parameters from datasheet curve. VBULKtr VBULKmin 69.25 V

COSStr_FET Coss_bg1

πacos 1

Vth_Coss

VRfl

acos 1Vth_Coss

VBULKtr

Coss_sm 1 acos 1Vth_Coss

VRfl

ac

Note: This COSStr_FET is the combined total of the upper and lower primary-side MOSFETs' effective capacitances.

Total effective time-related switched node capacitance CSWNtr is the sum of COSStr from both primary

MOSFETs, transformer winding capacitance CP, and reflected secondary capacitances COSStr_rect

(output rectifier may be diode or SR Fet) and any snubber capacitance Crect_snb.

Note: in high-frequency transformers, CP can be quite low (2.5pF for example).

CP 3pF <== Enter value of transformer primary winding capacitance.

COSS_Qs 2pF <== Enter value of depletion-mode MOSFET Qs COSS.

CDboot 10pF <== Enter value of high-side driver boot diode capacitance.

COSStr_rect 567pF <== Enter equivalent time-related rectifier capacitance.

Crect_snb 100pF <== Enter value of rectifier snubber capacitance (if any).

CSWNtr COSStr_FET CP COSS_Qs CDbootCOSStr_rect Crect_snb

NPS2

0.949 nF

fSWmin 250kHz <== Enter target minimum switching frequency at maximum load, minimum line.

tSWmax1

fSWmin4 μs

ηX 0.95 <== Enter efficiency of conversion at input to transformer (due to losses, excluding front-end losses).

PX

POUTmax

ηX52.105 W <== Decide: use POUTnom or POUTmax ( at OPP) for LM calculation.

kres 0.19265 <== Enter estimate of fraction of overall maximum switching period whichconstitutes the resonant half-cycle (valid only at low-line, max load). <== Iterate for check, below.

LMmax

kZmax π CSWNtr kZmax π 2CSWNtr 4 2PX

1 kres 1

VBULKmin

1

VRfl

2

tSWmax

2 2PX

1 kres 1

VBULKmin

1

VRfl

2

2

48.24 μ

PX 52.105 W

Assumes +/-10% tolerance on LM.

Following kres iteration, use this

value for most follow-on calculations.

LMnom

LMmax

1.1043.854 μH

Check: Iterate kres until tres ttest=

If tres > ttest, increase kres, elsedecrease kres, until they are equal.

tres kZmax π LMmax CSWNtr 0.771 μs

ttest kres tSWmax 0.771 μs

Estimate primary leakage inductance of transformer (using arbitrary assumption as 2% of LM):

Lk 0.02 LMnom 0.877 μH

Estimation of RCS

tONmax tON

VCSTopp1 0.6V= IPP RCS= IPP

VBULKmin

LMDMAX tSWmax=

VCSTopp1 0.6V

Dmax

tONmax

tSWmax0.512

Note: This is an estimate for RCS used to proceed

with follow-on power stage calculations. A moreaccurate calculation of RCS will be done later in the

control design section, after additional refiningparameters have become known.

RCS_tgt

VCSTopp1 LMmax

VBULKmin Dmax tSWmax0.204 Ω

RCS 0.200Ω <== Enter actual value of current-sense resistance used (often made of several resistors in parallel). This value should be less than, but close to RCS_tgt.

RCS value may need to be adjusted empirically during prototype testing for optimum performance.

This value of RCS is also used to help select the primary-side MOSFETs.

IPP_max

VBULKmin

LMmaxDmax tSWmax 2.94 A

IPrms_max IPP_max

Dmax

3 1.214 A IPavg_max 0.5 IPP_max Dmax 0.752 A

<== Use this result for high-frequency ripple currentcalculation in the bulk capacitor section, above.ICbulk_hf_rms IPrms_max

2IPavg_max

2 0.953 A

PRcs_max IPrms_max2RCS 0.295 W <== Maximum power loss in current-sense resistor at low-line,

over-power condition. This loss (at these conditions) is NOTused for average efficiency calculations. Ensure that RCS resistors used are rated for this power loss.

50% derating is often used for good margin.

Selecting Primary MOSFETs

Choose primary-side MOSFETs that have the same or similar RDS(on) values as RCS.

Examples: - For GaN implementation, choose XXXXXXX, or similar. - For SJ-Fet implementation, choose Infineon C7 series at 600V (internal tests show 600-V C7 parts haveminimal COSS hysteresis loss; 650-V C7 parts do not). Selected: IPL60R185C7 device (600V, 185mΩ, C7) in

ThinPAK 8x8 SMD package for both main switch QL (lower) and clamp switch QH (higher).

RDSon_QL 180mΩ <== Enter on-resistance of MOSFET selected for QL.

kRθ_QL 1.22 <== Enter adjustment factor for QL junction temperature rise. Assume 30C rise (includes ambient rise).

RDSon_QL kRθ_QL RDSon_QL 0.22 Ω

PQL_max IPrms_max2RDSon_QL 0.324 W

<== Enter thermal resistance of QL MOSFET based onheatsinking provided or anticipated. RθJA_QL

62K

W

Trise_QL PQL_max RθJA_QL 20.076 K Less than 30K rise; Okay.

Clamp capacitor current is anticipated to be shaped similar to a half-cosine wave, based on resonatingwith the leakage inductance of the transformer. This approximation is used to estimate the rms currentand power loss in the clamp MOSFET "QH".

ICLAMPrms_max IPP_max

1 Dmax Dres

2 1.13 A

RDSon_QH 180mΩ <== Enter on-resistance of MOSFET selected for QH.

kRθ_QH 1.22 <== Enter adjustment factor for QH junction temperature rise. Assume 30C rise (includes ambient rise).

RDSon_QH kRθ_QH RDSon_QH 0.22 Ω

PQH_max ICLAMPrms_max2RDSon_QH 0.28 W

<== Enter thermal resistance of QH MOSFET based onheatsinking provided or anticipated. RθJA_QH

62K

W

Trise_QH PQH_max RθJA_QH 17.378 K Less than 30K rise; Okay.

Note: - Losses for average efficiency calculations must be based on operating conditions at 230 Vac and 115 Vac. - Losses for power density and case-temp requirements must be based on nominal POUT and low-line.

- Losses for abnormal case-temp rise must be based on single-fault conditions as defined in the pertinentsafety standard for the product.

Clamp Capacitor Calculations

This value for CCLAMP is an initial estimate and may

need to be increased or decreased for optimalperformance during prototype evaluation.

CCLAMP1

π2Lk

tSWmax VBULKmin

VBULKmin VRfl

2

0.247 μF

CCLAMPnom 0.2μF <== Enter nominal value of clamp capacitance selected, for reference.

<== Enter actual value of clamp capacitance, including any reduction due to dc biasvoltage and temperature effects, based on dielectric properties.

CCLAMP 0.099μF

Clamp capacitor: put SMAJ120A TVS in parallel for max clamping, also put R inparallel with 3xRC equal to 1.4 seconds for discharge.

tCLAMPdchg 1.4s

CCLAMP 0.099 μF

RCLAMPdchg

tCLAMPdchg

3 CCLAMP4.714 MΩ

RCLAMPdchg 4.7MΩ <== Enter actual value of discharge resistance selected.

Make sure discharge resistor is rated to sustain the maximum clamp voltage.

Steady-state RCLAMP loss affects stand-by power dissipation.

PRclamp

NPS VOUTnom 2RCLAMPdchg

3.064 mW

Secondary-side Current to Rectifier (Diode or SR)

VSECmax VOUTmax

VACmaxpeak

NPS

82.861 V

ISPπ

2IOUTnom

1

1 Dmax Dres 11.963 A

ISEC_rmsπ

2IOUTnom

1

2 1 Dmax Dres 4.598 A

ISEC_avg ISP2

π 1 Dmax Dres 2.25 A <== Check: Based on half-sine wave-shape

approximation, ISEC_avg should = IOUTnom.

If not, then ISP (and ISEC-rms) are incorrect. IOUTnom 2.25 A

If Synchronous Rectification (SR) is implemented, use the rms current for loss calculation.If diode rectification is used, use the average current for loss calculations.

For SR control, ensure that the SR-Fet is not too big for the controller to drive. Excessivelylow RDS(on) value generally comes at the expense of high CISS capacitance. This can require

high average gate current when operating at high frequencies. Gate-drive losses may exceedSR conduction losses! Be sure that the SR controller can reliably deliver that average currentwithout overheating itself.

Assume UCC24612 SR controller will be used.

Select Infineon BSC160N15NS5 MOSFET (150V, 16mΩ , SON-8 pkg) for SR.

RDSonSR 16mΩ <== Enter on-resistance of MOSFET selected for SR.

kRθ_SR 1.19 <== Enter adjustment factor for SR junction temperature rise. Assume 30C rise (includes ambient rise).

RDSonSR kRθ_SR RDSonSR 19.04 mΩ

PSR_max ISEC_rms2RDSonSR 0.403 W

RθJA_SR52K

W <== Enter thermal resistance of SR MOSFET based on

heatsinking provided or anticipated.

Trise_SR PSR_max RθJA_SR 20.931 K Less than 30K rise; Okay.

CISS_SR 2000pF

QG_SR_tot 16nC <== Enter total gate charge (from DS) at VGS being delivered.

For an example, a 12-V zener diode is used to drop VOUT = 20-V down to ~8V

to keep total charge level lower than if the full 20 V was applied to the controller.It also moves some of the total loss into the zener instead of all in the controller,which may have very limited thermal dissipation capabilites.

Vzener 12V <== Enter value of voltage-dropping zener, if any.

IG_avg QG_SR_tot 500 kHz 8 mA

IDD_IC_avg 1mA

IDD_tot IDD_IC_avg IG_avg 9 mA

PDD_SR_tot IDD_tot VOUTnom 0.18 W <== Total power used to run the SR and SR controller atmid-load, high-line (where switching frequency is highest).

Pzener IDD_tot Vzener 0.108 W

PIC_tot IDD_tot VOUTnom Vzener 0.072 W

RθJA_IC450K

W <== Enter thermal resistance of SR controller (SOT-23-5). Rθ value is a guess,

not from DS (yet).

Trise_SR_IC PIC_tot RθJA_IC 32.4 K Less than 35K rise; Okay.

For further information on using the UCC24612 SR controller, refer to the application section of its datasheet.

Output Capacitor

Output capacitance COUT is determined by evaluating several factors and choosing the largest of the results.

- Minimum COUT value must be enough to meet transient specification for the falling dv/dt of VOUT due to a given

load step until the voltage-control loop can respond to restore regulation. - COUT component(s) chosen must provide the output voltage ripple requirement imposed by the system

requirements. ESR and COUT values contribute to this.

- COUT component(s) chosen must be rated for the maximum ripple current imposed by the system.

Transient response time ∆ttrans may be estimated from the target loop cross-over frequency

fxo, if that is known. Since the poles of the secondary-side shunt controller and the

opto-coupler factor into the ultimate loop-crossover frequency, this initial target value must bechecked after further design and testing to verify the assumption, or modify it and iterate.

ΔILoad_step IOUTnom 2.25 A <== Enter load-step magnitude for transient response.

fxo_tgt 3kHz <== Enter target loop cross-over frequency for transient response.

Δttrans0.35

fxo_tgt50μs 166.667 μs

ΔVtrans_max 1.00V <== Enter maximum transient voltage deviation for transientresponse.

ΔVesr_est 0.1V <== Enter deviation due to current step across estimated esr.

COUT_min_trans

ΔILoad_step Δttrans

ΔVtrans_max ΔVesr_est416.667 μF

COUT selected must endure the following rms ripple current at high switching frequency, regardless of value.

ICout_rms ISEC_rms2

IOUTnom2

4.01 A

COUT_min_rms 330μF <== Enter value of the smallest capacitor or parallel collection of capacitorswhose combined high-freqency rms current ratings sum to the calculated value. (Default initial value = 0 μF.)

COUT selected must provide the following maximum pk-to-pk ripple voltage at high switching frequency,

regardless of value. An L-C post filter can help achieve this, but the filter inductor's resistance will contributeto losses which degrade efficiency. Assuming that high efficiency is an over-riding concern, this calculationassumes that no inductor is used between paralleled output capacitors.

ΔVripple_max 0.050V <== Enter maximum peak-to-peak ripple voltage allowed by systemspecification.

More equations here (TBD), dealing with esr and peak cap current.

COUT_min_rpl 0μF <== Enter value of the smallest capacitor or parallel collection of capacitorswhose combined esrs and values conform to the target ripple specification. (Default initial value = 0 μF.)

Choose the maximum result of the previous minimum-value calculations, and apply margin factor (if any) todetermine the final total value for COUT.

kmargin 1.5 <== Enter margin factor for output capacitance.

COUT max COUT_min_trans COUT_min_rms COUT_min_rpl kmargin 625 μF

UCC28780 ACF controller allows operation up to over-power protection (OPP) limitindefinitely, and above that limit for 160 ms. The OPP limit curve varies with inputline voltage maintain roughly constant power limiting, but may be adjusteddownward somewhat by the ROPP setting (value of series resistor at CS input).

See control section of design calculator.)

NOTE: Converter may be operated indefinitely up to just below the OPP level(without tripping the 160-ms time limit), so thermal design should take this intoaccount. Also, adjust power stage design if regulation and transient response isrequired over the full input line range at just under the OPP limit.(For example, if bulk cap is sized only for nominal power, VOUT may fall out of

regulation during over-power operation at low-line, and transformer inductancemay be too high, so fSW will fall lower than expected.)

Unless otherwise specified, efficiency is usually measured at 230Vac, 50Hz or115Vac, 60Hz for regulatory agency compliance purposes. For compliance to safety standards, external case temperature rise limits maydrive the minimum efficiency required at rated output power.

AC line input is a sine wave. Bridge rectification peak-charges the bulkcapacitors and between peaks, the bulk voltage droops semi-linearly to a pointVLINEv on the next half-cycle ascending wavefront. This intersection point is

referred to as the bulk voltage "valley". The peak bridge current at this valleypoint is a function of the bulk capacitance value CBULK and the dv/dt of the input

voltage at that point, plus the bulk current to the load just prior to that valley pointIBv. The highest peak input current occurs at maximum load, of course, and at

maximum dv/dt, which occurs at the valley point during lowest line operation.

In high-density converters, losses are minimized and input resistances are lowenough to allow approximation of the input current as a triangular waveform withnearly vertical rise and nearly constant slope fall. (As input resistanceincreases, this approximation suffers from rounding at the current peak and morecurvature on the down-slope.) Assuming low series resistance, the current atseveral time points along the votlage waveform can be determined and used toobtain average and rms values for the input current.

These time points are t = 0, tv, tpk, and tzi, which correspond to the start of the

half-sine, the valley intersection point, the sine peak, and the point when inputcurrent goes to zero, respectively. The input current down-slope does notactually reach zero at the peak of the line, but a short time after the peak. At thevoltage peak, the input current is equal to the average power stage load current,so the bulk capacitor current is zero. This can be seen by noting that at thevoltage peak, dv/dt = 0, so CBULKdVc/dt = 0. Therefore, all load current going to

the power stage must be equal to the current coming in from the diode bridge. With tv, tpk, Iin_pkv and IBpk, the down-slope can be calculated, and from that

slope, tz can be found. From that wave shape, the average and rms input and

low-frequency capacitor currents be calculated with close approximation. In fact,they will be very slightly overstated, for conservative loss estimations.

s all hf current isental, no harmonics.

Temporary "made-up" values for esrs.Enter real values when known.

eference only; not used for any calculation.)

Because the MOSFET parameters affect the power stage and controldesign in several ways, it is difficult to choose the optimal MOSFETin asingle step. Therefore, the following selection guide may beuseful to narrow down the choices to start with for certain powerlevels. Iterative refinements can follow, based on the results of theinitial selection. (Note: Lowest available RDS(on) is not necessarily

the best choice because COSS may then become an excessively high

parameter, affecting power stage and control trajectories.)

SJ-MOSFET quick selection guide:

For ~30 W nominal rated output power level, use: Infineon IPxxxx, or equivalent.

For ~45 W nominal rated output power level, use: Infineon IPx60R180C7, or equivalent.

For ~65 W nominal rated output power level, use: Infineon IPx60R120C7, or equivalent.

cos 1Vth_Coss

VBULKtr

2

915.646 pF

If the resonance interval was a complete half-cycle, tres would equal π LC, but it is not a

complete half-cycle. Rather it is a portion of a half-cycle followed by a linear interval. Thishappens when VBULK is less than VRfl and the resonance tries to ring below ground (to -VRflwith respect to VBULK), but the body-diode of the main MOSFET clamps the ringing voltageto GND. The following expression captures this situation by modifying the "π" term with akZ factor which subtracts out the non-half-cycle time portion and adds in the linear timeportion, and scales to π. Generally, kZ > 1 for VBULK < VRfl. Find kZmax at VBULKmin.

kZmax

π acosVBULKmin

VRfl

1

VBULKmin

VRfl

21

π1.146

PX 52.105 W

VBULKmin 69.25 V1 kres 0.807

VRfl 120 V

tSWmax 4 μsPX

1.10POUTnom

ηX 1 kres 052.105 W

CSWNtr 949.174 pF kr 1 kres

μH<== NOT final result! - Result must be checked by iterating kres (above) until ttest = tres.

- Max value only; see nominal value, next equation.For the desired minimum switching frequency this calculation for

For the desired minimum switching frequency, this calculation for LMmax is only valid at low-line, max load conditions!

- Not valid at other line and load conditions, because min frequency will be lower.

Since tSWmax = tSW_TMi + tres and tres is kres of tSWmax, then tSW_TMi = (1-kres)tSWmax.

Check:

tSW_TMi 1 kres tSWmax 3.229 μs fSW_TMi tSW_TMi1

309.655 kHz

tON tSW_TMi

VRfl

VBULKmin VRfl

2.048 μs

tOFF tSW_TMi

VBULKmin

VBULKmin VRfl

1.182 μs

tON tOFF 3.229 μs tres 0.771 μs

tON tOFF tres 4 μs tSWmax 4 μs Dres

tres

tSWmax0.193

OKAY when equal.

Ipkr

VBULKmin

LMmaxtON 2.94 A Pchk 0.5 LMmax Ipkr

2 tSWmax

1 52.105 W

Reminders:

tSWmax 4 106

s

VBULKmin 69.25 V

VRfl 120 V

Lk 8.771 107

H