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Chapter 3: Gate-Level Minimization

Topics in this Chapter:

• The Map Method• Two-Variable Map• Three- Variable Map• Four/Five variable Map• Don’t –Care Conditions• Product of Sums Simplification • Implementing NAND and NOR circuits

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The Map Method

• Truth table of fn is unique but fn can be in many different algebraic forms

• Simplification by using boolean algebra is often difficult because we don’t know how to proceed

•Map method or Karnaugh map (K_Map) is simple and straightforward method that produces minimum number of terms.

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Two-Variable Map

A fn variable have 2n minterms (cells)

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Three- Variable Map• Adjacent cells represent minterms that differs by only one variable.

Therefore, adjacent cells are identical except for one variable that appears complemented in one cell and uncomplemented in the adjacent cell.

• Example : F(x,y,z) = ∑ (2,3,4,5)

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Another example : F(x,y,z) = ∑(3,4,6,7)

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Four variable Map

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Multilevel NAND circuits

To convert multilevel AND-OR to all NAND:

1. Convert all ANDs with AND-invert

2. Convert all ORs with invert-OR

3. Check the bubbles in diagrams if any of them is not compensated by another small circle along the same line insert an inverter (it is one input NAND gate) or complement the input literal

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Implementing NOR circuits

To convert multilevel AND-OR to all NOR:

1. Convert all ORs with OR-invert

2. Convert all ANDs with invert-AND

3. Check the bubbles in diagrams if any of them is not compensated by another small circle along the same line insert an inverter (one input NOR gate) or complement the input literal

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