Digital Logic Design

Chapter 3Gate-Level Minimization

Nasser M. Sabah

Outline of Chapter 3

Introduction

The Map Method

Four-Variable Map

Five-Variable Map

Product of Sums Simplification

NAND & NOR Implementation

Other Two-Level Implementations

Exclusive-OR Function

2

Introduction

Gate-level minimization refers to the design task of finding anoptimal gate-level implementation of Boolean functionsdescribing a digital circuit.

3

The Map Method

The complexity of the digital logic gates

The complexity of the algebraic expression

Logic minimization

Algebraic approaches: lack specific rules

The Karnaugh map

A simple straight forward procedure

A pictorial form of a truth table

A diagram made up of squares

Each square represents one minterm of the function that is to beminimized.

4

Review of Boolean Function

Boolean function

Sum of minterms

Sum of products (or product of sum) in the simplest form

A minimum number of terms

A minimum number of literals

The simplified expression may not be unique

5

Two-Variable Map

A two-variable map

Four minterms

x' = row 0; x = row 1

y' = column 0; y = column 1

A truth table in squarediagram

Figure 3.1 Two-variable Map

Representation of functions in the map

3xy m 1 2 3 ' 'x y m m m x y xy xy

6

Three-Variable Map

A three-variable map

Eight minterms

The Gray code sequence

Any two adjacent squares in the map differ by only on variable.

Primed in one square and unprimed in the other.

e.g., m5 and m7 can be simplified.

Three-variable Map

5 7 ' ( ' )m m xy z xyz xz y y xz

7

Three-Variable Map

m0 and m2 (m4 and m6) are adjacent

m0+ m2 = x'y'z' + x'yz' = x'z' (y'+y) = x'z'

m4+ m6 = xy'z' + xyz' = xz' (y'+y) = xz'

8

Example 3.1

Example 3.1: simplify the Boolean functions:

F(x, y, z) = Σ(2, 3, 4, 5) = x'y + xy'

2 3 4 5

1 1

' ' ' ' ' '

' ( ') '( ' ) ' '

m m m m x yz x yz xy z xy z

x y z z xy z z x y xy

( , , ) (2, 3, 4, 5)F x y z

( , , ) (2, 3, 4, 5) ' 'F x y z x y xy

9

Example 3.2

Example 3.2: simplify the Boolean functions:

F(x, y, z) = Σ(3, 4, 6, 7) = yz + xz'

( , , ) (3, 4, 6, 7)F x y z

( , , ) (3, 4, 6, 7) 'F x y z yz xz

10

Example 3.3

Example 3.3: simplify the Boolean functions:

F(x, y, z) = Σ(0, 2, 4, 5, 6) = z' +xy'

( , , ) (0, 2, 4, 5, 6)F x y z

( , , ) (0, 2, 4, 5, 6) ' 'F x y z z xy

11

Example 3.4

Example 3.4: Let the Boolean function

A'C + A'B + AB'C + BC = C + A'B

( , , ) (1, 2, 3, 5, 7) 'F A B C C A B

a) Express it in sum of minterms.

b) Find the minimal sum of products expression.

' ' 'F A C A B AB C BC

12

Four-Variable Map

The map

16 minterms

Combinations of 16 adjacent squares

Four-variable Map

13

Example 3.5

Example 3.5: simplify the Boolean functions:

' ' ' 'F y w z xz

( , , ) (0,1, 2, 4, 5, 6, 8, 9,12,13,14)F x y z

14

Example 3.6

Example 3-6: simplify the Boolean functions:

ABC + BCD + ABCD + ABC = BD + BC +ACD

' ' ' ' ' ' ' ' ' ' 'F A B C B CD A B C D AB C

15

Prime Implicants

Prime Implicant (PI): a product term obtained by combining

the maximum possible number of adjacent squares

(combining all possible maximum numbers of squares).

Essential Prime Implicant (EPI): a minterm in a square is

covered by only one prime implicant.

16

Prime Implicants

Consider ( , , , ) (0, 2, 3, 5, 7, 8, 9,10,11,13,15)F A B C D The simplified expression may not be unique

' 'B D

D

BDF

AD

C

' '

'

F B

A

D

D

B

B

CD

' '

'

F B

D

C

D

A

B

B

D

' '

'

'

F

B

B D

B

BD

A

C

1 1 1

1 1

1 1

1 1 1 1

00 01 11 10AB

CD

00

01

11

10

1 1 1

1 1

1 1

1 1 1 1

00 01 11 10AB

CD

00

01

11

10

1 1 1

1 1

1 1

1 1 1 1

00 01 11 10AB

CD

00

01

11

10

1 1 1

1 1

1 1

1 1 1 1

00 01 11 10AB

CD

00

01

11

10

17

Essential Prime Implicants

( , , , ) (0, 2, 3, 5, 7, 8, 9,10,11,13,15)F A B C D The partial map shows two essential

prime implicants (EPI), m0 & m5.

Each formed by collapsing four cells

into a term having only two literals.

One term is essential because there is

only one way to include mintem m0

within four adjacent squares (B'D').

Also, there is only one way to include

mintem m5 within four adjacent

squares (BD).

The three mintem that were omitted

from the partial map (m3, m9 & m11)

must be considered next.

m0m5

18

Prime Implicants

( , , , ) (0, 2, 3, 5, 7, 8, 9,10,11,13,15)F A B C D

Minterm m3 can be covered with

either prirme implicant CD or prime

implicant B'C.

Minterm m9 can be covered with

either AD or AB'.

Minterm m11 is covered with any one

of the four prime implicants.

The simplified expression is obtained

from the logical sum of the two

essential prime implicants and any

two prime implicants that cover

mintems m3, m9 & m11.

19

Five-Variable Map

Map for more than four variables becomes complicated Five-variable map: two four-variable map (one on the top of the other).

Five-variable Map

20

# of Adjacent Squares and # of Literals

Table 3.1 shows the relationship between the number of

adjacent squares and the number of literals in the term.

21

Example 3.7

Example 3.7: Simplify the Boolean function

( , , , , ) (0, 2, 4, 6, 9,13, 21, 23, 25, 29, 31)F A B C D E

' ' ' 'F A B E BD E ACE

22

Product of Sums Simplification

Approach #1:

Simplified F' in the form of sum of products.

Apply DeMorgan's theorem F = (F')' .

F': sum of products → F: product of sums.

Approach #2: duality

Combinations of maxterms (it was minterms).

0 1

0 1

( )( )

( ) ( )

' ( )( ')

( ') ' ( )( ') ' ' ' ' ' ' '

' ' '( ' ) ' ' '

' '

'

'

F A B C D A B C D

F F A B

F M M A B C D A B C D

A B C DD A

C D A B C D A B C D A B C D

A B C D D A B C

F A

B C

B C

M M

23

Example 3.8

Simplify the following Boolean function into:

(a) sum-of-products form, and (b) product-of-sums form.

Map for Example 3.8, F(A, B, C, D)= S(0, 1, 2, 5, 8, 9, 10) = B'D'+B'C'+A'C'D

( , , , ) (0,1, 2, 5, 8, 9,10)F A B C D

' ' ' ' ' '

' '

' ;

(

1'

0 '

( )

( )

' ')( ' ')( ' )

Sum of products form SOP

Product of sums form PO

Combine the squares

F B D B C A C D

Combine the squares

F AB CD BD

Apply DeMorgan s theorem

F A

with s

wit

S

B C D B D

h s

24

Example 3.8 (cont.)

Gate implementation of the function of Example 3.8

Sum-of products form Product-of sums form

Gate Implementation of the Function of Example 3.8

25

Sum-of-Minterm Procedure

Consider the function defined in Table 3.2.

Sum-of-minterm:

( , , ) (1,3,4,6)F x y z

( , , ) (0,2,5,7)F x y z

( , , ) ( )( )F x y z x z x z

Taking the complement of F

Combine the 1’s:

( , , )F x y z x z xz

Combine the 0’s:

'( , , )F x y z xz x z 0

Product-of-maxterm:

26

Don’t-Care Conditions

The value of a function is not specified for certain combinations

of variables.

BCD; 1010-1111: don't care.

The don't-care conditions can be utilized in logic minimization.

Can be implemented as 0 or 1.

27

Example 3.9

( , , , ) (1, 3, 7,11,15)F w x y z

which has the don't-care conditions

Simplify the Boolean function

( , , , ) (0, 2, 5)d w x y z

' '

( , , , ) (0,1, 2, 3, 7,11,15)

F yz w x

F w x y z

Either expression is acceptable.

'

( , , , ) (1, 3, 5, 7,11,15)

F yz w z

F w x y z

28

Solution:

OR

NAND and NOR Implementation

NAND gate is a universal gate

Can implement any digital system

Logic Operations with NAND Gates

29

NAND Gate

NAND gate: Invert-OR = NAND

Two Graphic Symbols for NAND Gate

30

Two-level Implementation

Two-level logic

NAND-NAND = sum of products

( ) ( )F AB CD AB CD AB CD

Example: Implement with NAND gateF AB C n yD s o l

31

( ) ( )AB CD

AB CD

( ) ( )AB CD

Example 3.10

Implement the following Boolean function with NAND gates only:

( , , ) (1,2,3,4,5,7)F x y z

( , , )

( ) ( ) '

F x y z xy x y z

xy x y z

xy x y z

32

( ) ( ) 'xy x y z xy x y z

Procedure with Two Levels NAND

The procedure

Simplified in the form of sum of products;

A NAND gate for each product term; the inputs to each NAND gate

are the literals of the term (the first level);

A single NAND gate for the second sum term (the second level);

A term with a single literal requires an inverter in the first level.

33

Multilevel NAND Circuits

Boolean function implementation

AND-OR logic → NAND-NAND logic

AND: NAND + inverter

NAND: inverter + OR

34

( ) 'A CD B BC

NAND Implementation35

( )( )' ' 'AB A B C D

NOR Implementation

NOR function is the dual of NAND function.

The NOR gate is also universal.

Logic Operation with NOR Gates

36

Two Graphic Symbols for a NOR Gate

Two Graphic Symbols for NOR Gate

Example:

( )( )

( )( )

( ) ( ) '

F A B C D

A B C

E

B

E

E

D

A C D

37

( )( )F A B C D E

Example

Example:

' ' '

'

( )( )

( )( )

( ) (

' '

' ' '

' )

)

( ) ( )( ' '

F AB A B C D

AB A B C D

AB A B C D

A B A B C D

38

( )( )' ' ' F AB A B C D with NOR gates

Other Two-Level Implementations

Wired logic

A wire connection between the outputs of two gates.

Open-collector TTL NAND gates: wired-AND logic.

The NOR output of emitter-coupled logic (ECL) gates: wired-OR logic.

( ) ( ) ( ) ( )( )

( ) ( ) [( )( )]

F AB CD AB CD A B C D

F A B C D A B C D

Wired Logic

AND-OR-INVERT function

OR-AND-INVERT function

39

Non-degenerate Forms

16 possible combinations of two-level forms.

The eight degenerate forms = a single operation.

AND-AND, AND-NAND, OR-OR, OR-NOR, NAND-OR, NAND-

NOR, NOR-AND, NOR-NAND.

The eight non-degenerate forms

AND-OR and NAND-NAND = sum of products.

OR-AND and NOR-NOR = product of sums.

NOR-OR, NAND-AND, OR-NAND, AND-NOR = ?

40

AND-OR-Invert Implementation

AND-OR-INVERT (AOI) Implementation.

NAND-AND = AND-NOR = AOI.

AND-OR-INVERT circuits, F = (AB +CD +E)

' ( )( ) '

'

( )

( )  

F AB CD E AB CD E

F AB CD E sum of products

41

OR-AND-Invert Implementation

OR-AND-INVERT (OAI) Implementation. OR-NAND = NOR-OR = OAI.

OR-AND-INVERT circuits, F = ((A+B)(C+D)E)'

[ ]'( )( ) ( '

'

) '

  

( ) '

( )( ) ( )

F A B C D E A B C D E

F A B C D E product of sums

42

Tabular Summary43

Examples 3.11

Implement the function of figure 3.31(a) with the four 2-level

forms listed in Table 3.3.

' ' ' 'F x y z xyz

' ' '

( ' ' ) '

( ' ) '. ( ') '. '

F x y xy z

AND NOR F x y xy z

NAND AND

AND OR INV

F

E

y xy z

T

x

R

' '

( )

' '

' ' '

' ' '

'

( )

[( )( )]

( ) ' ( ) ''

F x y z xyz

F x y z x y z

OR NAND F x y z x y z

NOR OR F x y z x

OR AND I

y

NVE T

z

R

44

Examples

45Other Two-level Implementations

45

Exclusive-OR Function

( ) ( )

A B B A

A B C A B C A B C

Commutative and associative

0

1 '

0

' 1

' ( ) '

' ( ) '

A A

A A

A A

A A

A B A B

A B A B

Some identities

' 'A B AB A B

( ) ' ' 'A B AB A B

Exclusive-NOR (XNOR)

Exclusive-OR (XOR)46

Exclusive-OR Implementations

Implementations

Exclusive-OR Implementations

( ' ') ( ' ') ' 'x y x x y y xy x y x y

47

Odd & Even Function

• XOR is an odd function → an odd number of 1’s → F = 1.

• XNOR is an even function → an even number of 1’s → F = 1.

Map for a Three-variable Exclusive-OR Function

( ' ' ) ' ( ' ')

' ' ' ' ' ' (1, 2, 4, 7)

A B C AB A B C AB A B C

AB C A BC ABC A B C

48

XOR and XNOR

Logic diagram of odd and even functions

Logic Diagram of Odd and Even Functions

49

( )A B C [( ) ]'A B C

Four-variable Exclusive-OR function

Four-variable Exclusive-OR function

Map for a Four-variable Exclusive-OR Function

( ' ' ) ( ' ' )

( ' ' )( ' ') ( ' ')( ' ' )

A B C D AB A B CD C D

AB A B CD C D AB A B CD C D

50

Parity Generation and Checking

Parity Generation and Checking:

Parity bit: P = x y z.

Parity check: C = x y z P.

C = 1: one bit error or an odd number of data bit error.

C = 0: correct or an even number of data bit error.

Logic Diagram of a Parity Generator and Checker

51

Parity Generation and Checking52

Parity Generation and Checking53